diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -27011,6 +27011,12 @@
                          DAG.getConstant(0, dl, MVT::i32),
                          DAG.getConstant(0, dl, MVT::i32));
     }
+    case llvm::Intrinsic::asan_check_memaccess: {
+      // Mark this as adjustsStack because it will be lowered to a call.
+      DAG.getMachineFunction().getFrameInfo().setAdjustsStack(true);
+      // Don't do anything here, we will expand these intrinsics out later.
+      return Op;
+    }
     case llvm::Intrinsic::x86_flags_read_u32:
     case llvm::Intrinsic::x86_flags_read_u64:
     case llvm::Intrinsic::x86_flags_write_u32:
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
@@ -3,18 +3,24 @@
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @load1(i8* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load1_rn[[RN1:.*]]
 ; CHECK:              callq   __asan_check_store1_rn[[RN1]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   call void @llvm.asan.check.memaccess(i8* %x, i32 0)
   call void @llvm.asan.check.memaccess(i8* %x, i32 32)
   ret void
 }
 
 define void @load2(i16* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load2_rn[[RN2:.*]]
 ; CHECK:              callq   __asan_check_store2_rn[[RN2]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i16* %x to i64
   %2 = bitcast i16* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 2)
@@ -23,9 +29,12 @@
 }
 
 define void @load4(i32* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load4_rn[[RN4:.*]]
 ; CHECK:              callq   __asan_check_store4_rn[[RN4]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i32* %x to i64
   %2 = bitcast i32* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 4)
@@ -33,9 +42,12 @@
   ret void
 }
 define void @load8(i64* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load8_rn[[RN8:.*]]
 ; CHECK:              callq   __asan_check_store8_rn[[RN8]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i64* %x to i64
   %2 = bitcast i64* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 6)
@@ -44,9 +56,12 @@
 }
 
 define void @load16(i128* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load16_rn[[RN16:.*]]
 ; CHECK:              callq   __asan_check_store16_rn[[RN16]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i128* %x to i64
   %2 = bitcast i128* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 8)
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -3,18 +3,24 @@
 target triple = "x86_64-pc-win"
 
 define void @load1(i8* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load1_rn[[RN1:.*]]
 ; CHECK:              callq   __asan_check_store1_rn[[RN1]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   call void @llvm.asan.check.memaccess(i8* %x, i32 0)
   call void @llvm.asan.check.memaccess(i8* %x, i32 32)
   ret void
 }
 
 define void @load2(i16* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load2_rn[[RN2:.*]]
 ; CHECK:              callq   __asan_check_store2_rn[[RN2]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i16* %x to i64
   %2 = bitcast i16* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 2)
@@ -23,9 +29,12 @@
 }
 
 define void @load4(i32* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load4_rn[[RN4:.*]]
 ; CHECK:              callq   __asan_check_store4_rn[[RN4]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i32* %x to i64
   %2 = bitcast i32* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 4)
@@ -33,9 +42,12 @@
   ret void
 }
 define void @load8(i64* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load8_rn[[RN8:.*]]
 ; CHECK:              callq   __asan_check_store8_rn[[RN8]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i64* %x to i64
   %2 = bitcast i64* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 6)
@@ -44,9 +56,12 @@
 }
 
 define void @load16(i128* nocapture readonly %x) {
+; CHECK:              pushq   %rax
+; CHECK-NOT:          push    %rbp
 ; CHECK:              callq   __asan_check_load16_rn[[RN16:.*]]
 ; CHECK:              callq   __asan_check_store16_rn[[RN16]]
-; CHECK-NEXT:         retq
+; CHECK-NOT:          pop     %rbp
+; CHECK:              popq    %rax
   %1 = ptrtoint i128* %x to i64
   %2 = bitcast i128* %x to i8*
   call void @llvm.asan.check.memaccess(i8* %2, i32 8)