diff --git a/llvm/lib/Target/X86/CMakeLists.txt b/llvm/lib/Target/X86/CMakeLists.txt --- a/llvm/lib/Target/X86/CMakeLists.txt +++ b/llvm/lib/Target/X86/CMakeLists.txt @@ -44,6 +44,7 @@ X86FixupBWInsts.cpp X86FixupLEAs.cpp X86AvoidStoreForwardingBlocks.cpp + X86DynAllocaExpander.cpp X86FixupSetCC.cpp X86FlagsCopyLowering.cpp X86FloatingPoint.cpp @@ -80,7 +81,6 @@ X86TargetObjectFile.cpp X86TargetTransformInfo.cpp X86VZeroUpper.cpp - X86WinAllocaExpander.cpp X86WinEHState.cpp X86InsertWait.cpp ) diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h --- a/llvm/lib/Target/X86/X86.h +++ b/llvm/lib/Target/X86/X86.h @@ -73,8 +73,8 @@ /// Return a pass that lowers EFLAGS copy pseudo instructions. FunctionPass *createX86FlagsCopyLoweringPass(); -/// Return a pass that expands WinAlloca pseudo-instructions. -FunctionPass *createX86WinAllocaExpander(); +/// Return a pass that expands DynAlloca pseudo-instructions. +FunctionPass *createX86DynAllocaExpander(); /// Return a pass that config the tile registers. FunctionPass *createX86TileConfigPass(); diff --git a/llvm/lib/Target/X86/X86WinAllocaExpander.cpp b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp rename from llvm/lib/Target/X86/X86WinAllocaExpander.cpp rename to llvm/lib/Target/X86/X86DynAllocaExpander.cpp --- a/llvm/lib/Target/X86/X86WinAllocaExpander.cpp +++ b/llvm/lib/Target/X86/X86DynAllocaExpander.cpp @@ -1,4 +1,4 @@ -//===----- X86WinAllocaExpander.cpp - Expand WinAlloca pseudo instruction -===// +//===----- X86DynAllocaExpander.cpp - Expand DynAlloca pseudo instruction -===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file defines a pass that expands WinAlloca pseudo-instructions. +// This file defines a pass that expands DynAlloca pseudo-instructions. // // It performs a conservative analysis to determine whether each allocation // falls within a region of the stack that is safe to use, or whether stack @@ -33,26 +33,26 @@ namespace { -class X86WinAllocaExpander : public MachineFunctionPass { +class X86DynAllocaExpander : public MachineFunctionPass { public: - X86WinAllocaExpander() : MachineFunctionPass(ID) {} + X86DynAllocaExpander() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; private: - /// Strategies for lowering a WinAlloca. + /// Strategies for lowering a DynAlloca. enum Lowering { TouchAndSub, Sub, Probe }; - /// Deterministic-order map from WinAlloca instruction to desired lowering. + /// Deterministic-order map from DynAlloca instruction to desired lowering. typedef MapVector LoweringMap; - /// Compute which lowering to use for each WinAlloca instruction. + /// Compute which lowering to use for each DynAlloca instruction. void computeLowerings(MachineFunction &MF, LoweringMap& Lowerings); /// Get the appropriate lowering based on current offset and amount. Lowering getLowering(int64_t CurrentOffset, int64_t AllocaAmount); - /// Lower a WinAlloca instruction. + /// Lower a DynAlloca instruction. void lower(MachineInstr* MI, Lowering L); MachineRegisterInfo *MRI = nullptr; @@ -64,22 +64,22 @@ int64_t StackProbeSize = 0; bool NoStackArgProbe = false; - StringRef getPassName() const override { return "X86 WinAlloca Expander"; } + StringRef getPassName() const override { return "X86 DynAlloca Expander"; } static char ID; }; -char X86WinAllocaExpander::ID = 0; +char X86DynAllocaExpander::ID = 0; } // end anonymous namespace -FunctionPass *llvm::createX86WinAllocaExpander() { - return new X86WinAllocaExpander(); +FunctionPass *llvm::createX86DynAllocaExpander() { + return new X86DynAllocaExpander(); } -/// Return the allocation amount for a WinAlloca instruction, or -1 if unknown. -static int64_t getWinAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI) { - assert(MI->getOpcode() == X86::WIN_ALLOCA_32 || - MI->getOpcode() == X86::WIN_ALLOCA_64); +/// Return the allocation amount for a DynAlloca instruction, or -1 if unknown. +static int64_t getDynAllocaAmount(MachineInstr *MI, MachineRegisterInfo *MRI) { + assert(MI->getOpcode() == X86::DYN_ALLOCA_32 || + MI->getOpcode() == X86::DYN_ALLOCA_64); assert(MI->getOperand(0).isReg()); Register AmountReg = MI->getOperand(0).getReg(); @@ -93,8 +93,8 @@ return Def->getOperand(1).getImm(); } -X86WinAllocaExpander::Lowering -X86WinAllocaExpander::getLowering(int64_t CurrentOffset, +X86DynAllocaExpander::Lowering +X86DynAllocaExpander::getLowering(int64_t CurrentOffset, int64_t AllocaAmount) { // For a non-constant amount or a large amount, we have to probe. if (AllocaAmount < 0 || AllocaAmount > StackProbeSize) @@ -128,11 +128,11 @@ } } -void X86WinAllocaExpander::computeLowerings(MachineFunction &MF, +void X86DynAllocaExpander::computeLowerings(MachineFunction &MF, LoweringMap &Lowerings) { // Do a one-pass reverse post-order walk of the CFG to conservatively estimate // the offset between the stack pointer and the lowest touched part of the - // stack, and use that to decide how to lower each WinAlloca instruction. + // stack, and use that to decide how to lower each DynAlloca instruction. // Initialize OutOffset[B], the stack offset at exit from B, to something big. DenseMap OutOffset; @@ -153,10 +153,10 @@ if (Offset == -1) Offset = INT32_MAX; for (MachineInstr &MI : *MBB) { - if (MI.getOpcode() == X86::WIN_ALLOCA_32 || - MI.getOpcode() == X86::WIN_ALLOCA_64) { - // A WinAlloca moves StackPtr, and potentially touches it. - int64_t Amount = getWinAllocaAmount(&MI, MRI); + if (MI.getOpcode() == X86::DYN_ALLOCA_32 || + MI.getOpcode() == X86::DYN_ALLOCA_64) { + // A DynAlloca moves StackPtr, and potentially touches it. + int64_t Amount = getDynAllocaAmount(&MI, MRI); Lowering L = getLowering(Offset, Amount); Lowerings[&MI] = L; switch (L) { @@ -195,12 +195,12 @@ return isInt<8>(Amount) ? X86::SUB32ri8 : X86::SUB32ri; } -void X86WinAllocaExpander::lower(MachineInstr* MI, Lowering L) { +void X86DynAllocaExpander::lower(MachineInstr *MI, Lowering L) { const DebugLoc &DL = MI->getDebugLoc(); MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock::iterator I = *MI; - int64_t Amount = getWinAllocaAmount(MI, MRI); + int64_t Amount = getDynAllocaAmount(MI, MRI); if (Amount == 0) { MI->eraseFromParent(); return; @@ -209,7 +209,7 @@ // These two variables differ on x32, which is a 64-bit target with a // 32-bit alloca. bool Is64Bit = STI->is64Bit(); - bool Is64BitAlloca = MI->getOpcode() == X86::WIN_ALLOCA_64; + bool Is64BitAlloca = MI->getOpcode() == X86::DYN_ALLOCA_64; assert(SlotSize == 4 || SlotSize == 8); switch (L) { @@ -271,8 +271,8 @@ AmountDef->eraseFromParent(); } -bool X86WinAllocaExpander::runOnMachineFunction(MachineFunction &MF) { - if (!MF.getInfo()->hasWinAlloca()) +bool X86DynAllocaExpander::runOnMachineFunction(MachineFunction &MF) { + if (!MF.getInfo()->hasDynAlloca()) return false; MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h --- a/llvm/lib/Target/X86/X86ISelLowering.h +++ b/llvm/lib/Target/X86/X86ISelLowering.h @@ -654,8 +654,8 @@ // is needed so that this can be expanded with control flow. VASTART_SAVE_XMM_REGS, - // Windows's _chkstk call to do stack probing. - WIN_ALLOCA, + // A stack checking function call. On Windows it's _chkstk call. + DYN_ALLOCA, // For allocating variable amounts of stack space when using // segmented stacks. Check if the current stacklet has enough space, and diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -25212,8 +25212,8 @@ DAG.getRegister(Vreg, SPTy)); } else { SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); - Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Size); - MF.getInfo()->setHasWinAlloca(true); + Chain = DAG.getNode(X86ISD::DYN_ALLOCA, dl, NodeTys, Chain, Size); + MF.getInfo()->setHasDynAlloca(true); const X86RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); Register SPReg = RegInfo->getStackRegister(); @@ -32343,7 +32343,7 @@ NODE_NAME_CASE(VASTART_SAVE_XMM_REGS) NODE_NAME_CASE(VAARG_64) NODE_NAME_CASE(VAARG_X32) - NODE_NAME_CASE(WIN_ALLOCA) + NODE_NAME_CASE(DYN_ALLOCA) NODE_NAME_CASE(MEMBARRIER) NODE_NAME_CASE(MFENCE) NODE_NAME_CASE(SEG_ALLOCA) diff --git a/llvm/lib/Target/X86/X86InstrCompiler.td b/llvm/lib/Target/X86/X86InstrCompiler.td --- a/llvm/lib/Target/X86/X86InstrCompiler.td +++ b/llvm/lib/Target/X86/X86InstrCompiler.td @@ -153,15 +153,15 @@ // (compared to ordinary calls) like stack pointer change. let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in -def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), +def DYN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size), "# dynamic stack allocation", - [(X86WinAlloca GR32:$size)]>, + [(X86DynAlloca GR32:$size)]>, Requires<[NotLP64]>; let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in -def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), +def DYN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size), "# dynamic stack allocation", - [(X86WinAlloca GR64:$size)]>, + [(X86DynAlloca GR64:$size)]>, Requires<[In64BitMode]>; } // SchedRW diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -112,7 +112,7 @@ def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; -def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; +def SDT_X86DYN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; @@ -294,7 +294,7 @@ def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; -def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, +def X86DynAlloca : SDNode<"X86ISD::DYN_ALLOCA", SDT_X86DYN_ALLOCA, [SDNPHasChain, SDNPOutGlue]>; def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, diff --git a/llvm/lib/Target/X86/X86MachineFunctionInfo.h b/llvm/lib/Target/X86/X86MachineFunctionInfo.h --- a/llvm/lib/Target/X86/X86MachineFunctionInfo.h +++ b/llvm/lib/Target/X86/X86MachineFunctionInfo.h @@ -102,8 +102,8 @@ /// True if this function uses the red zone. bool UsesRedZone = false; - /// True if this function has WIN_ALLOCA instructions. - bool HasWinAlloca = false; + /// True if this function has DYN_ALLOCA instructions. + bool HasDynAlloca = false; /// True if this function has any preallocated calls. bool HasPreallocatedCall = false; @@ -198,8 +198,8 @@ bool getUsesRedZone() const { return UsesRedZone; } void setUsesRedZone(bool V) { UsesRedZone = V; } - bool hasWinAlloca() const { return HasWinAlloca; } - void setHasWinAlloca(bool v) { HasWinAlloca = v; } + bool hasDynAlloca() const { return HasDynAlloca; } + void setHasDynAlloca(bool v) { HasDynAlloca = v; } bool hasPreallocatedCall() const { return HasPreallocatedCall; } void setHasPreallocatedCall(bool v) { HasPreallocatedCall = v; } diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp --- a/llvm/lib/Target/X86/X86TargetMachine.cpp +++ b/llvm/lib/Target/X86/X86TargetMachine.cpp @@ -503,7 +503,7 @@ addPass(createX86SpeculativeLoadHardeningPass()); addPass(createX86FlagsCopyLoweringPass()); - addPass(createX86WinAllocaExpander()); + addPass(createX86DynAllocaExpander()); if (getOptLevel() != CodeGenOpt::None) { addPass(createX86PreTileConfigPass()); diff --git a/llvm/test/CodeGen/X86/O0-pipeline.ll b/llvm/test/CodeGen/X86/O0-pipeline.ll --- a/llvm/test/CodeGen/X86/O0-pipeline.ll +++ b/llvm/test/CodeGen/X86/O0-pipeline.ll @@ -41,7 +41,7 @@ ; CHECK-NEXT: X86 speculative load hardening ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: X86 EFLAGS copy lowering -; CHECK-NEXT: X86 WinAlloca Expander +; CHECK-NEXT: X86 DynAlloca Expander ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Fast Register Allocator diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll --- a/llvm/test/CodeGen/X86/opt-pipeline.ll +++ b/llvm/test/CodeGen/X86/opt-pipeline.ll @@ -116,7 +116,7 @@ ; CHECK-NEXT: X86 speculative load hardening ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: X86 EFLAGS copy lowering -; CHECK-NEXT: X86 WinAlloca Expander +; CHECK-NEXT: X86 DynAlloca Expander ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction ; CHECK-NEXT: Tile Register Pre-configure diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn --- a/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn @@ -85,6 +85,7 @@ "X86CmovConversion.cpp", "X86DiscriminateMemOps.cpp", "X86DomainReassignment.cpp", + "X86DynAllocaExpander.cpp", "X86EvexToVex.cpp", "X86ExpandPseudo.cpp", "X86FastISel.cpp", @@ -133,7 +134,6 @@ "X86TargetTransformInfo.cpp", "X86TileConfig.cpp", "X86VZeroUpper.cpp", - "X86WinAllocaExpander.cpp", "X86WinEHState.cpp", ] }