diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -36232,7 +36232,7 @@
         Shuffle = ISD::OR;
         SrcVT = DstVT = MaskVT.changeTypeToInteger();
         return true;
-      } else if (NumV1Elts == NumV2Elts && NumV1Elts == NumMaskElts) {
+      } else {
         // FIXME: handle mismatched sizes?
         // TODO: investigate if `ISD::OR` handling in
         // `TargetLowering::SimplifyDemandedVectorElts` can be improved instead.
@@ -36253,6 +36253,11 @@
         KnownBits V1Known = computeKnownBitsElementWise(V1);
         KnownBits V2Known = computeKnownBitsElementWise(V2);
 
+        for (APInt *K :
+             {&V1Known.Zero, &V1Known.One, &V2Known.Zero, &V2Known.One})
+          *K = APIntOps::ScaleBitMask(*K, NumMaskElts,
+                                      APIntOps::BitMergingApproach::Lossy);
+
         for (unsigned i = 0; i != NumMaskElts && IsBlend; ++i) {
           int M = Mask[i];
           if (M == SM_SentinelUndef)