Index: llvm/lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstructions.td
+++ llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -2600,6 +2600,48 @@
                (i32 (EXTRACT_SUBREG SReg_64:$y, sub1))), sub1)
 >;
 
+// min(min(x, y), z)) or max(max(x, y), z)) -> min3(x, y, z) or max3(x, y, z)
+class Int32Min3OrMax3Pat<Instruction min3_or_max3, SDPatternOperator min_or_max,
+                         SDPatternOperator min_or_max_oneuse> : AMDGPUPat <
+  (DivergentBinFrag<min_or_max> (min_or_max_oneuse i32:$src0, i32:$src1),
+                                 i32:$src2),
+  (min3_or_max3 VSrc_b32:$src0, VSrc_b32:$src1, VSrc_b32:$src2)
+>;
+
+class Int16Min3OrMax3Pat<Instruction min3_or_max3, SDPatternOperator min_or_max,
+                         SDPatternOperator min_or_max_oneuse> : GCNPat <
+  (DivergentBinFrag<min_or_max> (min_or_max_oneuse i16:$src0, i16:$src1),
+                                 i16:$src2),
+  (min3_or_max3 SRCMODS.NONE, VSrc_b16:$src0, SRCMODS.NONE, VSrc_b16:$src1,
+                SRCMODS.NONE, VSrc_b16:$src2, DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+
+class FPMin3OrMax3Pat<Instruction min3_or_max3, ValueType vt,
+                      SDPatternOperator min_or_max,
+                      SDPatternOperator min_or_max_oneuse> : GCNPat <
+  (min_or_max (min_or_max_oneuse (VOP3Mods vt:$src0, i32:$src0_mods),
+                                 (VOP3Mods vt:$src1, i32:$src1_mods)),
+              (vt (VOP3Mods vt:$src2, i32:$src2_mods))),
+  (min3_or_max3 $src0_mods, $src0, $src1_mods, $src1, $src2_mods, $src2,
+                DSTCLAMP.NONE, DSTOMOD.NONE)
+>;
+
+def : Int32Min3OrMax3Pat<V_MIN3_I32_e64, smin, smin_oneuse>;
+def : Int32Min3OrMax3Pat<V_MIN3_U32_e64, umin, umin_oneuse>;
+def : Int32Min3OrMax3Pat<V_MAX3_I32_e64, smax, smax_oneuse>;
+def : Int32Min3OrMax3Pat<V_MAX3_U32_e64, umax, umax_oneuse>;
+def : FPMin3OrMax3Pat<V_MIN3_F32_e64, f32, fminnum_like, fminnum_like_oneuse>;
+def : FPMin3OrMax3Pat<V_MAX3_F32_e64, f32, fmaxnum_like, fmaxnum_like_oneuse>;
+
+let SubtargetPredicate = isGFX9Plus in {
+def : Int16Min3OrMax3Pat<V_MIN3_I16_e64, smin, smin_oneuse>;
+def : Int16Min3OrMax3Pat<V_MIN3_U16_e64, umin, umin_oneuse>;
+def : Int16Min3OrMax3Pat<V_MAX3_I16_e64, smax, smax_oneuse>;
+def : Int16Min3OrMax3Pat<V_MAX3_U16_e64, umax, umax_oneuse>;
+def : FPMin3OrMax3Pat<V_MIN3_F16_e64, f16, fminnum_like, fminnum_like_oneuse>;
+def : FPMin3OrMax3Pat<V_MAX3_F16_e64, f16, fmaxnum_like, fmaxnum_like_oneuse>;
+}
+
 multiclass IntMed3Pat<Instruction med3Inst,
                  SDPatternOperator min,
                  SDPatternOperator max,
Index: llvm/test/CodeGen/AMDGPU/GlobalISel/min3-and-max3.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/GlobalISel/min3-and-max3.ll
@@ -0,0 +1,717 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s
+
+; umin3
+
+define i32 @min3_u32(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: min3_u32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min3_u32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+  %umin3 = call i32 @llvm.umin.i32(i32 %umin, i32 %c)
+  ret i32 %umin3
+}
+
+define amdgpu_ps i32 @min3_u32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
+; VI-LABEL: min3_u32_uniform:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_min_u32 s0, s2, s3
+; VI-NEXT:    s_min_u32 s0, s0, s4
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_u32_uniform:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_min_u32 s0, s2, s3
+; GFX10-NEXT:    s_min_u32 s0, s0, s4
+; GFX10-NEXT:    ; return to shader part epilog
+  %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+  %umin3 = call i32 @llvm.umin.i32(i32 %umin, i32 %c)
+  ret i32 %umin3
+}
+
+define i32 @min3_u32_commute(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: min3_u32_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min3_u32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_u32_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+  %umin3 = call i32 @llvm.umin.i32(i32 %c, i32 %umin)
+  ret i32 %umin3
+}
+
+define i16 @min3_u16(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: min3_u16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min_u16_e32 v0, v0, v1
+; VI-NEXT:    v_min_u16_e32 v0, v0, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_u16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_u16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+  %umin3 = call i16 @llvm.umin.i16(i16 %umin, i16 %c)
+  ret i16 %umin3
+}
+
+define i16 @min3_u16_commute(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: min3_u16_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min_u16_e32 v0, v0, v1
+; VI-NEXT:    v_min_u16_e32 v0, v2, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_u16_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_u16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umin = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+  %umin3 = call i16 @llvm.umin.i16(i16 %c, i16 %umin)
+  ret i16 %umin3
+}
+
+; smin3
+
+define i32 @min3_i32(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: min3_i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min3_i32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_i32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+  %smin3 = call i32 @llvm.smin.i32(i32 %smin, i32 %c)
+  ret i32 %smin3
+}
+
+define amdgpu_ps i32 @min3_i32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
+; VI-LABEL: min3_i32_uniform:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_min_i32 s0, s2, s3
+; VI-NEXT:    s_min_i32 s0, s0, s4
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_i32_uniform:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_min_i32 s0, s2, s3
+; GFX10-NEXT:    s_min_i32 s0, s0, s4
+; GFX10-NEXT:    ; return to shader part epilog
+  %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+  %smin3 = call i32 @llvm.smin.i32(i32 %smin, i32 %c)
+  ret i32 %smin3
+}
+
+define i32 @min3_i32_commute(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: min3_i32_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min3_i32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_i32_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_i32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i32 @llvm.smin.i32(i32 %a, i32 %b)
+  %smin3 = call i32 @llvm.smin.i32(i32 %c, i32 %smin)
+  ret i32 %smin3
+}
+
+define i16 @min3_i16(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: min3_i16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min_i16_e32 v0, v0, v1
+; VI-NEXT:    v_min_i16_e32 v0, v0, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_i16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i16 @llvm.smin.i16(i16 %a, i16 %b)
+  %smin3 = call i16 @llvm.smin.i16(i16 %smin, i16 %c)
+  ret i16 %smin3
+}
+
+define i16 @min3_i16_commute(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: min3_i16_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_min_i16_e32 v0, v0, v1
+; VI-NEXT:    v_min_i16_e32 v0, v2, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_i16_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_min3_i16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smin = call i16 @llvm.smin.i16(i16 %a, i16 %b)
+  %smin3 = call i16 @llvm.smin.i16(i16 %c, i16 %smin)
+  ret i16 %smin3
+}
+
+
+; umax3
+
+define i32 @max3_u32(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: max3_u32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max3_u32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_u32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+  %umax3 = call i32 @llvm.umax.i32(i32 %umax, i32 %c)
+  ret i32 %umax3
+}
+
+define amdgpu_ps i32 @max3_u32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
+; VI-LABEL: max3_u32_uniform:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_max_u32 s0, s2, s3
+; VI-NEXT:    s_max_u32 s0, s0, s4
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_u32_uniform:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_max_u32 s0, s2, s3
+; GFX10-NEXT:    s_max_u32 s0, s0, s4
+; GFX10-NEXT:    ; return to shader part epilog
+  %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+  %umax3 = call i32 @llvm.umax.i32(i32 %umax, i32 %c)
+  ret i32 %umax3
+}
+
+define i32 @max3_u32_commute(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: max3_u32_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max3_u32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_u32_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_u32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+  %umax3 = call i32 @llvm.umax.i32(i32 %c, i32 %umax)
+  ret i32 %umax3
+}
+
+define i16 @max3_u16(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: max3_u16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_u16_e32 v0, v0, v1
+; VI-NEXT:    v_max_u16_e32 v0, v0, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_u16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_u16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+  %umax3 = call i16 @llvm.umax.i16(i16 %umax, i16 %c)
+  ret i16 %umax3
+}
+
+define i16 @max3_u16_commute(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: max3_u16_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_u16_e32 v0, v0, v1
+; VI-NEXT:    v_max_u16_e32 v0, v2, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_u16_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_u16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %umax = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+  %umax3 = call i16 @llvm.umax.i16(i16 %c, i16 %umax)
+  ret i16 %umax3
+}
+
+; smax3
+
+define i32 @max3_i32(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: max3_i32:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max3_i32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_i32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+  %smax3 = call i32 @llvm.smax.i32(i32 %smax, i32 %c)
+  ret i32 %smax3
+}
+
+define amdgpu_ps i32 @max3_i32_uniform(i32 inreg %a, i32 inreg %b, i32 inreg %c) {
+; VI-LABEL: max3_i32_uniform:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_max_i32 s0, s2, s3
+; VI-NEXT:    s_max_i32 s0, s0, s4
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_i32_uniform:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_max_i32 s0, s2, s3
+; GFX10-NEXT:    s_max_i32 s0, s0, s4
+; GFX10-NEXT:    ; return to shader part epilog
+  %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+  %smax3 = call i32 @llvm.smax.i32(i32 %smax, i32 %c)
+  ret i32 %smax3
+}
+
+define i32 @max3_i32_commute(i32 %a, i32 %b, i32 %c) {
+; VI-LABEL: max3_i32_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max3_i32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_i32_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_i32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i32 @llvm.smax.i32(i32 %a, i32 %b)
+  %smax3 = call i32 @llvm.smax.i32(i32 %c, i32 %smax)
+  ret i32 %smax3
+}
+
+define i16 @max3_i16(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: max3_i16:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_i16_e32 v0, v0, v1
+; VI-NEXT:    v_max_i16_e32 v0, v0, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_i16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i16 @llvm.smax.i16(i16 %a, i16 %b)
+  %smax3 = call i16 @llvm.smax.i16(i16 %smax, i16 %c)
+  ret i16 %smax3
+}
+
+define i16 @max3_i16_commute(i16 %a, i16 %b, i16 %c) {
+; VI-LABEL: max3_i16_commute:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_i16_e32 v0, v0, v1
+; VI-NEXT:    v_max_i16_e32 v0, v2, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_i16_commute:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max3_i16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %smax = call i16 @llvm.smax.i16(i16 %a, i16 %b)
+  %smax3 = call i16 @llvm.smax.i16(i16 %c, i16 %smax)
+  ret i16 %smax3
+}
+
+; fmin ieee=true
+
+define float @min3_f32_ieee_true(float %a, float %b, float %c) {
+; VI-LABEL: min3_f32_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
+; VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_min3_f32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_f32_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %min = call float @llvm.minnum.f32(float %a, float %b)
+  %min3 = call float @llvm.minnum.f32(float %min, float %c)
+  ret float %min3
+}
+
+define float @min3_f32_commute_ieee_true(float %a, float %b, float %c) {
+; VI-LABEL: min3_f32_commute_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
+; VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_min3_f32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_f32_commute_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %min = call float @llvm.minnum.f32(float %a, float %b)
+  %min3 = call float @llvm.minnum.f32(float %c, float %min)
+  ret float %min3
+}
+
+define half @min3_f16_ieee_true(half %a, half %b, half %c) {
+; VI-LABEL: min3_f16_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_e32 v0, v0, v0
+; VI-NEXT:    v_max_f16_e32 v1, v1, v1
+; VI-NEXT:    v_min_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v1, v2, v2
+; VI-NEXT:    v_min_f16_e32 v0, v0, v1
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_f16_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %min = call half @llvm.minnum.f16(half %a, half %b)
+  %min3 = call half @llvm.minnum.f16(half %min, half %c)
+  ret half %min3
+}
+
+define half @min3_f16_commute_ieee_true(half %a, half %b, half %c) {
+; VI-LABEL: min3_f16_commute_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_e32 v0, v0, v0
+; VI-NEXT:    v_max_f16_e32 v1, v1, v1
+; VI-NEXT:    v_min_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v1, v2, v2
+; VI-NEXT:    v_min_f16_e32 v0, v1, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: min3_f16_commute_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %min = call half @llvm.minnum.f16(half %a, half %b)
+  %min3 = call half @llvm.minnum.f16(half %c, half %min)
+  ret half %min3
+}
+
+; fmin ieee=false
+
+define amdgpu_ps float @min3_f32_ieee_false(float %a, float %b, float %c) {
+; VI-LABEL: min3_f32_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_min3_f32 v0, v0, v1, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_f32_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %min = call float @llvm.minnum.f32(float %a, float %b)
+  %min3 = call float @llvm.minnum.f32(float %min, float %c)
+  ret float %min3
+}
+
+define amdgpu_ps float @min3_f32_commute_ieee_false(float %a, float %b, float %c) {
+; VI-LABEL: min3_f32_commute_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_min3_f32 v0, v0, v1, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_f32_commute_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %min = call float @llvm.minnum.f32(float %a, float %b)
+  %min3 = call float @llvm.minnum.f32(float %c, float %min)
+  ret float %min3
+}
+
+define amdgpu_ps half @min3_f16_ieee_false(half %a, half %b, half %c) {
+; VI-LABEL: min3_f16_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_min_f16_e32 v0, v0, v1
+; VI-NEXT:    v_min_f16_e32 v0, v0, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_f16_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %min = call half @llvm.minnum.f16(half %a, half %b)
+  %min3 = call half @llvm.minnum.f16(half %min, half %c)
+  ret half %min3
+}
+
+define amdgpu_ps half @min3_f16_commute_ieee_false(half %a, half %b, half %c) {
+; VI-LABEL: min3_f16_commute_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_min_f16_e32 v0, v0, v1
+; VI-NEXT:    v_min_f16_e32 v0, v2, v0
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: min3_f16_commute_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_min3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %min = call half @llvm.minnum.f16(half %a, half %b)
+  %min3 = call half @llvm.minnum.f16(half %c, half %min)
+  ret half %min3
+}
+
+; fmax ieee=true
+
+define float @max3_f32_ieee_true(float %a, float %b, float %c) {
+; VI-LABEL: max3_f32_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
+; VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_max3_f32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_f32_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %max = call float @llvm.maxnum.f32(float %a, float %b)
+  %max3 = call float @llvm.maxnum.f32(float %max, float %c)
+  ret float %max3
+}
+
+define float @max3_f32_commute_ieee_true(float %a, float %b, float %c) {
+; VI-LABEL: max3_f32_commute_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_mul_f32_e32 v0, 1.0, v0
+; VI-NEXT:    v_mul_f32_e32 v1, 1.0, v1
+; VI-NEXT:    v_mul_f32_e32 v2, 1.0, v2
+; VI-NEXT:    v_max3_f32 v0, v0, v1, v2
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_f32_commute_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f32_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f32_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f32_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %max = call float @llvm.maxnum.f32(float %a, float %b)
+  %max3 = call float @llvm.maxnum.f32(float %c, float %max)
+  ret float %max3
+}
+
+define half @max3_f16_ieee_true(half %a, half %b, half %c) {
+; VI-LABEL: max3_f16_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_e32 v0, v0, v0
+; VI-NEXT:    v_max_f16_e32 v1, v1, v1
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v1, v2, v2
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_f16_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %max = call half @llvm.maxnum.f16(half %a, half %b)
+  %max3 = call half @llvm.maxnum.f16(half %max, half %c)
+  ret half %max3
+}
+
+define half @max3_f16_commute_ieee_true(half %a, half %b, half %c) {
+; VI-LABEL: max3_f16_commute_ieee_true:
+; VI:       ; %bb.0:
+; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT:    v_max_f16_e32 v0, v0, v0
+; VI-NEXT:    v_max_f16_e32 v1, v1, v1
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v1, v2, v2
+; VI-NEXT:    v_max_f16_e32 v0, v1, v0
+; VI-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: max3_f16_commute_ieee_true:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_max_f16_e32 v0, v0, v0
+; GFX10-NEXT:    v_max_f16_e32 v1, v1, v1
+; GFX10-NEXT:    v_max_f16_e32 v2, v2, v2
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+  %max = call half @llvm.maxnum.f16(half %a, half %b)
+  %max3 = call half @llvm.maxnum.f16(half %c, half %max)
+  ret half %max3
+}
+
+; fmax ieee=false
+
+define amdgpu_ps float @max3_f32_ieee_false(float %a, float %b, float %c) {
+; VI-LABEL: max3_f32_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_max3_f32 v0, v0, v1, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_f32_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %max = call float @llvm.maxnum.f32(float %a, float %b)
+  %max3 = call float @llvm.maxnum.f32(float %max, float %c)
+  ret float %max3
+}
+
+define amdgpu_ps float @max3_f32_commute_ieee_false(float %a, float %b, float %c) {
+; VI-LABEL: max3_f32_commute_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_max3_f32 v0, v0, v1, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_f32_commute_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f32 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %max = call float @llvm.maxnum.f32(float %a, float %b)
+  %max3 = call float @llvm.maxnum.f32(float %c, float %max)
+  ret float %max3
+}
+
+define amdgpu_ps half @max3_f16_ieee_false(half %a, half %b, half %c) {
+; VI-LABEL: max3_f16_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v0, v0, v2
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_f16_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %max = call half @llvm.maxnum.f16(half %a, half %b)
+  %max3 = call half @llvm.maxnum.f16(half %max, half %c)
+  ret half %max3
+}
+
+define amdgpu_ps half @max3_f16_commute_ieee_false(half %a, half %b, half %c) {
+; VI-LABEL: max3_f16_commute_ieee_false:
+; VI:       ; %bb.0:
+; VI-NEXT:    v_max_f16_e32 v0, v0, v1
+; VI-NEXT:    v_max_f16_e32 v0, v2, v0
+; VI-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: max3_f16_commute_ieee_false:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_max3_f16 v0, v0, v1, v2
+; GFX10-NEXT:    ; return to shader part epilog
+  %max = call half @llvm.maxnum.f16(half %a, half %b)
+  %max3 = call half @llvm.maxnum.f16(half %c, half %max)
+  ret half %max3
+}
+
+declare i16 @llvm.umin.i16(i16, i16)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i16 @llvm.smin.i16(i16, i16)
+declare i32 @llvm.smin.i32(i32, i32)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i16 @llvm.smax.i16(i16, i16)
+declare i32 @llvm.smax.i32(i32, i32)
+declare half @llvm.minnum.f16(half, half)
+declare half @llvm.maxnum.f16(half, half)
+declare float @llvm.minnum.f32(float, float)
+declare float @llvm.maxnum.f32(float, float)
Index: llvm/test/CodeGen/AMDGPU/ctlz.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -774,9 +774,8 @@
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v0, v0, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, v1, v0
+; GFX10-GISEL-NEXT:    v_min3_u32 v0, v1, v0, 64
 ; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -887,8 +886,7 @@
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_ffbh_u32_e32 v2, v2
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, v2, v1
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v1, v2, v1, 64
 ; GFX10-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
Index: llvm/test/CodeGen/AMDGPU/cttz.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/cttz.ll
+++ llvm/test/CodeGen/AMDGPU/cttz.ll
@@ -767,9 +767,8 @@
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v0, v0
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v1, v1, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, v0, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v0, v0, v1, 64
 ; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v0, 64, v0
 ; GFX10-GISEL-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -880,8 +879,7 @@
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v2, v2
 ; GFX10-GISEL-NEXT:    v_ffbl_b32_e32 v1, v1
 ; GFX10-GISEL-NEXT:    v_add_nc_u32_e64 v2, v2, 32 clamp
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, v1, v2
-; GFX10-GISEL-NEXT:    v_min_u32_e32 v1, 64, v1
+; GFX10-GISEL-NEXT:    v_min3_u32 v1, v1, v2, 64
 ; GFX10-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-GISEL-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()