diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -336,6 +336,8 @@
         unsigned ExtraInfo = I->getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
         if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
           AdjustsStack = true;
+      } else if (TII.isStackAdjustIntrinsic(*I)) {
+        AdjustsStack = true;
       }
 
   assert(!MFI.isMaxCallFrameSizeComputed() ||
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
@@ -3,8 +3,12 @@
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @load1(i8* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load1_rn[[RN1:.*]]
-; CHECK:              callq   __asan_check_store1_rn[[RN1]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK-NEXT:         callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   call void @llvm.asan.check.memaccess(i8* %x, i32 0)
   call void @llvm.asan.check.memaccess(i8* %x, i32 32)
@@ -12,8 +16,12 @@
 }
 
 define void @load2(i16* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load2_rn[[RN2:.*]]
-; CHECK:              callq   __asan_check_store2_rn[[RN2]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK-NEXT:         callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i16* %x to i64
   %2 = bitcast i16* %x to i8*
@@ -23,8 +31,12 @@
 }
 
 define void @load4(i32* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load4_rn[[RN4:.*]]
-; CHECK:              callq   __asan_check_store4_rn[[RN4]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK-NEXT:         callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i32* %x to i64
   %2 = bitcast i32* %x to i8*
@@ -33,8 +45,12 @@
   ret void
 }
 define void @load8(i64* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load8_rn[[RN8:.*]]
-; CHECK:              callq   __asan_check_store8_rn[[RN8]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK-NEXT:         callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i64* %x to i64
   %2 = bitcast i64* %x to i8*
@@ -44,8 +60,12 @@
 }
 
 define void @load16(i128* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load16_rn[[RN16:.*]]
-; CHECK:              callq   __asan_check_store16_rn[[RN16]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK-NEXT:         callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i128* %x to i64
   %2 = bitcast i128* %x to i8*
diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
--- a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
+++ b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -3,8 +3,12 @@
 target triple = "x86_64-pc-win"
 
 define void @load1(i8* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load1_rn[[RN1:.*]]
-; CHECK:              callq   __asan_check_store1_rn[[RN1]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK-NEXT:         callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   call void @llvm.asan.check.memaccess(i8* %x, i32 0)
   call void @llvm.asan.check.memaccess(i8* %x, i32 32)
@@ -12,8 +16,12 @@
 }
 
 define void @load2(i16* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load2_rn[[RN2:.*]]
-; CHECK:              callq   __asan_check_store2_rn[[RN2]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK-NEXT:         callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i16* %x to i64
   %2 = bitcast i16* %x to i8*
@@ -23,8 +31,12 @@
 }
 
 define void @load4(i32* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load4_rn[[RN4:.*]]
-; CHECK:              callq   __asan_check_store4_rn[[RN4]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK-NEXT:         callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i32* %x to i64
   %2 = bitcast i32* %x to i8*
@@ -33,8 +45,12 @@
   ret void
 }
 define void @load8(i64* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load8_rn[[RN8:.*]]
-; CHECK:              callq   __asan_check_store8_rn[[RN8]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK-NEXT:         callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i64* %x to i64
   %2 = bitcast i64* %x to i8*
@@ -44,8 +60,12 @@
 }
 
 define void @load16(i128* nocapture readonly %x) {
-; CHECK:              callq   __asan_check_load16_rn[[RN16:.*]]
-; CHECK:              callq   __asan_check_store16_rn[[RN16]]
+; CHECK:              pushq   %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 16
+; CHECK-NEXT:         callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK-NEXT:         callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT:         popq    %rax
+; CHECK-NEXT:         .cfi_def_cfa_offset 8
 ; CHECK-NEXT:         retq
   %1 = ptrtoint i128* %x to i64
   %2 = bitcast i128* %x to i8*
@@ -53,7 +73,6 @@
   call void @llvm.asan.check.memaccess(i8* %2, i32 40)
   ret void
 }
-
 ; CHECK:              .type   __asan_check_load1_rn[[RN1]],@function
 ; CHECK-NEXT:         .weak   __asan_check_load1_rn[[RN1]]
 ; CHECK-NEXT:         .hidden __asan_check_load1_rn[[RN1]]