Index: llvm/lib/Target/PowerPC/PPCInstrVSX.td =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2809,6 +2809,10 @@ def : Pat<(v2i64 (build_vector DblToULong.A, DblToULong.A)), (v2i64 (XXPERMDI (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), (SUBREG_TO_REG (i64 1), (XSCVDPUXDS $A), sub_64), 0))>; +def : Pat<(v4i32 (PPCSToV DblToInt.A)), + (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; +def : Pat<(v4i32 (PPCSToV DblToUInt.A)), + (v4i32 (SUBREG_TO_REG (i64 1), (XSCVDPSXWS f64:$A), sub_64))>; defm : ScalToVecWPermute< v4i32, FltToIntLoad.A, (XXSPLTW (SUBREG_TO_REG (i64 1), (XSCVDPSXWSs (XFLOADf32 ForceXForm:$A)), sub_64), 1), Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll @@ -0,0 +1,118 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; xscvdpsxws and uxws is only available on Power7 and above +; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ +; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ +; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE + +define dso_local <4 x i32> @test(<4 x i32> %a, double %b) { +; CHECK-LE-LABEL: test: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xscvdpsxws 35, 1 +; CHECK-LE-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-LE-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-LE-NEXT: lvx 4, 0, 3 +; CHECK-LE-NEXT: vperm 2, 3, 2, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xscvdpsxws 0, 1 +; CHECK-BE-NEXT: addi 3, 1, -4 +; CHECK-BE-NEXT: stfiwx 0, 0, 3 +; CHECK-BE-NEXT: lwz 3, -4(1) +; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3 +; CHECK-BE-NEXT: stw 3, -32(1) +; CHECK-BE-NEXT: addi 3, 1, -32 +; CHECK-BE-NEXT: lxvw4x 1, 0, 3 +; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1 +; CHECK-BE-NEXT: blr +entry: + %conv = fptosi double %b to i32 + %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 + ret <4 x i32> %vecins +} + +define dso_local <4 x i32> @test2(<4 x i32> %a, float %b) { +; CHECK-LE-LABEL: test2: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xscvdpsxws 35, 1 +; CHECK-LE-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; CHECK-LE-NEXT: addi 3, 3, .LCPI1_0@toc@l +; CHECK-LE-NEXT: lvx 4, 0, 3 +; CHECK-LE-NEXT: vperm 2, 3, 2, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test2: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xscvdpsxws 0, 1 +; CHECK-BE-NEXT: addi 3, 1, -4 +; CHECK-BE-NEXT: stfiwx 0, 0, 3 +; CHECK-BE-NEXT: lwz 3, -4(1) +; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3 +; CHECK-BE-NEXT: stw 3, -32(1) +; CHECK-BE-NEXT: addi 3, 1, -32 +; CHECK-BE-NEXT: lxvw4x 1, 0, 3 +; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1 +; CHECK-BE-NEXT: blr +entry: + %conv = fptosi float %b to i32 + %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 + ret <4 x i32> %vecins +} + +define dso_local <4 x i32> @test3(<4 x i32> %a, double %b) { +; CHECK-LE-LABEL: test3: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xscvdpsxws 35, 1 +; CHECK-LE-NEXT: addis 3, 2, .LCPI2_0@toc@ha +; CHECK-LE-NEXT: addi 3, 3, .LCPI2_0@toc@l +; CHECK-LE-NEXT: lvx 4, 0, 3 +; CHECK-LE-NEXT: vperm 2, 3, 2, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test3: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xscvdpuxws 0, 1 +; CHECK-BE-NEXT: addi 3, 1, -4 +; CHECK-BE-NEXT: stfiwx 0, 0, 3 +; CHECK-BE-NEXT: lwz 3, -4(1) +; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3 +; CHECK-BE-NEXT: stw 3, -32(1) +; CHECK-BE-NEXT: addi 3, 1, -32 +; CHECK-BE-NEXT: lxvw4x 1, 0, 3 +; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1 +; CHECK-BE-NEXT: blr +entry: + %conv = fptoui double %b to i32 + %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 + ret <4 x i32> %vecins +} + +define dso_local <4 x i32> @test4(<4 x i32> %a, float %b) { +; CHECK-LE-LABEL: test4: +; CHECK-LE: # %bb.0: # %entry +; CHECK-LE-NEXT: xscvdpsxws 35, 1 +; CHECK-LE-NEXT: addis 3, 2, .LCPI3_0@toc@ha +; CHECK-LE-NEXT: addi 3, 3, .LCPI3_0@toc@l +; CHECK-LE-NEXT: lvx 4, 0, 3 +; CHECK-LE-NEXT: vperm 2, 3, 2, 4 +; CHECK-LE-NEXT: blr +; +; CHECK-BE-LABEL: test4: +; CHECK-BE: # %bb.0: # %entry +; CHECK-BE-NEXT: xscvdpuxws 0, 1 +; CHECK-BE-NEXT: addi 3, 1, -4 +; CHECK-BE-NEXT: stfiwx 0, 0, 3 +; CHECK-BE-NEXT: lwz 3, -4(1) +; CHECK-BE-NEXT: xxsldwi 0, 34, 34, 3 +; CHECK-BE-NEXT: stw 3, -32(1) +; CHECK-BE-NEXT: addi 3, 1, -32 +; CHECK-BE-NEXT: lxvw4x 1, 0, 3 +; CHECK-BE-NEXT: xxsldwi 34, 0, 1, 1 +; CHECK-BE-NEXT: blr +entry: + %conv = fptoui float %b to i32 + %vecins = insertelement <4 x i32> %a, i32 %conv, i32 3 + ret <4 x i32> %vecins +} Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll =================================================================== --- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll +++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll @@ -13,12 +13,8 @@ ; CHECK-P8-LABEL: test2elt: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxswapd vs0, v2 -; CHECK-P8-NEXT: xscvdpuxws f1, v2 -; CHECK-P8-NEXT: xscvdpuxws f0, f0 -; CHECK-P8-NEXT: mffprwz r3, f1 -; CHECK-P8-NEXT: mtvsrwz v2, r3 -; CHECK-P8-NEXT: mffprwz r4, f0 -; CHECK-P8-NEXT: mtvsrwz v3, r4 +; CHECK-P8-NEXT: xscvdpsxws v2, v2 +; CHECK-P8-NEXT: xscvdpsxws v3, f0 ; CHECK-P8-NEXT: vmrghw v2, v2, v3 ; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: mffprd r3, f0 @@ -26,26 +22,18 @@ ; ; CHECK-P9-LABEL: test2elt: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: xscvdpuxws f0, v2 -; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: xxswapd vs0, v2 -; CHECK-P9-NEXT: mtvsrwz v3, r3 -; CHECK-P9-NEXT: xscvdpuxws f0, f0 -; CHECK-P9-NEXT: mffprwz r3, f0 -; CHECK-P9-NEXT: mtvsrwz v2, r3 +; CHECK-P9-NEXT: xscvdpsxws v3, v2 +; CHECK-P9-NEXT: xscvdpsxws v2, f0 ; CHECK-P9-NEXT: vmrghw v2, v3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test2elt: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpuxws f0, v2 -; CHECK-BE-NEXT: mffprwz r3, f0 ; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvdpuxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvdpsxws v3, v2 +; CHECK-BE-NEXT: xscvdpsxws v2, f0 ; CHECK-BE-NEXT: vmrgow v2, v3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: blr @@ -305,12 +293,8 @@ ; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8: # %bb.0: # %entry ; CHECK-P8-NEXT: xxswapd vs0, v2 -; CHECK-P8-NEXT: xscvdpsxws f1, v2 -; CHECK-P8-NEXT: xscvdpsxws f0, f0 -; CHECK-P8-NEXT: mffprwz r3, f1 -; CHECK-P8-NEXT: mtvsrwz v2, r3 -; CHECK-P8-NEXT: mffprwz r4, f0 -; CHECK-P8-NEXT: mtvsrwz v3, r4 +; CHECK-P8-NEXT: xscvdpsxws v2, v2 +; CHECK-P8-NEXT: xscvdpsxws v3, f0 ; CHECK-P8-NEXT: vmrghw v2, v2, v3 ; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: mffprd r3, f0 @@ -318,26 +302,18 @@ ; ; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9: # %bb.0: # %entry -; CHECK-P9-NEXT: xscvdpsxws f0, v2 -; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: xxswapd vs0, v2 -; CHECK-P9-NEXT: mtvsrwz v3, r3 -; CHECK-P9-NEXT: xscvdpsxws f0, f0 -; CHECK-P9-NEXT: mffprwz r3, f0 -; CHECK-P9-NEXT: mtvsrwz v2, r3 +; CHECK-P9-NEXT: xscvdpsxws v3, v2 +; CHECK-P9-NEXT: xscvdpsxws v2, f0 ; CHECK-P9-NEXT: vmrghw v2, v3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: blr ; ; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE: # %bb.0: # %entry -; CHECK-BE-NEXT: xscvdpsxws f0, v2 -; CHECK-BE-NEXT: mffprwz r3, f0 ; CHECK-BE-NEXT: xxswapd vs0, v2 -; CHECK-BE-NEXT: mtvsrwz v3, r3 -; CHECK-BE-NEXT: xscvdpsxws f0, f0 -; CHECK-BE-NEXT: mffprwz r3, f0 -; CHECK-BE-NEXT: mtvsrwz v2, r3 +; CHECK-BE-NEXT: xscvdpsxws v3, v2 +; CHECK-BE-NEXT: xscvdpsxws v2, f0 ; CHECK-BE-NEXT: vmrgow v2, v3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: blr