Index: clang/docs/ReleaseNotes.rst =================================================================== --- clang/docs/ReleaseNotes.rst +++ clang/docs/ReleaseNotes.rst @@ -170,6 +170,12 @@ - Support for ``AVX512-FP16`` instructions has been added. +Arm and AArch64 Support in Clang +-------------------------------- + +- Support has been added for the following processors (command-line identifiers in parentheses): + - Arm Cortex-A510 (``cortex-a510``) + Internal API Changes -------------------- Index: clang/test/Driver/aarch64-cpus.c =================================================================== --- clang/test/Driver/aarch64-cpus.c +++ clang/test/Driver/aarch64-cpus.c @@ -394,6 +394,15 @@ // CA55-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "cortex-a55" // CA55-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" +// RUN: %clang -target aarch64 -mcpu=cortex-a510 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A510 %s +// CORTEX-A510: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a510" +// CORTEX-A510-NOT: "-target-feature" "{{[+-]}}sm4" +// CORTEX-A510-NOT: "-target-feature" "{{[+-]}}sha3" +// CORTEX-A510-NOT: "-target-feature" "{{[+-]}}aes" +// CORTEX-A510-SAME: {{$}} +// RUN: %clang -target aarch64 -mcpu=cortex-a510+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A510-CRYPTO %s +// CORTEX-A510-CRYPTO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes" + // RUN: %clang -target aarch64_be -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s // RUN: %clang -target aarch64 -mbig-endian -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s // RUN: %clang -target aarch64_be -mbig-endian -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s Index: llvm/include/llvm/Support/AArch64TargetParser.def =================================================================== --- llvm/include/llvm/Support/AArch64TargetParser.def +++ llvm/include/llvm/Support/AArch64TargetParser.def @@ -144,6 +144,10 @@ (AArch64::AEK_CRC)) AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC)) +AARCH64_CPU_NAME("cortex-a510", ARMV9A, FK_NEON_FP_ARMV8, false, + (AArch64::AEK_BF16 | AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM | + AArch64::AEK_PAUTH | AArch64::AEK_MTE | AArch64::AEK_SSBS | + AArch64::AEK_SB | AArch64::AEK_FP16FML)) AARCH64_CPU_NAME("cortex-a57", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_CRC)) AARCH64_CPU_NAME("cortex-a65", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false, Index: llvm/lib/Target/AArch64/AArch64.td =================================================================== --- llvm/lib/Target/AArch64/AArch64.td +++ llvm/lib/Target/AArch64/AArch64.td @@ -630,6 +630,22 @@ FeatureFuseAddress, ]>; +def ProcA510 : SubtargetFeature<"a510", "ARMProcFamily", "CortexA510", + "Cortex-A510 ARM processors", [ + HasV9_0aOps, + FeatureNEON, + FeaturePerfMon, + FeatureMatMulInt8, + FeatureBF16, + FeatureAM, + FeatureMTE, + FeatureETE, + FeatureSVE2BitPerm, + FeatureFP16FML, + FeatureFuseAES, + FeaturePostRAScheduler + ]>; + def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", [ FeatureBalanceFPOps, @@ -1186,6 +1202,7 @@ def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>; def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>; +def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>; def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>; Index: llvm/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -50,6 +50,7 @@ CortexA35, CortexA53, CortexA55, + CortexA510, CortexA57, CortexA65, CortexA72, Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -78,6 +78,7 @@ break; case CortexA53: case CortexA55: + case CortexA510: PrefFunctionLogAlignment = 4; break; case CortexA57: Index: llvm/unittests/Support/TargetParserTest.cpp =================================================================== --- llvm/unittests/Support/TargetParserTest.cpp +++ llvm/unittests/Support/TargetParserTest.cpp @@ -898,6 +898,17 @@ AArch64::AEK_RDM | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC, "8.2-A"), + ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8", + AArch64::AEK_CRC | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_RAS | + AArch64::AEK_LSE | AArch64::AEK_RDM | + AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | + AArch64::AEK_SVE2 | AArch64::AEK_BF16 | + AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM | + AArch64::AEK_PAUTH | AArch64::AEK_MTE | + AArch64::AEK_SSBS | AArch64::AEK_FP16FML | + AArch64::AEK_SB, + "9-A"), ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8", AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP | AArch64::AEK_SIMD, @@ -1178,7 +1189,7 @@ AArch64::AEK_LSE | AArch64::AEK_RDM, "8.2-A"))); -static constexpr unsigned NumAArch64CPUArchs = 48; +static constexpr unsigned NumAArch64CPUArchs = 49; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List;