diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -691,7 +691,7 @@ RC == &AMDGPU::SReg_32RegClass) { if (SrcReg == AMDGPU::SCC) { BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg) - .addImm(1) + .addImm(-1) .addImm(0); return; } @@ -724,7 +724,7 @@ if (RC == &AMDGPU::SReg_64RegClass) { if (SrcReg == AMDGPU::SCC) { BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B64), DestReg) - .addImm(1) + .addImm(-1) .addImm(0); return; } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll @@ -4693,9 +4693,9 @@ ; GFX6-NEXT: s_sub_i32 s9, s12, 64 ; GFX6-NEXT: s_sub_i32 s10, 64, s12 ; GFX6-NEXT: s_cmp_lt_u32 s12, 64 -; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s12, 0 -; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[0:1], s12 ; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX6-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 @@ -4714,9 +4714,9 @@ ; GFX6-NEXT: s_sub_i32 s12, s8, 64 ; GFX6-NEXT: s_sub_i32 s10, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_cselect_b32 s13, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX6-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 @@ -4740,9 +4740,9 @@ ; GFX8-NEXT: s_sub_i32 s9, s12, 64 ; GFX8-NEXT: s_sub_i32 s10, 64, s12 ; GFX8-NEXT: s_cmp_lt_u32 s12, 64 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s12, 0 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[14:15], s[0:1], s12 ; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX8-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 @@ -4761,9 +4761,9 @@ ; GFX8-NEXT: s_sub_i32 s12, s8, 64 ; GFX8-NEXT: s_sub_i32 s10, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_cselect_b32 s13, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX8-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 @@ -4787,9 +4787,9 @@ ; GFX9-NEXT: s_sub_i32 s9, s12, 64 ; GFX9-NEXT: s_sub_i32 s10, 64, s12 ; GFX9-NEXT: s_cmp_lt_u32 s12, 64 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s12, 0 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[14:15], s[0:1], s12 ; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s10 ; GFX9-NEXT: s_lshl_b64 s[12:13], s[2:3], s12 @@ -4808,9 +4808,9 @@ ; GFX9-NEXT: s_sub_i32 s12, s8, 64 ; GFX9-NEXT: s_sub_i32 s10, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[4:5], s8 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[0:1], s8 @@ -4834,9 +4834,9 @@ ; GFX10-NEXT: s_sub_i32 s9, s12, 64 ; GFX10-NEXT: s_sub_i32 s10, 64, s12 ; GFX10-NEXT: s_cmp_lt_u32 s12, 64 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s12, 0 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[2:3], s12 ; GFX10-NEXT: s_lshr_b64 s[14:15], s[0:1], s10 ; GFX10-NEXT: s_lshl_b64 s[12:13], s[0:1], s12 @@ -4855,9 +4855,9 @@ ; GFX10-NEXT: s_lshr_b64 s[4:5], s[6:7], 1 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 -; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cselect_b32 s15, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s8 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s9 ; GFX10-NEXT: s_lshr_b64 s[8:9], s[4:5], s8 @@ -5299,9 +5299,9 @@ ; GFX6-NEXT: s_sub_i32 s5, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cselect_b32 s12, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_cselect_b32 s13, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[0:1], s8 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 @@ -5319,12 +5319,12 @@ ; GFX6-NEXT: s_sub_i32 s2, s4, 64 ; GFX6-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s4 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s3 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s4 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s2 ; GFX6-NEXT: s_and_b32 s2, 1, s5 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 @@ -5354,9 +5354,9 @@ ; GFX8-NEXT: s_sub_i32 s5, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cselect_b32 s12, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_cselect_b32 s13, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[6:7], s[0:1], s8 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 @@ -5374,12 +5374,12 @@ ; GFX8-NEXT: s_sub_i32 s2, s4, 64 ; GFX8-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3] ; GFX8-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3] ; GFX8-NEXT: s_and_b32 s2, 1, s5 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 @@ -5409,9 +5409,9 @@ ; GFX9-NEXT: s_sub_i32 s5, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[6:7], s[0:1], s8 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[2:3], s8 @@ -5429,12 +5429,12 @@ ; GFX9-NEXT: s_sub_i32 s2, s4, 64 ; GFX9-NEXT: v_or_b32_e32 v1, v1, v4 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s3, v[2:3] ; GFX9-NEXT: v_lshrrev_b64 v[8:9], s4, v[2:3] -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: v_lshrrev_b64 v[2:3], s2, v[2:3] ; GFX9-NEXT: s_and_b32 s2, 1, s5 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s2 @@ -5466,10 +5466,10 @@ ; GFX10-NEXT: s_sub_i32 s6, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 31, v2 -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3] -; GFX10-NEXT: s_cselect_b32 s13, 1, 0 +; GFX10-NEXT: s_cselect_b32 s13, -1, 0 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s8 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s6 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 @@ -5487,11 +5487,11 @@ ; GFX10-NEXT: s_sub_i32 s0, s4, 64 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] -; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] @@ -5522,9 +5522,9 @@ ; GFX6-NEXT: s_sub_i32 s6, 64, s8 ; GFX6-NEXT: s_sub_i32 s5, s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s10, 1, 0 +; GFX6-NEXT: s_cselect_b32 s10, -1, 0 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s6 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s8 ; GFX6-NEXT: v_lshl_b64 v[8:9], v[0:1], s8 @@ -5542,9 +5542,9 @@ ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX6-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 -; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cselect_b32 s12, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -5577,9 +5577,9 @@ ; GFX8-NEXT: s_sub_i32 s6, 64, s8 ; GFX8-NEXT: s_sub_i32 s5, s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] @@ -5597,9 +5597,9 @@ ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 -; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cselect_b32 s12, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -5632,9 +5632,9 @@ ; GFX9-NEXT: s_sub_i32 s6, 64, s8 ; GFX9-NEXT: s_sub_i32 s5, s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] @@ -5652,9 +5652,9 @@ ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX9-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc @@ -5689,10 +5689,10 @@ ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] -; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 @@ -5710,11 +5710,11 @@ ; GFX10-NEXT: s_sub_i32 s7, 64, s10 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64 ; GFX10-NEXT: v_cndmask_b32_e32 v6, 0, v8, vcc_lo -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v7, 0, v9, vcc_lo ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 -; GFX10-NEXT: s_cselect_b32 s13, 1, 0 +; GFX10-NEXT: s_cselect_b32 s13, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s10 ; GFX10-NEXT: s_lshl_b64 s[6:7], s[2:3], s7 ; GFX10-NEXT: s_lshr_b64 s[8:9], s[2:3], s10 @@ -5844,9 +5844,9 @@ ; GFX6-NEXT: s_sub_i32 s17, s22, 64 ; GFX6-NEXT: s_sub_i32 s23, 64, s22 ; GFX6-NEXT: s_cmp_lt_u32 s22, 64 -; GFX6-NEXT: s_cselect_b32 s28, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s22, 0 -; GFX6-NEXT: s_cselect_b32 s29, 1, 0 +; GFX6-NEXT: s_cselect_b32 s29, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[0:1], s22 ; GFX6-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX6-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 @@ -5865,9 +5865,9 @@ ; GFX6-NEXT: s_sub_i32 s26, s16, 64 ; GFX6-NEXT: s_sub_i32 s22, 64, s16 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64 -; GFX6-NEXT: s_cselect_b32 s27, 1, 0 +; GFX6-NEXT: s_cselect_b32 s27, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s16, 0 -; GFX6-NEXT: s_cselect_b32 s28, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX6-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX6-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 @@ -5886,9 +5886,9 @@ ; GFX6-NEXT: s_sub_i32 s11, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s22, 1, 0 +; GFX6-NEXT: s_cselect_b32 s22, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX6-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 @@ -5907,9 +5907,9 @@ ; GFX6-NEXT: s_sub_i32 s18, s10, 64 ; GFX6-NEXT: s_sub_i32 s14, 64, s10 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64 -; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s10, 0 -; GFX6-NEXT: s_cselect_b32 s20, 1, 0 +; GFX6-NEXT: s_cselect_b32 s20, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX6-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 @@ -5933,9 +5933,9 @@ ; GFX8-NEXT: s_sub_i32 s17, s22, 64 ; GFX8-NEXT: s_sub_i32 s23, 64, s22 ; GFX8-NEXT: s_cmp_lt_u32 s22, 64 -; GFX8-NEXT: s_cselect_b32 s28, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s22, 0 -; GFX8-NEXT: s_cselect_b32 s29, 1, 0 +; GFX8-NEXT: s_cselect_b32 s29, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[0:1], s22 ; GFX8-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX8-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 @@ -5954,9 +5954,9 @@ ; GFX8-NEXT: s_sub_i32 s26, s16, 64 ; GFX8-NEXT: s_sub_i32 s22, 64, s16 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64 -; GFX8-NEXT: s_cselect_b32 s27, 1, 0 +; GFX8-NEXT: s_cselect_b32 s27, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s16, 0 -; GFX8-NEXT: s_cselect_b32 s28, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX8-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX8-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 @@ -5975,9 +5975,9 @@ ; GFX8-NEXT: s_sub_i32 s11, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s22, 1, 0 +; GFX8-NEXT: s_cselect_b32 s22, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX8-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 @@ -5996,9 +5996,9 @@ ; GFX8-NEXT: s_sub_i32 s18, s10, 64 ; GFX8-NEXT: s_sub_i32 s14, 64, s10 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s10, 0 -; GFX8-NEXT: s_cselect_b32 s20, 1, 0 +; GFX8-NEXT: s_cselect_b32 s20, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX8-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 @@ -6022,9 +6022,9 @@ ; GFX9-NEXT: s_sub_i32 s17, s22, 64 ; GFX9-NEXT: s_sub_i32 s23, 64, s22 ; GFX9-NEXT: s_cmp_lt_u32 s22, 64 -; GFX9-NEXT: s_cselect_b32 s28, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s22, 0 -; GFX9-NEXT: s_cselect_b32 s29, 1, 0 +; GFX9-NEXT: s_cselect_b32 s29, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[0:1], s22 ; GFX9-NEXT: s_lshr_b64 s[26:27], s[0:1], s23 ; GFX9-NEXT: s_lshl_b64 s[22:23], s[2:3], s22 @@ -6043,9 +6043,9 @@ ; GFX9-NEXT: s_sub_i32 s26, s16, 64 ; GFX9-NEXT: s_sub_i32 s22, 64, s16 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64 -; GFX9-NEXT: s_cselect_b32 s27, 1, 0 +; GFX9-NEXT: s_cselect_b32 s27, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s16, 0 -; GFX9-NEXT: s_cselect_b32 s28, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[8:9], s16 ; GFX9-NEXT: s_lshl_b64 s[22:23], s[8:9], s22 ; GFX9-NEXT: s_lshr_b64 s[16:17], s[0:1], s16 @@ -6064,9 +6064,9 @@ ; GFX9-NEXT: s_sub_i32 s11, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[4:5], s8 ; GFX9-NEXT: s_lshr_b64 s[20:21], s[4:5], s9 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[6:7], s8 @@ -6085,9 +6085,9 @@ ; GFX9-NEXT: s_sub_i32 s18, s10, 64 ; GFX9-NEXT: s_sub_i32 s14, 64, s10 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s10, 0 -; GFX9-NEXT: s_cselect_b32 s20, 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[12:13], s[8:9], s10 ; GFX9-NEXT: s_lshl_b64 s[14:15], s[8:9], s14 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s10 @@ -6111,9 +6111,9 @@ ; GFX10-NEXT: s_sub_i32 s17, s22, 64 ; GFX10-NEXT: s_sub_i32 s23, 64, s22 ; GFX10-NEXT: s_cmp_lt_u32 s22, 64 -; GFX10-NEXT: s_cselect_b32 s28, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s22, 0 -; GFX10-NEXT: s_cselect_b32 s29, 1, 0 +; GFX10-NEXT: s_cselect_b32 s29, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s23 ; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s22 ; GFX10-NEXT: s_lshl_b64 s[22:23], s[0:1], s22 @@ -6132,9 +6132,9 @@ ; GFX10-NEXT: s_lshr_b64 s[8:9], s[10:11], 1 ; GFX10-NEXT: s_sub_i32 s17, 64, s16 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64 -; GFX10-NEXT: s_cselect_b32 s27, 1, 0 +; GFX10-NEXT: s_cselect_b32 s27, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s16, 0 -; GFX10-NEXT: s_cselect_b32 s28, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s16 ; GFX10-NEXT: s_lshl_b64 s[24:25], s[8:9], s17 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[8:9], s16 @@ -6153,9 +6153,9 @@ ; GFX10-NEXT: s_sub_i32 s11, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s9 ; GFX10-NEXT: s_lshl_b64 s[20:21], s[6:7], s8 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[4:5], s8 @@ -6174,9 +6174,9 @@ ; GFX10-NEXT: s_lshr_b64 s[12:13], s[14:15], 1 ; GFX10-NEXT: s_sub_i32 s11, 64, s10 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[14:15], s[4:5], s10 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[12:13], s11 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], s10 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll @@ -4785,9 +4785,9 @@ ; GFX6-NEXT: s_sub_i32 s13, s8, 64 ; GFX6-NEXT: s_sub_i32 s9, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX6-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 @@ -4801,9 +4801,9 @@ ; GFX6-NEXT: s_sub_i32 s14, s12, 64 ; GFX6-NEXT: s_sub_i32 s13, 64, s12 ; GFX6-NEXT: s_cmp_lt_u32 s12, 64 -; GFX6-NEXT: s_cselect_b32 s15, 1, 0 +; GFX6-NEXT: s_cselect_b32 s15, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s12, 0 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[6:7], s12 ; GFX6-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX6-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 @@ -4832,9 +4832,9 @@ ; GFX8-NEXT: s_sub_i32 s13, s8, 64 ; GFX8-NEXT: s_sub_i32 s9, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX8-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 @@ -4848,9 +4848,9 @@ ; GFX8-NEXT: s_sub_i32 s14, s12, 64 ; GFX8-NEXT: s_sub_i32 s13, 64, s12 ; GFX8-NEXT: s_cmp_lt_u32 s12, 64 -; GFX8-NEXT: s_cselect_b32 s15, 1, 0 +; GFX8-NEXT: s_cselect_b32 s15, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s12, 0 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[6:7], s12 ; GFX8-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX8-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 @@ -4879,9 +4879,9 @@ ; GFX9-NEXT: s_sub_i32 s13, s8, 64 ; GFX9-NEXT: s_sub_i32 s9, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[14:15], s8 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], s9 ; GFX9-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 @@ -4895,9 +4895,9 @@ ; GFX9-NEXT: s_sub_i32 s14, s12, 64 ; GFX9-NEXT: s_sub_i32 s13, 64, s12 ; GFX9-NEXT: s_cmp_lt_u32 s12, 64 -; GFX9-NEXT: s_cselect_b32 s15, 1, 0 +; GFX9-NEXT: s_cselect_b32 s15, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s12, 0 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[6:7], s12 ; GFX9-NEXT: s_lshr_b64 s[10:11], s[4:5], s12 ; GFX9-NEXT: s_lshl_b64 s[12:13], s[6:7], s13 @@ -4926,9 +4926,9 @@ ; GFX10-NEXT: s_sub_i32 s13, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[10:11], s[0:1], s9 ; GFX10-NEXT: s_lshl_b64 s[14:15], s[2:3], s8 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[0:1], s8 @@ -4942,9 +4942,9 @@ ; GFX10-NEXT: s_sub_i32 s14, s12, 64 ; GFX10-NEXT: s_sub_i32 s10, 64, s12 ; GFX10-NEXT: s_cmp_lt_u32 s12, 64 -; GFX10-NEXT: s_cselect_b32 s15, 1, 0 +; GFX10-NEXT: s_cselect_b32 s15, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s12, 0 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], s12 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[6:7], s10 ; GFX10-NEXT: s_lshr_b64 s[12:13], s[6:7], s12 @@ -5391,9 +5391,9 @@ ; GFX6-NEXT: s_sub_i32 s9, s4, 64 ; GFX6-NEXT: s_sub_i32 s5, 64, s4 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 -; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cselect_b32 s12, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 -; GFX6-NEXT: s_cselect_b32 s13, 1, 0 +; GFX6-NEXT: s_cselect_b32 s13, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX6-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 @@ -5407,12 +5407,12 @@ ; GFX6-NEXT: s_sub_i32 s5, 64, s8 ; GFX6-NEXT: s_sub_i32 s4, s8, 64 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], s8 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s5 ; GFX6-NEXT: v_lshr_b64 v[8:9], v[2:3], s8 -; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cselect_b32 s7, -1, 0 ; GFX6-NEXT: v_lshr_b64 v[2:3], v[2:3], s4 ; GFX6-NEXT: s_and_b32 s4, 1, s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 @@ -5447,9 +5447,9 @@ ; GFX8-NEXT: s_sub_i32 s9, s4, 64 ; GFX8-NEXT: s_sub_i32 s5, 64, s4 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 -; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cselect_b32 s12, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 -; GFX8-NEXT: s_cselect_b32 s13, 1, 0 +; GFX8-NEXT: s_cselect_b32 s13, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX8-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX8-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 @@ -5463,12 +5463,12 @@ ; GFX8-NEXT: s_sub_i32 s5, 64, s8 ; GFX8-NEXT: s_sub_i32 s4, s8, 64 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX8-NEXT: v_lshrrev_b64 v[8:9], s8, v[2:3] -; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, -1, 0 ; GFX8-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] ; GFX8-NEXT: s_and_b32 s4, 1, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 @@ -5503,9 +5503,9 @@ ; GFX9-NEXT: s_sub_i32 s9, s4, 64 ; GFX9-NEXT: s_sub_i32 s5, 64, s4 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 -; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[10:11], s4 ; GFX9-NEXT: s_lshr_b64 s[6:7], s[10:11], s5 ; GFX9-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 @@ -5519,12 +5519,12 @@ ; GFX9-NEXT: s_sub_i32 s5, 64, s8 ; GFX9-NEXT: s_sub_i32 s4, s8, 64 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s5, v[2:3] ; GFX9-NEXT: v_lshrrev_b64 v[8:9], s8, v[2:3] -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: v_lshrrev_b64 v[2:3], s4, v[2:3] ; GFX9-NEXT: s_and_b32 s4, 1, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 @@ -5560,9 +5560,9 @@ ; GFX10-NEXT: s_sub_i32 s5, 64, s4 ; GFX10-NEXT: s_cmp_lt_u32 s4, 64 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s8, v[0:1] -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s4, 0 -; GFX10-NEXT: s_cselect_b32 s13, 1, 0 +; GFX10-NEXT: s_cselect_b32 s13, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[0:1], s5 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[2:3], s4 ; GFX10-NEXT: s_lshl_b64 s[4:5], s[0:1], s4 @@ -5578,11 +5578,11 @@ ; GFX10-NEXT: s_sub_i32 s0, s8, 64 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: v_lshrrev_b64 v[8:9], s0, v[2:3] -; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 ; GFX10-NEXT: v_or_b32_e32 v5, v5, v7 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s1, 1, vcc_lo ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_lshrrev_b64 v[2:3], s8, v[2:3] @@ -5617,9 +5617,9 @@ ; GFX6-NEXT: v_lshrrev_b32_e32 v0, 31, v1 ; GFX6-NEXT: s_cmp_lt_u32 s4, 64 ; GFX6-NEXT: v_or_b32_e32 v2, v2, v0 -; GFX6-NEXT: s_cselect_b32 s7, 1, 0 +; GFX6-NEXT: s_cselect_b32 s7, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s4, 0 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: v_lshr_b64 v[0:1], v[4:5], s6 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[2:3], s4 ; GFX6-NEXT: v_lshl_b64 v[8:9], v[4:5], s4 @@ -5632,9 +5632,9 @@ ; GFX6-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX6-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[4:5], s5 -; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s12, 1, 0 +; GFX6-NEXT: s_cselect_b32 s12, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc @@ -5671,9 +5671,9 @@ ; GFX8-NEXT: v_lshrrev_b32_e32 v0, 31, v1 ; GFX8-NEXT: s_cmp_lt_u32 s4, 64 ; GFX8-NEXT: v_or_b32_e32 v2, v2, v0 -; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s4, 0 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] ; GFX8-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] @@ -5686,9 +5686,9 @@ ; GFX8-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX8-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX8-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5] -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s12, 1, 0 +; GFX8-NEXT: s_cselect_b32 s12, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc @@ -5725,9 +5725,9 @@ ; GFX9-NEXT: v_lshrrev_b32_e32 v0, 31, v1 ; GFX9-NEXT: s_cmp_lt_u32 s4, 64 ; GFX9-NEXT: v_or_b32_e32 v2, v2, v0 -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s4, 0 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: v_lshrrev_b64 v[0:1], s6, v[4:5] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s4, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[8:9], s4, v[4:5] @@ -5740,9 +5740,9 @@ ; GFX9-NEXT: v_or_b32_e32 v6, v0, v6 ; GFX9-NEXT: v_or_b32_e32 v7, v1, v7 ; GFX9-NEXT: v_lshlrev_b64 v[0:1], s5, v[4:5] -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v4, 0, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, 0, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc @@ -5781,10 +5781,10 @@ ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 ; GFX10-NEXT: v_lshrrev_b64 v[4:5], s4, v[0:1] ; GFX10-NEXT: v_lshlrev_b64 v[6:7], s8, v[2:3] -; GFX10-NEXT: s_cselect_b32 vcc_lo, 1, 0 +; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 ; GFX10-NEXT: v_lshlrev_b64 v[8:9], s8, v[0:1] -; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_cselect_b32 s7, -1, 0 ; GFX10-NEXT: s_and_b32 s4, 1, vcc_lo ; GFX10-NEXT: v_lshlrev_b64 v[0:1], s5, v[0:1] ; GFX10-NEXT: v_or_b32_e32 v4, v4, v6 @@ -5799,9 +5799,9 @@ ; GFX10-NEXT: s_sub_i32 s7, 64, s6 ; GFX10-NEXT: s_cmp_lt_u32 s6, 64 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s6, 0 -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[0:1], s6 ; GFX10-NEXT: s_lshl_b64 s[8:9], s[2:3], s7 ; GFX10-NEXT: s_lshr_b64 s[6:7], s[2:3], s6 @@ -5943,9 +5943,9 @@ ; GFX6-NEXT: s_sub_i32 s23, s16, 64 ; GFX6-NEXT: s_sub_i32 s17, 64, s16 ; GFX6-NEXT: s_cmp_lt_u32 s16, 64 -; GFX6-NEXT: s_cselect_b32 s28, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s16, 0 -; GFX6-NEXT: s_cselect_b32 s29, 1, 0 +; GFX6-NEXT: s_cselect_b32 s29, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX6-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 @@ -5959,9 +5959,9 @@ ; GFX6-NEXT: s_sub_i32 s26, s22, 64 ; GFX6-NEXT: s_sub_i32 s24, 64, s22 ; GFX6-NEXT: s_cmp_lt_u32 s22, 64 -; GFX6-NEXT: s_cselect_b32 s27, 1, 0 +; GFX6-NEXT: s_cselect_b32 s27, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s22, 0 -; GFX6-NEXT: s_cselect_b32 s28, 1, 0 +; GFX6-NEXT: s_cselect_b32 s28, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX6-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX6-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -5984,9 +5984,9 @@ ; GFX6-NEXT: s_sub_i32 s9, s10, 64 ; GFX6-NEXT: s_sub_i32 s11, 64, s10 ; GFX6-NEXT: s_cmp_lt_u32 s10, 64 -; GFX6-NEXT: s_cselect_b32 s20, 1, 0 +; GFX6-NEXT: s_cselect_b32 s20, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s10, 0 -; GFX6-NEXT: s_cselect_b32 s21, 1, 0 +; GFX6-NEXT: s_cselect_b32 s21, -1, 0 ; GFX6-NEXT: s_lshl_b64 s[6:7], s[16:17], s10 ; GFX6-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX6-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 @@ -6000,9 +6000,9 @@ ; GFX6-NEXT: s_sub_i32 s18, s8, 64 ; GFX6-NEXT: s_sub_i32 s16, 64, s8 ; GFX6-NEXT: s_cmp_lt_u32 s8, 64 -; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 ; GFX6-NEXT: s_cmp_eq_u32 s8, 0 -; GFX6-NEXT: s_cselect_b32 s20, 1, 0 +; GFX6-NEXT: s_cselect_b32 s20, -1, 0 ; GFX6-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX6-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX6-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 @@ -6032,9 +6032,9 @@ ; GFX8-NEXT: s_sub_i32 s23, s16, 64 ; GFX8-NEXT: s_sub_i32 s17, 64, s16 ; GFX8-NEXT: s_cmp_lt_u32 s16, 64 -; GFX8-NEXT: s_cselect_b32 s28, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s16, 0 -; GFX8-NEXT: s_cselect_b32 s29, 1, 0 +; GFX8-NEXT: s_cselect_b32 s29, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX8-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 @@ -6048,9 +6048,9 @@ ; GFX8-NEXT: s_sub_i32 s26, s22, 64 ; GFX8-NEXT: s_sub_i32 s24, 64, s22 ; GFX8-NEXT: s_cmp_lt_u32 s22, 64 -; GFX8-NEXT: s_cselect_b32 s27, 1, 0 +; GFX8-NEXT: s_cselect_b32 s27, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s22, 0 -; GFX8-NEXT: s_cselect_b32 s28, 1, 0 +; GFX8-NEXT: s_cselect_b32 s28, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX8-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX8-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -6073,9 +6073,9 @@ ; GFX8-NEXT: s_sub_i32 s9, s10, 64 ; GFX8-NEXT: s_sub_i32 s11, 64, s10 ; GFX8-NEXT: s_cmp_lt_u32 s10, 64 -; GFX8-NEXT: s_cselect_b32 s20, 1, 0 +; GFX8-NEXT: s_cselect_b32 s20, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s10, 0 -; GFX8-NEXT: s_cselect_b32 s21, 1, 0 +; GFX8-NEXT: s_cselect_b32 s21, -1, 0 ; GFX8-NEXT: s_lshl_b64 s[6:7], s[16:17], s10 ; GFX8-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX8-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 @@ -6089,9 +6089,9 @@ ; GFX8-NEXT: s_sub_i32 s18, s8, 64 ; GFX8-NEXT: s_sub_i32 s16, 64, s8 ; GFX8-NEXT: s_cmp_lt_u32 s8, 64 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_cmp_eq_u32 s8, 0 -; GFX8-NEXT: s_cselect_b32 s20, 1, 0 +; GFX8-NEXT: s_cselect_b32 s20, -1, 0 ; GFX8-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX8-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX8-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 @@ -6121,9 +6121,9 @@ ; GFX9-NEXT: s_sub_i32 s23, s16, 64 ; GFX9-NEXT: s_sub_i32 s17, 64, s16 ; GFX9-NEXT: s_cmp_lt_u32 s16, 64 -; GFX9-NEXT: s_cselect_b32 s28, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s16, 0 -; GFX9-NEXT: s_cselect_b32 s29, 1, 0 +; GFX9-NEXT: s_cselect_b32 s29, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[2:3], s[24:25], s16 ; GFX9-NEXT: s_lshr_b64 s[26:27], s[24:25], s17 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 @@ -6137,9 +6137,9 @@ ; GFX9-NEXT: s_sub_i32 s26, s22, 64 ; GFX9-NEXT: s_sub_i32 s24, 64, s22 ; GFX9-NEXT: s_cmp_lt_u32 s22, 64 -; GFX9-NEXT: s_cselect_b32 s27, 1, 0 +; GFX9-NEXT: s_cselect_b32 s27, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s22, 0 -; GFX9-NEXT: s_cselect_b32 s28, 1, 0 +; GFX9-NEXT: s_cselect_b32 s28, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[0:1], s[10:11], s22 ; GFX9-NEXT: s_lshl_b64 s[24:25], s[10:11], s24 ; GFX9-NEXT: s_lshr_b64 s[22:23], s[8:9], s22 @@ -6162,9 +6162,9 @@ ; GFX9-NEXT: s_sub_i32 s9, s10, 64 ; GFX9-NEXT: s_sub_i32 s11, 64, s10 ; GFX9-NEXT: s_cmp_lt_u32 s10, 64 -; GFX9-NEXT: s_cselect_b32 s20, 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s10, 0 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_lshl_b64 s[6:7], s[16:17], s10 ; GFX9-NEXT: s_lshr_b64 s[18:19], s[16:17], s11 ; GFX9-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 @@ -6178,9 +6178,9 @@ ; GFX9-NEXT: s_sub_i32 s18, s8, 64 ; GFX9-NEXT: s_sub_i32 s16, 64, s8 ; GFX9-NEXT: s_cmp_lt_u32 s8, 64 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_cmp_eq_u32 s8, 0 -; GFX9-NEXT: s_cselect_b32 s20, 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 ; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], s8 ; GFX9-NEXT: s_lshl_b64 s[16:17], s[14:15], s16 ; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], s8 @@ -6210,9 +6210,9 @@ ; GFX10-NEXT: s_sub_i32 s23, s16, 64 ; GFX10-NEXT: s_sub_i32 s17, 64, s16 ; GFX10-NEXT: s_cmp_lt_u32 s16, 64 -; GFX10-NEXT: s_cselect_b32 s28, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s16, 0 -; GFX10-NEXT: s_cselect_b32 s29, 1, 0 +; GFX10-NEXT: s_cselect_b32 s29, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[24:25], s[0:1], s17 ; GFX10-NEXT: s_lshl_b64 s[26:27], s[2:3], s16 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[0:1], s16 @@ -6226,9 +6226,9 @@ ; GFX10-NEXT: s_sub_i32 s26, s22, 64 ; GFX10-NEXT: s_sub_i32 s23, 64, s22 ; GFX10-NEXT: s_cmp_lt_u32 s22, 64 -; GFX10-NEXT: s_cselect_b32 s27, 1, 0 +; GFX10-NEXT: s_cselect_b32 s27, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s22, 0 -; GFX10-NEXT: s_cselect_b32 s28, 1, 0 +; GFX10-NEXT: s_cselect_b32 s28, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[0:1], s[8:9], s22 ; GFX10-NEXT: s_lshl_b64 s[24:25], s[10:11], s23 ; GFX10-NEXT: s_lshr_b64 s[22:23], s[10:11], s22 @@ -6251,9 +6251,9 @@ ; GFX10-NEXT: s_sub_i32 s9, s10, 64 ; GFX10-NEXT: s_sub_i32 s11, 64, s10 ; GFX10-NEXT: s_cmp_lt_u32 s10, 64 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s10, 0 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[16:17], s[4:5], s11 ; GFX10-NEXT: s_lshl_b64 s[18:19], s[6:7], s10 ; GFX10-NEXT: s_lshl_b64 s[10:11], s[4:5], s10 @@ -6267,9 +6267,9 @@ ; GFX10-NEXT: s_sub_i32 s18, s8, 64 ; GFX10-NEXT: s_sub_i32 s9, 64, s8 ; GFX10-NEXT: s_cmp_lt_u32 s8, 64 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_cmp_eq_u32 s8, 0 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_lshr_b64 s[4:5], s[12:13], s8 ; GFX10-NEXT: s_lshl_b64 s[16:17], s[14:15], s9 ; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], s8 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll @@ -31,7 +31,7 @@ ; GFX: ; %bb.0: ; GFX-NEXT: s_ashr_i32 s2, s1, 31 ; GFX-NEXT: s_add_u32 s0, s0, s2 -; GFX-NEXT: s_cselect_b32 s4, 1, 0 +; GFX-NEXT: s_cselect_b32 s4, -1, 0 ; GFX-NEXT: s_and_b32 s4, s4, 1 ; GFX-NEXT: s_cmp_lg_u32 s4, 0 ; GFX-NEXT: s_mov_b32 s3, s2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll @@ -88,7 +88,7 @@ ; GFX7-LABEL: s_div_fmas_f32: ; GFX7: ; %bb.0: ; GFX7-NEXT: s_cmp_eq_u32 s3, 0 -; GFX7-NEXT: s_cselect_b32 s3, 1, 0 +; GFX7-NEXT: s_cselect_b32 s3, -1, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 ; GFX7-NEXT: s_and_b32 s0, 1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s1 @@ -101,7 +101,7 @@ ; GFX8-LABEL: s_div_fmas_f32: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_cmp_eq_u32 s3, 0 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: s_and_b32 s0, 1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 @@ -116,7 +116,7 @@ ; GFX10_W32-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s1 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s2 -; GFX10_W32-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s3, -1, 0 ; GFX10_W32-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s0, v0, v1 @@ -126,7 +126,7 @@ ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_cmp_eq_u32 s3, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s1 -; GFX10_W64-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s3, -1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s2 ; GFX10_W64-NEXT: s_and_b32 s3, 1, s3 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s3 @@ -142,7 +142,7 @@ ; GFX7: ; %bb.0: ; GFX7-NEXT: s_cmp_eq_u32 s6, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 -; GFX7-NEXT: s_cselect_b32 s6, 1, 0 +; GFX7-NEXT: s_cselect_b32 s6, -1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, s1 ; GFX7-NEXT: v_mov_b32_e32 v2, s2 ; GFX7-NEXT: v_mov_b32_e32 v4, s4 @@ -160,7 +160,7 @@ ; GFX8: ; %bb.0: ; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v2, s2 ; GFX8-NEXT: v_mov_b32_e32 v4, s4 @@ -181,7 +181,7 @@ ; GFX10_W32-NEXT: v_mov_b32_e32 v2, s4 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s3 ; GFX10_W32-NEXT: v_mov_b32_e32 v3, s5 -; GFX10_W32-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10_W32-NEXT: s_and_b32 s6, 1, s6 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s6 ; GFX10_W32-NEXT: v_div_fmas_f64 v[0:1], s[0:1], v[0:1], v[2:3] @@ -193,7 +193,7 @@ ; GFX10_W64: ; %bb.0: ; GFX10_W64-NEXT: s_cmp_eq_u32 s6, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s2 -; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v2, s4 ; GFX10_W64-NEXT: s_and_b32 s6, 1, s6 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s3 @@ -596,7 +596,7 @@ ; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_cmp_eq_u32 s3, 0 -; GFX7-NEXT: s_cselect_b32 s3, 1, 0 +; GFX7-NEXT: s_cselect_b32 s3, -1, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, s0 ; GFX7-NEXT: s_and_b32 s0, 1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s1 @@ -613,7 +613,7 @@ ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_cmp_eq_u32 s7, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, 1, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 ; GFX8-NEXT: v_mov_b32_e32 v1, s5 @@ -635,7 +635,7 @@ ; GFX10_W32-NEXT: s_cmp_eq_u32 s7, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v0, s5 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, s6 -; GFX10_W32-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10_W32-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, s4, v0, v1 @@ -651,7 +651,7 @@ ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_cmp_eq_u32 s7, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v0, s5 -; GFX10_W64-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, s6 ; GFX10_W64-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 @@ -825,7 +825,7 @@ ; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64 offset:8 glc ; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_cmp_lg_u32 s8, 0 -; GFX7-NEXT: s_cselect_b32 s0, 1, 0 +; GFX7-NEXT: s_cselect_b32 s0, -1, 0 ; GFX7-NEXT: s_and_b32 s0, 1, s0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 @@ -859,7 +859,7 @@ ; GFX8-NEXT: s_add_u32 s0, s4, 8 ; GFX8-NEXT: s_addc_u32 s1, s5, 0 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, 1, s2 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 @@ -886,7 +886,7 @@ ; GFX10_W32-NEXT: s_waitcnt vmcnt(0) ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W32-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10_W32-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s0 @@ -909,7 +909,7 @@ ; GFX10_W64-NEXT: s_waitcnt vmcnt(0) ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W64-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10_W64-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[0:1] @@ -956,7 +956,7 @@ ; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_cmp_lg_u32 s0, 0 -; GFX7-NEXT: s_cselect_b32 s6, 1, 0 +; GFX7-NEXT: s_cselect_b32 s6, -1, 0 ; GFX7-NEXT: BB13_2: ; %exit ; GFX7-NEXT: s_or_b64 exec, exec, s[2:3] ; GFX7-NEXT: s_and_b32 s0, 1, s6 @@ -990,7 +990,7 @@ ; GFX8-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_cmp_lg_u32 s0, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: BB13_2: ; %exit ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX8-NEXT: s_add_u32 s0, s2, 8 @@ -1023,7 +1023,7 @@ ; GFX10_W32-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W32-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10_W32-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10_W32-NEXT: BB13_2: ; %exit ; GFX10_W32-NEXT: s_or_b32 exec_lo, exec_lo, s4 ; GFX10_W32-NEXT: s_and_b32 s0, 1, s5 @@ -1053,7 +1053,7 @@ ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x0 ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10_W64-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10_W64-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10_W64-NEXT: BB13_2: ; %exit ; GFX10_W64-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX10_W64-NEXT: s_and_b32 s0, 1, s6 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll @@ -9,7 +9,7 @@ ; GCN-NEXT: s_load_dword s1, s[4:5], 0x24 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s0, 0 -; GCN-NEXT: s_cselect_b32 s0, 1, 0 +; GCN-NEXT: s_cselect_b32 s0, -1, 0 ; GCN-NEXT: s_and_b32 s0, 1, s0 ; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GCN-NEXT: s_or_b32 s0, s0, s1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll @@ -8,7 +8,7 @@ ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xa ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_eq_u32 s2, 0 -; GCN-NEXT: s_cselect_b32 s2, 1, 0 +; GCN-NEXT: s_cselect_b32 s2, -1, 0 ; GCN-NEXT: s_and_b32 s2, 1, s2 ; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll @@ -51,7 +51,7 @@ ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_cmp_lg_u32 s1, 56 -; GCN-NEXT: s_cselect_b32 s0, 1, 0 +; GCN-NEXT: s_cselect_b32 s0, -1, 0 ; GCN-NEXT: s_not_b64 exec, exec ; GCN-NEXT: v_mov_b32_e32 v0, 42 ; GCN-NEXT: s_not_b64 exec, exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll @@ -442,7 +442,7 @@ ; GFX7-NEXT: s_mul_i32 s7, s1, s4 ; GFX7-NEXT: s_mul_i32 s2, s2, s3 ; GFX7-NEXT: v_mul_hi_u32 v3, s0, v3 -; GFX7-NEXT: s_cselect_b32 s8, 1, 0 +; GFX7-NEXT: s_cselect_b32 s8, -1, 0 ; GFX7-NEXT: s_mul_i32 s6, s0, s3 ; GFX7-NEXT: s_mul_i32 s5, s0, s5 ; GFX7-NEXT: s_add_i32 s0, s2, s7 @@ -472,7 +472,7 @@ ; GFX8-NEXT: s_mul_i32 s7, s1, s4 ; GFX8-NEXT: s_mul_i32 s2, s2, s3 ; GFX8-NEXT: v_mul_hi_u32 v3, s0, v3 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_mul_i32 s6, s0, s3 ; GFX8-NEXT: s_mul_i32 s5, s0, s5 ; GFX8-NEXT: s_add_i32 s0, s2, s7 @@ -493,11 +493,11 @@ ; GFX9-NEXT: s_mul_i32 s7, s1, s3 ; GFX9-NEXT: s_mul_i32 s8, s0, s4 ; GFX9-NEXT: s_add_u32 s7, s7, s8 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_mul_hi_u32 s9, s0, s3 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_add_u32 s7, s7, s9 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_add_i32 s8, s8, s9 ; GFX9-NEXT: s_mul_i32 s9, s1, s4 @@ -521,12 +521,12 @@ ; GFX10-NEXT: s_mul_i32 s7, s0, s4 ; GFX10-NEXT: s_mul_hi_u32 s8, s0, s3 ; GFX10-NEXT: s_add_u32 s6, s6, s7 -; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_cselect_b32 s7, -1, 0 ; GFX10-NEXT: s_mul_i32 s9, s1, s4 ; GFX10-NEXT: s_and_b32 s7, s7, 1 ; GFX10-NEXT: s_mul_i32 s2, s2, s3 ; GFX10-NEXT: s_add_u32 s6, s6, s8 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_mul_i32 s5, s0, s5 ; GFX10-NEXT: s_add_i32 s2, s2, s9 ; GFX10-NEXT: s_mul_hi_u32 s1, s1, s3 @@ -656,7 +656,7 @@ ; GFX7-NEXT: s_mul_i32 s9, s1, s4 ; GFX7-NEXT: s_mul_i32 s10, s0, s5 ; GFX7-NEXT: s_add_u32 s9, s9, s10 -; GFX7-NEXT: s_cselect_b32 s10, 1, 0 +; GFX7-NEXT: s_cselect_b32 s10, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s9, v0 ; GFX7-NEXT: s_and_b32 s10, s10, 1 ; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc @@ -665,13 +665,13 @@ ; GFX7-NEXT: s_mul_i32 s10, s1, s5 ; GFX7-NEXT: v_mov_b32_e32 v2, s1 ; GFX7-NEXT: s_add_u32 s9, s9, s10 -; GFX7-NEXT: s_cselect_b32 s10, 1, 0 +; GFX7-NEXT: s_cselect_b32 s10, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v2, v2, s4 ; GFX7-NEXT: s_mul_i32 s11, s0, s6 ; GFX7-NEXT: s_and_b32 s10, s10, 1 ; GFX7-NEXT: s_add_u32 s9, s9, s11 ; GFX7-NEXT: v_mov_b32_e32 v3, s5 -; GFX7-NEXT: s_cselect_b32 s11, 1, 0 +; GFX7-NEXT: s_cselect_b32 s11, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v4, s0, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s9, v2 ; GFX7-NEXT: s_and_b32 s11, s11, 1 @@ -714,7 +714,7 @@ ; GFX8-NEXT: s_mul_i32 s9, s1, s4 ; GFX8-NEXT: s_mul_i32 s10, s0, s5 ; GFX8-NEXT: s_add_u32 s9, s9, s10 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s9, v0 ; GFX8-NEXT: s_and_b32 s10, s10, 1 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc @@ -723,13 +723,13 @@ ; GFX8-NEXT: s_mul_i32 s10, s1, s5 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: s_add_u32 s9, s9, s10 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v2, v2, s4 ; GFX8-NEXT: s_mul_i32 s11, s0, s6 ; GFX8-NEXT: s_and_b32 s10, s10, 1 ; GFX8-NEXT: s_add_u32 s9, s9, s11 ; GFX8-NEXT: v_mov_b32_e32 v3, s5 -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v4, s0, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s9, v2 ; GFX8-NEXT: s_and_b32 s11, s11, 1 @@ -770,35 +770,35 @@ ; GFX9-NEXT: s_mul_i32 s9, s1, s4 ; GFX9-NEXT: s_mul_i32 s10, s0, s5 ; GFX9-NEXT: s_add_u32 s9, s9, s10 -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: s_mul_hi_u32 s11, s0, s4 ; GFX9-NEXT: s_and_b32 s10, s10, 1 ; GFX9-NEXT: s_add_u32 s9, s9, s11 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_and_b32 s11, s11, 1 ; GFX9-NEXT: s_add_i32 s10, s10, s11 ; GFX9-NEXT: s_mul_i32 s11, s2, s4 ; GFX9-NEXT: s_mul_i32 s12, s1, s5 ; GFX9-NEXT: s_add_u32 s11, s11, s12 -; GFX9-NEXT: s_cselect_b32 s12, 1, 0 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 ; GFX9-NEXT: s_mul_i32 s13, s0, s6 ; GFX9-NEXT: s_and_b32 s12, s12, 1 ; GFX9-NEXT: s_add_u32 s11, s11, s13 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_and_b32 s13, s13, 1 ; GFX9-NEXT: s_mul_hi_u32 s14, s1, s4 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_add_u32 s11, s11, s14 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_and_b32 s13, s13, 1 ; GFX9-NEXT: s_mul_hi_u32 s15, s0, s5 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_add_u32 s11, s11, s15 -; GFX9-NEXT: s_cselect_b32 s13, 1, 0 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 ; GFX9-NEXT: s_and_b32 s13, s13, 1 ; GFX9-NEXT: s_add_i32 s12, s12, s13 ; GFX9-NEXT: s_add_u32 s10, s11, s10 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_and_b32 s11, s11, 1 ; GFX9-NEXT: s_add_i32 s12, s12, s11 ; GFX9-NEXT: s_mul_i32 s11, s2, s5 @@ -827,11 +827,11 @@ ; GFX10-NEXT: s_mul_i32 s9, s0, s5 ; GFX10-NEXT: s_mul_hi_u32 s10, s0, s4 ; GFX10-NEXT: s_add_u32 s8, s8, s9 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: s_mul_i32 s11, s1, s5 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_add_u32 s8, s8, s10 -; GFX10-NEXT: s_cselect_b32 s10, 1, 0 +; GFX10-NEXT: s_cselect_b32 s10, -1, 0 ; GFX10-NEXT: s_mul_i32 s12, s0, s6 ; GFX10-NEXT: s_and_b32 s10, s10, 1 ; GFX10-NEXT: s_mul_hi_u32 s13, s1, s4 @@ -839,27 +839,27 @@ ; GFX10-NEXT: s_mul_i32 s10, s2, s4 ; GFX10-NEXT: s_mul_i32 s3, s3, s4 ; GFX10-NEXT: s_add_u32 s10, s10, s11 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, -1, 0 ; GFX10-NEXT: s_mul_i32 s7, s0, s7 ; GFX10-NEXT: s_and_b32 s11, s11, 1 ; GFX10-NEXT: s_add_u32 s10, s10, s12 -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_and_b32 s12, s12, 1 ; GFX10-NEXT: s_add_i32 s11, s11, s12 ; GFX10-NEXT: s_add_u32 s10, s10, s13 -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s13, s0, s5 ; GFX10-NEXT: s_and_b32 s12, s12, 1 ; GFX10-NEXT: s_add_i32 s11, s11, s12 ; GFX10-NEXT: s_add_u32 s10, s10, s13 -; GFX10-NEXT: s_cselect_b32 s12, 1, 0 +; GFX10-NEXT: s_cselect_b32 s12, -1, 0 ; GFX10-NEXT: s_mul_i32 s13, s1, s6 ; GFX10-NEXT: s_and_b32 s12, s12, 1 ; GFX10-NEXT: s_mul_hi_u32 s1, s1, s5 ; GFX10-NEXT: s_add_i32 s11, s11, s12 ; GFX10-NEXT: s_mul_i32 s12, s2, s5 ; GFX10-NEXT: s_add_u32 s9, s10, s9 -; GFX10-NEXT: s_cselect_b32 s10, 1, 0 +; GFX10-NEXT: s_cselect_b32 s10, -1, 0 ; GFX10-NEXT: s_add_i32 s3, s3, s12 ; GFX10-NEXT: s_mul_hi_u32 s2, s2, s4 ; GFX10-NEXT: s_add_i32 s3, s3, s13 @@ -1081,7 +1081,7 @@ ; GFX7-NEXT: s_mul_i32 s17, s1, s8 ; GFX7-NEXT: s_mul_i32 s18, s0, s9 ; GFX7-NEXT: s_add_u32 s17, s17, s18 -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, s17, v0 ; GFX7-NEXT: s_and_b32 s18, s18, 1 ; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc @@ -1090,13 +1090,13 @@ ; GFX7-NEXT: s_mul_i32 s18, s1, s9 ; GFX7-NEXT: v_mov_b32_e32 v2, s1 ; GFX7-NEXT: s_add_u32 s17, s17, s18 -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v2, v2, s8 ; GFX7-NEXT: s_mul_i32 s19, s0, s10 ; GFX7-NEXT: s_and_b32 s18, s18, 1 ; GFX7-NEXT: s_add_u32 s17, s17, s19 ; GFX7-NEXT: v_mov_b32_e32 v3, s9 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v4, s0, v3 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, s17, v2 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1108,14 +1108,14 @@ ; GFX7-NEXT: s_mul_i32 s18, s2, s9 ; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s18 -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX7-NEXT: v_add_i32_e32 v1, vcc, v2, v1 ; GFX7-NEXT: s_mul_i32 s19, s1, s10 ; GFX7-NEXT: s_and_b32 s18, s18, 1 ; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s19 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GFX7-NEXT: v_mov_b32_e32 v4, s2 ; GFX7-NEXT: v_mul_hi_u32 v5, v4, s8 @@ -1123,7 +1123,7 @@ ; GFX7-NEXT: s_mul_i32 s20, s0, s11 ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: s_add_u32 s17, s17, s20 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v3, s1, v3 ; GFX7-NEXT: v_add_i32_e32 v5, vcc, s17, v5 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1137,13 +1137,13 @@ ; GFX7-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GFX7-NEXT: s_add_u32 s17, s17, s18 ; GFX7-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; GFX7-NEXT: s_mul_i32 s19, s2, s10 ; GFX7-NEXT: s_and_b32 s18, s18, 1 ; GFX7-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GFX7-NEXT: s_add_u32 s17, s17, s19 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX7-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1152,7 +1152,7 @@ ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s20 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v3, vcc, v5, v3 ; GFX7-NEXT: v_mov_b32_e32 v5, s3 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1160,7 +1160,7 @@ ; GFX7-NEXT: s_mul_i32 s21, s0, s12 ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: s_add_u32 s17, s17, s21 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v7, vcc, s17, v7 ; GFX7-NEXT: s_and_b32 s19, s19, 1 ; GFX7-NEXT: v_mul_hi_u32 v4, v4, s9 @@ -1171,7 +1171,7 @@ ; GFX7-NEXT: s_mul_i32 s18, s4, s9 ; GFX7-NEXT: s_add_u32 s17, s17, s18 ; GFX7-NEXT: v_mul_hi_u32 v8, s1, v6 -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX7-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX7-NEXT: v_mov_b32_e32 v9, s11 @@ -1180,7 +1180,7 @@ ; GFX7-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; GFX7-NEXT: s_add_u32 s17, s17, s19 ; GFX7-NEXT: v_mul_hi_u32 v10, s0, v9 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1189,7 +1189,7 @@ ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: v_add_i32_e32 v4, vcc, v4, v10 ; GFX7-NEXT: s_add_u32 s17, s17, s20 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX7-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1198,7 +1198,7 @@ ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s21 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v4, vcc, v7, v4 ; GFX7-NEXT: v_mov_b32_e32 v7, s4 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1206,7 +1206,7 @@ ; GFX7-NEXT: s_mul_i32 s22, s0, s13 ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: s_add_u32 s17, s17, s22 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v8, vcc, s17, v8 ; GFX7-NEXT: s_and_b32 s19, s19, 1 ; GFX7-NEXT: v_mul_hi_u32 v10, v5, s9 @@ -1216,14 +1216,14 @@ ; GFX7-NEXT: s_mul_i32 s17, s6, s8 ; GFX7-NEXT: s_mul_i32 s18, s5, s9 ; GFX7-NEXT: s_add_u32 s17, s17, s18 -; GFX7-NEXT: s_cselect_b32 s18, 1, 0 +; GFX7-NEXT: s_cselect_b32 s18, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v6, s2, v6 ; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GFX7-NEXT: s_mul_i32 s19, s4, s10 ; GFX7-NEXT: s_and_b32 s18, s18, 1 ; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s19 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v10, vcc, v14, v10 ; GFX7-NEXT: v_mul_hi_u32 v11, s1, v9 ; GFX7-NEXT: v_add_i32_e32 v6, vcc, v8, v6 @@ -1235,7 +1235,7 @@ ; GFX7-NEXT: v_add_i32_e32 v8, vcc, v10, v8 ; GFX7-NEXT: s_add_u32 s17, s17, s20 ; GFX7-NEXT: v_mul_hi_u32 v13, s0, v12 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v6, vcc, v6, v11 ; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1244,7 +1244,7 @@ ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: v_add_i32_e32 v6, vcc, v6, v13 ; GFX7-NEXT: s_add_u32 s17, s17, s21 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX7-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1253,7 +1253,7 @@ ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX7-NEXT: s_add_u32 s17, s17, s22 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_add_i32_e32 v6, vcc, v8, v6 ; GFX7-NEXT: v_mov_b32_e32 v8, s5 ; GFX7-NEXT: v_mul_hi_u32 v10, v8, s8 @@ -1261,7 +1261,7 @@ ; GFX7-NEXT: s_mul_i32 s23, s0, s14 ; GFX7-NEXT: s_add_i32 s18, s18, s19 ; GFX7-NEXT: s_add_u32 s17, s17, s23 -; GFX7-NEXT: s_cselect_b32 s19, 1, 0 +; GFX7-NEXT: s_cselect_b32 s19, -1, 0 ; GFX7-NEXT: v_mul_hi_u32 v11, v7, s9 ; GFX7-NEXT: v_add_i32_e32 v10, vcc, s17, v10 ; GFX7-NEXT: s_and_b32 s19, s19, 1 @@ -1341,7 +1341,7 @@ ; GFX8-NEXT: s_mul_i32 s17, s1, s8 ; GFX8-NEXT: s_mul_i32 s18, s0, s9 ; GFX8-NEXT: s_add_u32 s17, s17, s18 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s17, v0 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc @@ -1350,13 +1350,13 @@ ; GFX8-NEXT: s_mul_i32 s18, s1, s9 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 ; GFX8-NEXT: s_add_u32 s17, s17, s18 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v2, v2, s8 ; GFX8-NEXT: s_mul_i32 s19, s0, s10 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: s_add_u32 s17, s17, s19 ; GFX8-NEXT: v_mov_b32_e32 v3, s9 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v4, s0, v3 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, s17, v2 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1368,14 +1368,14 @@ ; GFX8-NEXT: s_mul_i32 s18, s2, s9 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s18 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v5, v4 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1 ; GFX8-NEXT: s_mul_i32 s19, s1, s10 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s19 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2 ; GFX8-NEXT: v_mov_b32_e32 v4, s2 ; GFX8-NEXT: v_mul_hi_u32 v5, v4, s8 @@ -1383,7 +1383,7 @@ ; GFX8-NEXT: s_mul_i32 s20, s0, s11 ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: s_add_u32 s17, s17, s20 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v3, s1, v3 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, s17, v5 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1397,13 +1397,13 @@ ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: s_add_u32 s17, s17, s18 ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v8, v5 ; GFX8-NEXT: s_mul_i32 s19, s2, s10 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v7 ; GFX8-NEXT: s_add_u32 s17, s17, s19 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v7 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1412,7 +1412,7 @@ ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s20 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v5, v3 ; GFX8-NEXT: v_mov_b32_e32 v5, s3 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1420,7 +1420,7 @@ ; GFX8-NEXT: s_mul_i32 s21, s0, s12 ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: s_add_u32 s17, s17, s21 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v7, vcc, s17, v7 ; GFX8-NEXT: s_and_b32 s19, s19, 1 ; GFX8-NEXT: v_mul_hi_u32 v4, v4, s9 @@ -1431,7 +1431,7 @@ ; GFX8-NEXT: s_mul_i32 s18, s4, s9 ; GFX8-NEXT: s_add_u32 s17, s17, s18 ; GFX8-NEXT: v_mul_hi_u32 v8, s1, v6 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; GFX8-NEXT: v_mov_b32_e32 v9, s11 @@ -1440,7 +1440,7 @@ ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v11, v7 ; GFX8-NEXT: s_add_u32 s17, s17, s19 ; GFX8-NEXT: v_mul_hi_u32 v10, s0, v9 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v8 ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1449,7 +1449,7 @@ ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v10 ; GFX8-NEXT: s_add_u32 s17, s17, s20 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; GFX8-NEXT: v_add_u32_e32 v7, vcc, v7, v8 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1458,7 +1458,7 @@ ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s21 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v7, v4 ; GFX8-NEXT: v_mov_b32_e32 v7, s4 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1466,7 +1466,7 @@ ; GFX8-NEXT: s_mul_i32 s22, s0, s13 ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: s_add_u32 s17, s17, s22 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, s17, v8 ; GFX8-NEXT: s_and_b32 s19, s19, 1 ; GFX8-NEXT: v_mul_hi_u32 v10, v5, s9 @@ -1476,14 +1476,14 @@ ; GFX8-NEXT: s_mul_i32 s17, s6, s8 ; GFX8-NEXT: s_mul_i32 s18, s5, s9 ; GFX8-NEXT: s_add_u32 s17, s17, s18 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v6, s2, v6 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10 ; GFX8-NEXT: s_mul_i32 s19, s4, s10 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s19 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, v14, v10 ; GFX8-NEXT: v_mul_hi_u32 v11, s1, v9 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6 @@ -1495,7 +1495,7 @@ ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v10, v8 ; GFX8-NEXT: s_add_u32 s17, s17, s20 ; GFX8-NEXT: v_mul_hi_u32 v13, s0, v12 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v11 ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1504,7 +1504,7 @@ ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v13 ; GFX8-NEXT: s_add_u32 s17, s17, s21 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v10 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1513,7 +1513,7 @@ ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: s_add_u32 s17, s17, s22 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_add_u32_e32 v6, vcc, v8, v6 ; GFX8-NEXT: v_mov_b32_e32 v8, s5 ; GFX8-NEXT: v_mul_hi_u32 v10, v8, s8 @@ -1521,7 +1521,7 @@ ; GFX8-NEXT: s_mul_i32 s23, s0, s14 ; GFX8-NEXT: s_add_i32 s18, s18, s19 ; GFX8-NEXT: s_add_u32 s17, s17, s23 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: v_mul_hi_u32 v11, v7, s9 ; GFX8-NEXT: v_add_u32_e32 v10, vcc, s17, v10 ; GFX8-NEXT: s_and_b32 s19, s19, 1 @@ -1599,231 +1599,231 @@ ; GFX9-NEXT: s_mul_i32 s17, s1, s8 ; GFX9-NEXT: s_mul_i32 s18, s0, s9 ; GFX9-NEXT: s_add_u32 s17, s17, s18 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_mul_hi_u32 s19, s0, s8 ; GFX9-NEXT: s_and_b32 s18, s18, 1 ; GFX9-NEXT: s_add_u32 s17, s17, s19 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_and_b32 s19, s19, 1 ; GFX9-NEXT: s_add_i32 s18, s18, s19 ; GFX9-NEXT: s_mul_i32 s19, s2, s8 ; GFX9-NEXT: s_mul_i32 s20, s1, s9 ; GFX9-NEXT: s_add_u32 s19, s19, s20 -; GFX9-NEXT: s_cselect_b32 s20, 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 ; GFX9-NEXT: s_mul_i32 s21, s0, s10 ; GFX9-NEXT: s_and_b32 s20, s20, 1 ; GFX9-NEXT: s_add_u32 s19, s19, s21 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_and_b32 s21, s21, 1 ; GFX9-NEXT: s_mul_hi_u32 s22, s1, s8 ; GFX9-NEXT: s_add_i32 s20, s20, s21 ; GFX9-NEXT: s_add_u32 s19, s19, s22 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_and_b32 s21, s21, 1 ; GFX9-NEXT: s_mul_hi_u32 s23, s0, s9 ; GFX9-NEXT: s_add_i32 s20, s20, s21 ; GFX9-NEXT: s_add_u32 s19, s19, s23 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_and_b32 s21, s21, 1 ; GFX9-NEXT: s_add_i32 s20, s20, s21 ; GFX9-NEXT: s_add_u32 s18, s19, s18 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_and_b32 s19, s19, 1 ; GFX9-NEXT: s_add_i32 s20, s20, s19 ; GFX9-NEXT: s_mul_i32 s19, s3, s8 ; GFX9-NEXT: s_mul_i32 s21, s2, s9 ; GFX9-NEXT: s_add_u32 s19, s19, s21 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_mul_i32 s22, s1, s10 ; GFX9-NEXT: s_and_b32 s21, s21, 1 ; GFX9-NEXT: s_add_u32 s19, s19, s22 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_mul_i32 s23, s0, s11 ; GFX9-NEXT: s_add_i32 s21, s21, s22 ; GFX9-NEXT: s_add_u32 s19, s19, s23 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_mul_hi_u32 s24, s2, s8 ; GFX9-NEXT: s_add_i32 s21, s21, s22 ; GFX9-NEXT: s_add_u32 s19, s19, s24 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_mul_hi_u32 s25, s1, s9 ; GFX9-NEXT: s_add_i32 s21, s21, s22 ; GFX9-NEXT: s_add_u32 s19, s19, s25 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_mul_hi_u32 s26, s0, s10 ; GFX9-NEXT: s_add_i32 s21, s21, s22 ; GFX9-NEXT: s_add_u32 s19, s19, s26 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_add_i32 s21, s21, s22 ; GFX9-NEXT: s_add_u32 s19, s19, s20 -; GFX9-NEXT: s_cselect_b32 s20, 1, 0 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 ; GFX9-NEXT: s_and_b32 s20, s20, 1 ; GFX9-NEXT: s_add_i32 s21, s21, s20 ; GFX9-NEXT: s_mul_i32 s20, s4, s8 ; GFX9-NEXT: s_mul_i32 s22, s3, s9 ; GFX9-NEXT: s_add_u32 s20, s20, s22 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_mul_i32 s23, s2, s10 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_add_u32 s20, s20, s23 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_i32 s24, s1, s11 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s24 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_i32 s25, s0, s12 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s25 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_hi_u32 s26, s3, s8 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s26 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_hi_u32 s27, s2, s9 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s27 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_hi_u32 s28, s1, s10 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s28 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_mul_hi_u32 s29, s0, s11 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s29 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_add_i32 s22, s22, s23 ; GFX9-NEXT: s_add_u32 s20, s20, s21 -; GFX9-NEXT: s_cselect_b32 s21, 1, 0 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 ; GFX9-NEXT: s_and_b32 s21, s21, 1 ; GFX9-NEXT: s_add_i32 s22, s22, s21 ; GFX9-NEXT: s_mul_i32 s21, s5, s8 ; GFX9-NEXT: s_mul_i32 s23, s4, s9 ; GFX9-NEXT: s_add_u32 s21, s21, s23 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_mul_i32 s24, s3, s10 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_add_u32 s21, s21, s24 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_i32 s25, s2, s11 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s25 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_i32 s26, s1, s12 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s26 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_i32 s27, s0, s13 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s27 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_hi_u32 s28, s4, s8 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s28 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_hi_u32 s29, s3, s9 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s29 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_hi_u32 s30, s2, s10 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s30 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_hi_u32 s31, s1, s11 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s31 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_mul_hi_u32 s33, s0, s12 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s33 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_add_i32 s23, s23, s24 ; GFX9-NEXT: s_add_u32 s21, s21, s22 -; GFX9-NEXT: s_cselect_b32 s22, 1, 0 +; GFX9-NEXT: s_cselect_b32 s22, -1, 0 ; GFX9-NEXT: s_and_b32 s22, s22, 1 ; GFX9-NEXT: s_add_i32 s23, s23, s22 ; GFX9-NEXT: s_mul_i32 s22, s6, s8 ; GFX9-NEXT: s_mul_i32 s24, s5, s9 ; GFX9-NEXT: s_add_u32 s22, s22, s24 -; GFX9-NEXT: s_cselect_b32 s24, 1, 0 +; GFX9-NEXT: s_cselect_b32 s24, -1, 0 ; GFX9-NEXT: s_mul_i32 s25, s4, s10 ; GFX9-NEXT: s_and_b32 s24, s24, 1 ; GFX9-NEXT: s_add_u32 s22, s22, s25 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_i32 s26, s3, s11 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s26 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_i32 s27, s2, s12 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s27 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_i32 s28, s1, s13 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s28 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_i32 s29, s0, s14 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s29 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s30, s5, s8 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s30 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s31, s4, s9 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s31 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s33, s3, s10 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s33 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s34, s2, s11 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s34 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s35, s1, s12 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s35 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_mul_hi_u32 s36, s0, s13 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s36 -; GFX9-NEXT: s_cselect_b32 s25, 1, 0 +; GFX9-NEXT: s_cselect_b32 s25, -1, 0 ; GFX9-NEXT: s_and_b32 s25, s25, 1 ; GFX9-NEXT: s_add_i32 s24, s24, s25 ; GFX9-NEXT: s_add_u32 s22, s22, s23 -; GFX9-NEXT: s_cselect_b32 s23, 1, 0 +; GFX9-NEXT: s_cselect_b32 s23, -1, 0 ; GFX9-NEXT: s_and_b32 s23, s23, 1 ; GFX9-NEXT: s_add_i32 s24, s24, s23 ; GFX9-NEXT: s_mul_i32 s23, s6, s9 @@ -1872,11 +1872,11 @@ ; GFX10-NEXT: s_mul_i32 s17, s0, s9 ; GFX10-NEXT: s_mul_hi_u32 s18, s0, s8 ; GFX10-NEXT: s_add_u32 s16, s16, s17 -; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: s_mul_i32 s19, s1, s9 ; GFX10-NEXT: s_and_b32 s17, s17, 1 ; GFX10-NEXT: s_add_u32 s16, s16, s18 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_mul_i32 s20, s0, s10 ; GFX10-NEXT: s_and_b32 s18, s18, 1 ; GFX10-NEXT: s_mul_hi_u32 s21, s1, s8 @@ -1884,29 +1884,29 @@ ; GFX10-NEXT: s_mul_i32 s18, s2, s8 ; GFX10-NEXT: s_mul_i32 s22, s0, s11 ; GFX10-NEXT: s_add_u32 s18, s18, s19 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_mul_i32 s23, s1, s11 ; GFX10-NEXT: s_and_b32 s19, s19, 1 ; GFX10-NEXT: s_add_u32 s18, s18, s20 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_mul_i32 s24, s0, s12 ; GFX10-NEXT: s_and_b32 s20, s20, 1 ; GFX10-NEXT: s_mul_i32 s25, s4, s9 ; GFX10-NEXT: s_add_i32 s19, s19, s20 ; GFX10-NEXT: s_add_u32 s18, s18, s21 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s21, s0, s9 ; GFX10-NEXT: s_and_b32 s20, s20, 1 ; GFX10-NEXT: s_mul_i32 s26, s2, s11 ; GFX10-NEXT: s_add_i32 s19, s19, s20 ; GFX10-NEXT: s_add_u32 s18, s18, s21 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_mul_i32 s21, s1, s10 ; GFX10-NEXT: s_and_b32 s20, s20, 1 ; GFX10-NEXT: s_mul_i32 s27, s0, s13 ; GFX10-NEXT: s_add_i32 s19, s19, s20 ; GFX10-NEXT: s_add_u32 s17, s18, s17 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: s_mul_i32 s20, s2, s9 ; GFX10-NEXT: s_and_b32 s18, s18, 1 ; GFX10-NEXT: s_mul_hi_u32 s28, s3, s9 @@ -1914,196 +1914,196 @@ ; GFX10-NEXT: s_mul_i32 s18, s3, s8 ; GFX10-NEXT: s_mul_i32 s7, s7, s8 ; GFX10-NEXT: s_add_u32 s18, s18, s20 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_mul_i32 s15, s0, s15 ; GFX10-NEXT: s_and_b32 s20, s20, 1 ; GFX10-NEXT: s_add_u32 s18, s18, s21 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s21 ; GFX10-NEXT: s_add_u32 s18, s18, s22 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s22, s2, s8 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s21 ; GFX10-NEXT: s_add_u32 s18, s18, s22 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s22, s1, s9 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s21 ; GFX10-NEXT: s_add_u32 s18, s18, s22 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s22, s0, s10 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s21 ; GFX10-NEXT: s_add_u32 s18, s18, s22 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_mul_i32 s22, s2, s10 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s21 ; GFX10-NEXT: s_add_u32 s18, s18, s19 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_mul_i32 s21, s3, s9 ; GFX10-NEXT: s_and_b32 s19, s19, 1 ; GFX10-NEXT: s_add_i32 s20, s20, s19 ; GFX10-NEXT: s_mul_i32 s19, s4, s8 ; GFX10-NEXT: s_add_u32 s19, s19, s21 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_u32 s19, s19, s22 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s23 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s23, s3, s8 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s24 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s24, s2, s9 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s23 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s23, s1, s10 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s24 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s24, s0, s11 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s23 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_i32 s23, s5, s8 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s24 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_i32 s24, s3, s10 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s22 ; GFX10-NEXT: s_add_u32 s19, s19, s20 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_mul_i32 s22, s1, s12 ; GFX10-NEXT: s_and_b32 s20, s20, 1 ; GFX10-NEXT: s_add_i32 s21, s21, s20 ; GFX10-NEXT: s_add_u32 s23, s23, s25 -; GFX10-NEXT: s_cselect_b32 s25, 1, 0 +; GFX10-NEXT: s_cselect_b32 s25, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s20, s4, s8 ; GFX10-NEXT: s_and_b32 s25, s25, 1 ; GFX10-NEXT: s_add_u32 s23, s23, s24 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s24, s25, s24 ; GFX10-NEXT: s_add_u32 s23, s23, s26 -; GFX10-NEXT: s_cselect_b32 s25, 1, 0 +; GFX10-NEXT: s_cselect_b32 s25, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s26, s2, s10 ; GFX10-NEXT: s_and_b32 s25, s25, 1 ; GFX10-NEXT: s_add_i32 s24, s24, s25 ; GFX10-NEXT: s_add_u32 s22, s23, s22 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s25, s1, s11 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s23, s24, s23 ; GFX10-NEXT: s_add_u32 s22, s22, s27 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s27, s0, s12 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s20, s22, s20 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_mul_i32 s24, s6, s8 ; GFX10-NEXT: s_and_b32 s22, s22, 1 ; GFX10-NEXT: s_add_i32 s22, s23, s22 ; GFX10-NEXT: s_add_u32 s20, s20, s28 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_i32 s28, s5, s9 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s22, s22, s23 ; GFX10-NEXT: s_add_u32 s20, s20, s26 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_i32 s26, s4, s10 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s22, s22, s23 ; GFX10-NEXT: s_add_u32 s20, s20, s25 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_i32 s25, s3, s11 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s22, s22, s23 ; GFX10-NEXT: s_add_u32 s20, s20, s27 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_i32 s27, s2, s12 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s22, s22, s23 ; GFX10-NEXT: s_add_u32 s20, s20, s21 -; GFX10-NEXT: s_cselect_b32 s21, 1, 0 +; GFX10-NEXT: s_cselect_b32 s21, -1, 0 ; GFX10-NEXT: s_mul_i32 s23, s1, s13 ; GFX10-NEXT: s_and_b32 s21, s21, 1 ; GFX10-NEXT: s_add_i32 s22, s22, s21 ; GFX10-NEXT: s_add_u32 s21, s24, s28 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_i32 s28, s0, s14 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_u32 s21, s21, s26 -; GFX10-NEXT: s_cselect_b32 s26, 1, 0 +; GFX10-NEXT: s_cselect_b32 s26, -1, 0 ; GFX10-NEXT: s_and_b32 s26, s26, 1 ; GFX10-NEXT: s_add_i32 s24, s24, s26 ; GFX10-NEXT: s_add_u32 s21, s21, s25 -; GFX10-NEXT: s_cselect_b32 s25, 1, 0 +; GFX10-NEXT: s_cselect_b32 s25, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s26, s5, s8 ; GFX10-NEXT: s_and_b32 s25, s25, 1 ; GFX10-NEXT: s_add_i32 s24, s24, s25 ; GFX10-NEXT: s_add_u32 s21, s21, s27 -; GFX10-NEXT: s_cselect_b32 s25, 1, 0 +; GFX10-NEXT: s_cselect_b32 s25, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s27, s4, s9 ; GFX10-NEXT: s_and_b32 s25, s25, 1 ; GFX10-NEXT: s_add_i32 s24, s24, s25 ; GFX10-NEXT: s_add_u32 s21, s21, s23 -; GFX10-NEXT: s_cselect_b32 s23, 1, 0 +; GFX10-NEXT: s_cselect_b32 s23, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s25, s3, s10 ; GFX10-NEXT: s_and_b32 s23, s23, 1 ; GFX10-NEXT: s_add_i32 s23, s24, s23 ; GFX10-NEXT: s_add_u32 s21, s21, s28 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s28, s2, s11 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s26 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s26, s1, s12 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s27 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_hi_u32 s27, s0, s13 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s25 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_i32 s25, s6, s9 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_mul_hi_u32 s6, s6, s8 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s28 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s26 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_i32 s26, s5, s10 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_mul_hi_u32 s5, s5, s9 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s27 -; GFX10-NEXT: s_cselect_b32 s24, 1, 0 +; GFX10-NEXT: s_cselect_b32 s24, -1, 0 ; GFX10-NEXT: s_mul_i32 s27, s4, s11 ; GFX10-NEXT: s_and_b32 s24, s24, 1 ; GFX10-NEXT: s_mul_hi_u32 s4, s4, s10 ; GFX10-NEXT: s_add_i32 s23, s23, s24 ; GFX10-NEXT: s_add_u32 s21, s21, s22 -; GFX10-NEXT: s_cselect_b32 s22, 1, 0 +; GFX10-NEXT: s_cselect_b32 s22, -1, 0 ; GFX10-NEXT: s_add_i32 s7, s7, s25 ; GFX10-NEXT: s_mul_i32 s24, s3, s12 ; GFX10-NEXT: s_add_i32 s7, s7, s26 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll @@ -1003,10 +1003,10 @@ ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000 ; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000 ; GFX8-NEXT: s_cmp_lt_i32 s3, s0 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000 ; GFX8-NEXT: s_cmp_lt_i32 s1, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_xor_b32 s0, s1, s0 ; GFX8-NEXT: s_ashr_i32 s1, s3, 23 ; GFX8-NEXT: s_add_i32 s1, s1, 0xff800000 @@ -4209,7 +4209,7 @@ ; GFX6-LABEL: s_saddsat_i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s4, s0, s2 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_and_b32 s5, s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s5, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 @@ -4220,7 +4220,7 @@ ; GFX6-NEXT: s_ashr_i32 s2, s5, 31 ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX6-NEXT: s_add_u32 s0, s2, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4237,7 +4237,7 @@ ; GFX8-LABEL: s_saddsat_i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s4, s0, s2 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_and_b32 s5, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -4248,7 +4248,7 @@ ; GFX8-NEXT: s_ashr_i32 s2, s5, 31 ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX8-NEXT: s_add_u32 s0, s2, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4265,7 +4265,7 @@ ; GFX9-LABEL: s_saddsat_i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s4, s0, s2 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_and_b32 s5, s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s5, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 @@ -4276,7 +4276,7 @@ ; GFX9-NEXT: s_ashr_i32 s2, s5, 31 ; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX9-NEXT: s_add_u32 s0, s2, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4293,7 +4293,7 @@ ; GFX10-LABEL: s_saddsat_i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s4, s0, s2 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_and_b32 s5, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 @@ -4304,7 +4304,7 @@ ; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: s_xor_b32 s3, s1, s0 ; GFX10-NEXT: s_add_u32 s0, s2, 0 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s3 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 @@ -4563,7 +4563,7 @@ ; GFX6-LABEL: s_saddsat_v2i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s8, s0, s4 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 @@ -4574,7 +4574,7 @@ ; GFX6-NEXT: s_ashr_i32 s4, s9, 31 ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX6-NEXT: s_add_u32 s0, s4, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 @@ -4582,7 +4582,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: s_add_u32 s0, s2, s6 ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: v_mov_b32_e32 v0, s8 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 @@ -4598,7 +4598,7 @@ ; GFX6-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: s_add_u32 s0, s4, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s3, s4, s5 @@ -4616,7 +4616,7 @@ ; GFX8-LABEL: s_saddsat_v2i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s8, s0, s4 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -4627,7 +4627,7 @@ ; GFX8-NEXT: s_ashr_i32 s4, s9, 31 ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX8-NEXT: s_add_u32 s0, s4, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_brev_b32 s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 @@ -4635,7 +4635,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: s_add_u32 s0, s2, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 @@ -4651,7 +4651,7 @@ ; GFX8-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: s_add_u32 s0, s4, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s3, s4, s5 @@ -4669,7 +4669,7 @@ ; GFX9-LABEL: s_saddsat_v2i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s8, s0, s4 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 @@ -4680,7 +4680,7 @@ ; GFX9-NEXT: s_ashr_i32 s4, s9, 31 ; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX9-NEXT: s_add_u32 s0, s4, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_brev_b32 s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 @@ -4688,7 +4688,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: s_add_u32 s0, s2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 @@ -4704,7 +4704,7 @@ ; GFX9-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: s_add_u32 s0, s4, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s3, s4, s5 @@ -4722,7 +4722,7 @@ ; GFX10-LABEL: s_saddsat_v2i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s8, s0, s4 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[4:5], 0 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, s8 @@ -4734,13 +4734,13 @@ ; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: s_xor_b32 s8, s4, s0 ; GFX10-NEXT: s_add_u32 s0, s1, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s10 ; GFX10-NEXT: s_add_u32 s4, s2, s6 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8 ; GFX10-NEXT: s_and_b32 s5, s5, 1 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 @@ -4752,7 +4752,7 @@ ; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: s_xor_b32 s2, s3, s2 ; GFX10-NEXT: s_add_u32 s0, s1, 0 -; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_cselect_b32 s3, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2 ; GFX10-NEXT: s_and_b32 s3, s3, 1 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 @@ -4771,15 +4771,15 @@ ; GFX6-LABEL: s_saddsat_i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s4, s0, s4 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: s_addc_u32 s5, s1, s5 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: s_addc_u32 s8, s2, s6 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0 @@ -4798,16 +4798,16 @@ ; GFX6-NEXT: s_ashr_i32 s3, s9, 31 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX6-NEXT: s_add_u32 s0, s3, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s3, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s2, s3, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s6, s6, 1 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 @@ -4835,15 +4835,15 @@ ; GFX8-LABEL: s_saddsat_i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s4, s0, s4 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_addc_u32 s5, s1, s5 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_addc_u32 s8, s2, s6 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 @@ -4853,7 +4853,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 @@ -4861,23 +4861,23 @@ ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX8-NEXT: s_ashr_i32 s3, s9, 31 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX8-NEXT: s_add_u32 s0, s3, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s3, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s2, s3, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s6, s6, 1 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 @@ -4905,15 +4905,15 @@ ; GFX9-LABEL: s_saddsat_i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s4, s0, s4 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: s_addc_u32 s5, s1, s5 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: s_addc_u32 s8, s2, s6 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 @@ -4923,7 +4923,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 @@ -4931,23 +4931,23 @@ ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[6:7], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX9-NEXT: s_ashr_i32 s3, s9, 31 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX9-NEXT: s_add_u32 s0, s3, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s3, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s2, s3, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s6, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s6, 0 @@ -4975,17 +4975,17 @@ ; GFX10-LABEL: s_saddsat_i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s4, s0, s4 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s5, s1, s5 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[4:5], s[0:1] ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_mov_b32_e32 v2, s5 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s8, s2, s6 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, s8 @@ -4993,14 +4993,14 @@ ; GFX10-NEXT: s_addc_u32 s9, s3, s7 ; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[8:9], s[2:3] -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, s9 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[6:7], 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_ashr_i32 s3, s9, 31 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 @@ -5008,18 +5008,18 @@ ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0 ; GFX10-NEXT: s_add_u32 s0, s3, 0 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s4 ; GFX10-NEXT: s_addc_u32 s1, s3, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s2, s2, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 @@ -5225,7 +5225,7 @@ ; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s4 @@ -5262,7 +5262,7 @@ ; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[2:3], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s4 @@ -5290,7 +5290,7 @@ ; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[2:3], 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: s_and_b32 s0, 1, s0 @@ -5560,15 +5560,15 @@ ; GFX6-LABEL: s_saddsat_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s8, s0, s8 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_and_b32 s16, s16, 1 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_addc_u32 s9, s1, s9 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_and_b32 s16, s16, 1 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_addc_u32 s16, s2, s10 -; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s17, s17, 1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0 @@ -5587,15 +5587,15 @@ ; GFX6-NEXT: s_ashr_i32 s3, s17, 31 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX6-NEXT: s_add_u32 s0, s3, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s3, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s2, s3, 0 -; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 ; GFX6-NEXT: s_and_b32 s11, s11, 1 ; GFX6-NEXT: s_brev_b32 s10, 1 ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 @@ -5605,14 +5605,14 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: s_add_u32 s0, s4, s12 ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_addc_u32 s1, s5, s13 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_mov_b32_e32 v0, s2 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, s9 @@ -5623,7 +5623,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v3, s17 ; GFX6-NEXT: s_addc_u32 s2, s6, s14 -; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cselect_b32 s3, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc ; GFX6-NEXT: v_mov_b32_e32 v2, s4 @@ -5644,16 +5644,16 @@ ; GFX6-NEXT: s_ashr_i32 s7, s3, 31 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] ; GFX6-NEXT: s_add_u32 s4, s7, 0 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_and_b32 s5, s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s5, 0 ; GFX6-NEXT: s_addc_u32 s5, s7, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 ; GFX6-NEXT: s_and_b32 s6, s6, 1 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 ; GFX6-NEXT: s_addc_u32 s6, s7, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 @@ -5685,15 +5685,15 @@ ; GFX8-LABEL: s_saddsat_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s8, s0, s8 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_and_b32 s16, s16, 1 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_addc_u32 s9, s1, s9 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_and_b32 s16, s16, 1 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_addc_u32 s16, s2, s10 -; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_and_b32 s17, s17, 1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 @@ -5703,7 +5703,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 @@ -5711,22 +5711,22 @@ ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX8-NEXT: s_ashr_i32 s3, s17, 31 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX8-NEXT: s_add_u32 s0, s3, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s3, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s2, s3, 0 -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: s_and_b32 s11, s11, 1 ; GFX8-NEXT: s_brev_b32 s10, 1 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 @@ -5736,14 +5736,14 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: s_add_u32 s0, s4, s12 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_addc_u32 s1, s5, s13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: v_mov_b32_e32 v4, s9 @@ -5752,7 +5752,7 @@ ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s16 ; GFX8-NEXT: v_mov_b32_e32 v3, s17 ; GFX8-NEXT: s_and_b32 s3, s3, 1 @@ -5766,7 +5766,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s4, 1, s6 @@ -5774,23 +5774,23 @@ ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] ; GFX8-NEXT: s_and_b32 s4, 1, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX8-NEXT: s_ashr_i32 s7, s3, 31 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] ; GFX8-NEXT: s_add_u32 s4, s7, 0 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_and_b32 s5, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_addc_u32 s5, s7, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: s_and_b32 s6, s6, 1 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_addc_u32 s6, s7, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 @@ -5822,15 +5822,15 @@ ; GFX9-LABEL: s_saddsat_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s8, s0, s8 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_and_b32 s16, s16, 1 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_addc_u32 s9, s1, s9 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_and_b32 s16, s16, 1 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_addc_u32 s16, s2, s10 -; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_and_b32 s17, s17, 1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 @@ -5840,7 +5840,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[16:17], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 @@ -5848,22 +5848,22 @@ ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], s[10:11], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX9-NEXT: s_ashr_i32 s3, s17, 31 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[0:1] ; GFX9-NEXT: s_add_u32 s0, s3, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s3, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s2, s3, 0 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_and_b32 s11, s11, 1 ; GFX9-NEXT: s_brev_b32 s10, 1 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 @@ -5873,14 +5873,14 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: s_add_u32 s0, s4, s12 ; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_addc_u32 s1, s5, s13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, s9 @@ -5889,7 +5889,7 @@ ; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cselect_b32 s3, -1, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s16 ; GFX9-NEXT: v_mov_b32_e32 v3, s17 ; GFX9-NEXT: s_and_b32 s3, s3, 1 @@ -5903,7 +5903,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s4, 1, s6 @@ -5911,23 +5911,23 @@ ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], s[14:15], 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] ; GFX9-NEXT: s_and_b32 s4, 1, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX9-NEXT: s_ashr_i32 s7, s3, 31 ; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, s[4:5] ; GFX9-NEXT: s_add_u32 s4, s7, 0 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_and_b32 s5, s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s5, 0 ; GFX9-NEXT: s_addc_u32 s5, s7, 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: s_and_b32 s6, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s6, 0 ; GFX9-NEXT: s_addc_u32 s6, s7, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 @@ -5959,18 +5959,18 @@ ; GFX10-LABEL: s_saddsat_v2i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s8, s0, s8 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_and_b32 s16, s16, 1 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_addc_u32 s9, s1, s9 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] ; GFX10-NEXT: s_and_b32 s16, s16, 1 ; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], 0 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, s9 ; GFX10-NEXT: s_addc_u32 s16, s2, s10 -; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s17, s17, 1 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 @@ -5978,12 +5978,12 @@ ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3] ; GFX10-NEXT: v_mov_b32_e32 v3, s17 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s0, 1, s18 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_ashr_i32 s3, s17, 31 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_brev_b32 s10, 1 @@ -5992,39 +5992,39 @@ ; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, s0 ; GFX10-NEXT: s_add_u32 s0, s3, 0 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, s8 ; GFX10-NEXT: s_addc_u32 s1, s3, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s2, s2, 1 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, -1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_and_b32 s11, s11, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo ; GFX10-NEXT: s_add_u32 s0, s4, s12 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_mov_b32_e32 v2, s16 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo ; GFX10-NEXT: s_addc_u32 s1, s5, s13 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s3, s[14:15], 0 ; GFX10-NEXT: s_addc_u32 s8, s6, s14 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v6, s1 @@ -6033,25 +6033,25 @@ ; GFX10-NEXT: s_addc_u32 s9, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[6:7] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[6:7] -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, s9 ; GFX10-NEXT: s_and_b32 s2, 1, s2 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: s_ashr_i32 s5, s9, 31 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3 ; GFX10-NEXT: s_and_b32 s3, 1, s2 ; GFX10-NEXT: s_add_u32 s2, s5, 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 s3, 0, s3 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0, s3 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: s_addc_u32 s3, s5, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, s0 @@ -6059,7 +6059,7 @@ ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX10-NEXT: s_addc_u32 s4, s5, 0 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -210,12 +210,12 @@ ; CHECK-NEXT: s_ashr_i32 s6, s3, 31 ; CHECK-NEXT: s_ashr_i32 s8, s5, 31 ; CHECK-NEXT: s_add_u32 s0, s2, s6 -; CHECK-NEXT: s_cselect_b32 s1, 1, 0 +; CHECK-NEXT: s_cselect_b32 s1, -1, 0 ; CHECK-NEXT: s_and_b32 s1, s1, 1 ; CHECK-NEXT: s_cmp_lg_u32 s1, 0 ; CHECK-NEXT: s_addc_u32 s1, s3, s6 ; CHECK-NEXT: s_add_u32 s10, s4, s8 -; CHECK-NEXT: s_cselect_b32 s3, 1, 0 +; CHECK-NEXT: s_cselect_b32 s3, -1, 0 ; CHECK-NEXT: s_and_b32 s3, s3, 1 ; CHECK-NEXT: s_cmp_lg_u32 s3, 0 ; CHECK-NEXT: s_mov_b32 s9, s8 @@ -228,7 +228,7 @@ ; CHECK-NEXT: s_sub_u32 s3, 0, s10 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; CHECK-NEXT: s_cselect_b32 s0, 1, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 ; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -1210,7 +1210,7 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_movk_i32 s10, 0x1000 ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 @@ -1220,7 +1220,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s9 ; GISEL-NEXT: s_sub_u32 s11, 0, s8 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -1343,7 +1343,7 @@ ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 ; GISEL-NEXT: s_and_b32 s5, s5, 1 @@ -1362,7 +1362,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7 ; GISEL-NEXT: s_sub_u32 s8, 0, s6 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -1933,7 +1933,7 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 @@ -1943,7 +1943,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s9 ; GISEL-NEXT: s_sub_u32 s11, 0, s8 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -2066,7 +2066,7 @@ ; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 ; GISEL-NEXT: s_and_b32 s5, s5, 1 @@ -2085,7 +2085,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7 ; GISEL-NEXT: s_sub_u32 s8, 0, s6 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdivrem.ll @@ -150,12 +150,12 @@ ; GFX8-NEXT: s_ashr_i32 s12, s11, 31 ; GFX8-NEXT: s_ashr_i32 s2, s9, 31 ; GFX8-NEXT: s_add_u32 s0, s8, s2 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s9, s2 ; GFX8-NEXT: s_add_u32 s8, s10, s12 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: s_and_b32 s3, s3, 1 ; GFX8-NEXT: s_cmp_lg_u32 s3, 0 ; GFX8-NEXT: s_mov_b32 s13, s12 @@ -169,7 +169,7 @@ ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_sub_u32 s14, 0, s8 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -330,12 +330,12 @@ ; GFX9-NEXT: s_ashr_i32 s12, s11, 31 ; GFX9-NEXT: s_ashr_i32 s2, s9, 31 ; GFX9-NEXT: s_add_u32 s0, s8, s2 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s9, s2 ; GFX9-NEXT: s_add_u32 s8, s10, s12 -; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cselect_b32 s3, -1, 0 ; GFX9-NEXT: s_and_b32 s3, s3, 1 ; GFX9-NEXT: s_cmp_lg_u32 s3, 0 ; GFX9-NEXT: s_mov_b32 s13, s12 @@ -349,7 +349,7 @@ ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_sub_u32 s14, 0, s8 -; GFX9-NEXT: s_cselect_b32 s0, 1, 0 +; GFX9-NEXT: s_cselect_b32 s0, -1, 0 ; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -501,13 +501,13 @@ ; GFX10-NEXT: s_ashr_i32 s2, s9, 31 ; GFX10-NEXT: s_ashr_i32 s12, s11, 31 ; GFX10-NEXT: s_add_u32 s0, s8, s2 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_mov_b32 s13, s12 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s9, s2 ; GFX10-NEXT: s_add_u32 s8, s10, s12 -; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_cselect_b32 s3, -1, 0 ; GFX10-NEXT: s_and_b32 s3, s3, 1 ; GFX10-NEXT: s_cmp_lg_u32 s3, 0 ; GFX10-NEXT: s_mov_b32 s3, s2 @@ -517,7 +517,7 @@ ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX10-NEXT: s_sub_u32 s1, 0, s8 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 @@ -1347,12 +1347,12 @@ ; GFX8-NEXT: s_ashr_i32 s6, s9, 31 ; GFX8-NEXT: s_ashr_i32 s12, s1, 31 ; GFX8-NEXT: s_add_u32 s8, s8, s6 -; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, -1, 0 ; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_addc_u32 s9, s9, s6 ; GFX8-NEXT: s_add_u32 s0, s0, s12 -; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, -1, 0 ; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_mov_b32 s13, s12 @@ -1366,7 +1366,7 @@ ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX8-NEXT: s_sub_u32 s16, 0, s14 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: s_and_b32 s0, s0, 1 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX8-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -1509,12 +1509,12 @@ ; GFX8-NEXT: s_add_u32 s0, s10, s8 ; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1 ; GFX8-NEXT: v_mov_b32_e32 v4, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s11, s8 ; GFX8-NEXT: s_add_u32 s2, s2, s12 -; GFX8-NEXT: s_cselect_b32 s7, 1, 0 +; GFX8-NEXT: s_cselect_b32 s7, -1, 0 ; GFX8-NEXT: s_and_b32 s7, s7, 1 ; GFX8-NEXT: s_cmp_lg_u32 s7, 0 ; GFX8-NEXT: s_mov_b32 s13, s12 @@ -1539,7 +1539,7 @@ ; GFX8-NEXT: s_xor_b64 s[6:7], s[0:1], s[8:9] ; GFX8-NEXT: v_add_f32_e32 v2, v6, v2 ; GFX8-NEXT: s_sub_u32 s10, 0, s2 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: s_and_b32 s0, s0, 1 @@ -1699,12 +1699,12 @@ ; GFX9-NEXT: s_ashr_i32 s6, s9, 31 ; GFX9-NEXT: s_ashr_i32 s12, s1, 31 ; GFX9-NEXT: s_add_u32 s8, s8, s6 -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_addc_u32 s9, s9, s6 ; GFX9-NEXT: s_add_u32 s0, s0, s12 -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_mov_b32 s13, s12 @@ -1718,7 +1718,7 @@ ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: s_sub_u32 s16, 0, s14 -; GFX9-NEXT: s_cselect_b32 s0, 1, 0 +; GFX9-NEXT: s_cselect_b32 s0, -1, 0 ; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX9-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 @@ -1851,12 +1851,12 @@ ; GFX9-NEXT: s_xor_b64 s[0:1], s[6:7], s[12:13] ; GFX9-NEXT: s_ashr_i32 s12, s3, 31 ; GFX9-NEXT: s_add_u32 s10, s10, s8 -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_addc_u32 s11, s11, s8 ; GFX9-NEXT: s_add_u32 s2, s2, s12 -; GFX9-NEXT: s_cselect_b32 s7, 1, 0 +; GFX9-NEXT: s_cselect_b32 s7, -1, 0 ; GFX9-NEXT: s_and_b32 s7, s7, 1 ; GFX9-NEXT: s_cmp_lg_u32 s7, 0 ; GFX9-NEXT: s_mov_b32 s13, s12 @@ -1877,7 +1877,7 @@ ; GFX9-NEXT: v_trunc_f32_e32 v6, v6 ; GFX9-NEXT: v_mul_f32_e32 v7, 0xcf800000, v6 ; GFX9-NEXT: v_add_f32_e32 v4, v7, v4 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v4, v4 ; GFX9-NEXT: v_cvt_u32_f32_e32 v6, v6 ; GFX9-NEXT: s_and_b32 s1, s1, 1 @@ -2036,13 +2036,13 @@ ; GFX10-NEXT: s_ashr_i32 s12, s9, 31 ; GFX10-NEXT: s_ashr_i32 s6, s1, 31 ; GFX10-NEXT: s_add_u32 s14, s8, s12 -; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_cselect_b32 s7, -1, 0 ; GFX10-NEXT: s_mov_b32 s13, s12 ; GFX10-NEXT: s_and_b32 s7, s7, 1 ; GFX10-NEXT: s_cmp_lg_u32 s7, 0 ; GFX10-NEXT: s_addc_u32 s15, s9, s12 ; GFX10-NEXT: s_add_u32 s0, s0, s6 -; GFX10-NEXT: s_cselect_b32 s7, 1, 0 +; GFX10-NEXT: s_cselect_b32 s7, -1, 0 ; GFX10-NEXT: s_and_b32 s8, s7, 1 ; GFX10-NEXT: s_mov_b32 s7, s6 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 @@ -2051,7 +2051,7 @@ ; GFX10-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7] ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s9 ; GFX10-NEXT: s_sub_u32 s22, 0, s8 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 @@ -2062,7 +2062,7 @@ ; GFX10-NEXT: s_ashr_i32 s18, s3, 31 ; GFX10-NEXT: s_xor_b64 s[20:21], s[12:13], s[6:7] ; GFX10-NEXT: s_add_u32 s0, s10, s16 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: s_mov_b32 s19, s18 @@ -2070,7 +2070,7 @@ ; GFX10-NEXT: s_mov_b32 s17, s16 ; GFX10-NEXT: s_addc_u32 s1, s11, s16 ; GFX10-NEXT: s_add_u32 s2, s2, s18 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 @@ -2081,7 +2081,7 @@ ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s3 ; GFX10-NEXT: v_cvt_f32_u32_e32 v3, s2 ; GFX10-NEXT: s_sub_u32 s6, 0, s2 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_trunc_f32_e32 v2, v2 ; GFX10-NEXT: v_mul_f32_e32 v1, 0x4f800000, v1 ; GFX10-NEXT: s_and_b32 s0, s0, 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -206,12 +206,12 @@ ; CHECK-NEXT: s_ashr_i32 s0, s5, 31 ; CHECK-NEXT: s_ashr_i32 s6, s3, 31 ; CHECK-NEXT: s_add_u32 s8, s2, s6 -; CHECK-NEXT: s_cselect_b32 s7, 1, 0 +; CHECK-NEXT: s_cselect_b32 s7, -1, 0 ; CHECK-NEXT: s_and_b32 s7, s7, 1 ; CHECK-NEXT: s_cmp_lg_u32 s7, 0 ; CHECK-NEXT: s_addc_u32 s9, s3, s6 ; CHECK-NEXT: s_add_u32 s10, s4, s0 -; CHECK-NEXT: s_cselect_b32 s3, 1, 0 +; CHECK-NEXT: s_cselect_b32 s3, -1, 0 ; CHECK-NEXT: s_and_b32 s3, s3, 1 ; CHECK-NEXT: s_cmp_lg_u32 s3, 0 ; CHECK-NEXT: s_mov_b32 s1, s0 @@ -224,7 +224,7 @@ ; CHECK-NEXT: s_sub_u32 s3, 0, s10 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v0, v0 -; CHECK-NEXT: s_cselect_b32 s0, 1, 0 +; CHECK-NEXT: s_cselect_b32 s0, -1, 0 ; CHECK-NEXT: s_and_b32 s0, s0, 1 ; CHECK-NEXT: s_cmp_lg_u32 s0, 0 ; CHECK-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -1188,7 +1188,7 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_movk_i32 s10, 0x1000 ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 @@ -1198,7 +1198,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s9 ; GISEL-NEXT: s_sub_u32 s11, 0, s8 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -1323,7 +1323,7 @@ ; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5] ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s8, v7 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 @@ -1338,7 +1338,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7 ; GISEL-NEXT: s_sub_u32 s8, 0, s6 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -1903,7 +1903,7 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_mov_b32 s10, 0x12d8fb ; GISEL-NEXT: s_add_u32 s4, s10, 0 -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 ; GISEL-NEXT: s_mov_b32 s6, 0 @@ -1913,7 +1913,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s8 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s9 ; GISEL-NEXT: s_sub_u32 s11, 0, s8 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 @@ -2038,7 +2038,7 @@ ; GISEL-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[4:5] ; GISEL-NEXT: s_add_u32 s4, s10, 0 ; GISEL-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc -; GISEL-NEXT: s_cselect_b32 s5, 1, 0 +; GISEL-NEXT: s_cselect_b32 s5, -1, 0 ; GISEL-NEXT: v_subrev_i32_e32 v9, vcc, s8, v7 ; GISEL-NEXT: s_and_b32 s5, s5, 1 ; GISEL-NEXT: s_cmp_lg_u32 s5, 0 @@ -2053,7 +2053,7 @@ ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s6 ; GISEL-NEXT: v_cvt_f32_u32_e32 v5, s7 ; GISEL-NEXT: s_sub_u32 s8, 0, s6 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: s_and_b32 s4, s4, 1 ; GISEL-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll @@ -1003,10 +1003,10 @@ ; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000 ; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000 ; GFX8-NEXT: s_cmp_lt_i32 s3, s0 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000 ; GFX8-NEXT: s_cmp_gt_i32 s1, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_xor_b32 s0, s1, s0 ; GFX8-NEXT: s_ashr_i32 s1, s3, 23 ; GFX8-NEXT: s_add_i32 s1, s1, 0xff800000 @@ -4195,7 +4195,7 @@ ; GFX6-LABEL: s_ssubsat_i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s4, s0, s2 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_and_b32 s5, s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s5, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 @@ -4206,7 +4206,7 @@ ; GFX6-NEXT: s_ashr_i32 s2, s5, 31 ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX6-NEXT: s_add_u32 s0, s2, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4223,7 +4223,7 @@ ; GFX8-LABEL: s_ssubsat_i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s4, s0, s2 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_and_b32 s5, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -4234,7 +4234,7 @@ ; GFX8-NEXT: s_ashr_i32 s2, s5, 31 ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX8-NEXT: s_add_u32 s0, s2, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4251,7 +4251,7 @@ ; GFX9-LABEL: s_ssubsat_i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s4, s0, s2 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_and_b32 s5, s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s5, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 @@ -4262,7 +4262,7 @@ ; GFX9-NEXT: s_ashr_i32 s2, s5, 31 ; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX9-NEXT: s_add_u32 s0, s2, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s2, 0x80000000 @@ -4279,7 +4279,7 @@ ; GFX10-LABEL: s_ssubsat_i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s4, s0, s2 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_and_b32 s5, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 @@ -4290,7 +4290,7 @@ ; GFX10-NEXT: v_mov_b32_e32 v1, s5 ; GFX10-NEXT: s_xor_b32 s3, s1, s0 ; GFX10-NEXT: s_add_u32 s0, s2, 0 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s3 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 @@ -4549,7 +4549,7 @@ ; GFX6-LABEL: s_ssubsat_v2i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s8, s0, s4 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s0 @@ -4560,7 +4560,7 @@ ; GFX6-NEXT: s_ashr_i32 s4, s9, 31 ; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX6-NEXT: s_add_u32 s0, s4, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_brev_b32 s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 @@ -4568,7 +4568,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: s_sub_u32 s0, s2, s6 ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: v_mov_b32_e32 v0, s8 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 @@ -4584,7 +4584,7 @@ ; GFX6-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX6-NEXT: v_mov_b32_e32 v0, s0 ; GFX6-NEXT: s_add_u32 s0, s4, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s3, s4, s5 @@ -4602,7 +4602,7 @@ ; GFX8-LABEL: s_ssubsat_v2i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s8, s0, s4 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0 @@ -4613,7 +4613,7 @@ ; GFX8-NEXT: s_ashr_i32 s4, s9, 31 ; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX8-NEXT: s_add_u32 s0, s4, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_brev_b32 s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 @@ -4621,7 +4621,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: s_sub_u32 s0, s2, s6 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: v_mov_b32_e32 v0, s8 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 @@ -4637,7 +4637,7 @@ ; GFX8-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: s_add_u32 s0, s4, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s3, s4, s5 @@ -4655,7 +4655,7 @@ ; GFX9-LABEL: s_ssubsat_v2i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s8, s0, s4 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0 @@ -4666,7 +4666,7 @@ ; GFX9-NEXT: s_ashr_i32 s4, s9, 31 ; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc ; GFX9-NEXT: s_add_u32 s0, s4, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_brev_b32 s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 @@ -4674,7 +4674,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: s_sub_u32 s0, s2, s6 ; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 @@ -4690,7 +4690,7 @@ ; GFX9-NEXT: s_xor_b64 vcc, s[2:3], vcc ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: s_add_u32 s0, s4, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s3, s4, s5 @@ -4708,7 +4708,7 @@ ; GFX10-LABEL: s_ssubsat_v2i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s8, s0, s4 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v0, s8 @@ -4720,13 +4720,13 @@ ; GFX10-NEXT: v_mov_b32_e32 v1, s9 ; GFX10-NEXT: s_xor_b32 s8, s4, s0 ; GFX10-NEXT: s_add_u32 s0, s1, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s10 ; GFX10-NEXT: s_sub_u32 s4, s2, s6 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8 ; GFX10-NEXT: s_and_b32 s5, s5, 1 ; GFX10-NEXT: v_mov_b32_e32 v2, s4 @@ -4738,7 +4738,7 @@ ; GFX10-NEXT: v_mov_b32_e32 v3, s5 ; GFX10-NEXT: s_xor_b32 s2, s3, s2 ; GFX10-NEXT: s_add_u32 s0, s1, 0 -; GFX10-NEXT: s_cselect_b32 s3, 1, 0 +; GFX10-NEXT: s_cselect_b32 s3, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2 ; GFX10-NEXT: s_and_b32 s3, s3, 1 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 @@ -4757,15 +4757,15 @@ ; GFX6-LABEL: s_ssubsat_i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s8, s0, s4 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 ; GFX6-NEXT: s_subb_u32 s9, s1, s5 -; GFX6-NEXT: s_cselect_b32 s10, 1, 0 +; GFX6-NEXT: s_cselect_b32 s10, -1, 0 ; GFX6-NEXT: s_and_b32 s10, s10, 1 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 ; GFX6-NEXT: s_subb_u32 s10, s2, s6 -; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s11, s11, 1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0 @@ -4785,16 +4785,16 @@ ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX6-NEXT: s_add_u32 s0, s3, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s3, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0 ; GFX6-NEXT: s_addc_u32 s2, s3, 0 -; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cselect_b32 s4, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s4, s4, 1 @@ -4823,15 +4823,15 @@ ; GFX8-LABEL: s_ssubsat_i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s8, s0, s4 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_subb_u32 s9, s1, s5 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: s_and_b32 s10, s10, 1 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_subb_u32 s10, s2, s6 -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: s_and_b32 s11, s11, 1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 @@ -4841,7 +4841,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 @@ -4851,22 +4851,22 @@ ; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: s_ashr_i32 s3, s11, 31 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: s_add_u32 s0, s3, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s3, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s2, s3, 0 -; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s4, s4, 1 @@ -4895,15 +4895,15 @@ ; GFX9-LABEL: s_ssubsat_i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s8, s0, s4 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_subb_u32 s9, s1, s5 -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: s_and_b32 s10, s10, 1 ; GFX9-NEXT: s_cmp_lg_u32 s10, 0 ; GFX9-NEXT: s_subb_u32 s10, s2, s6 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_and_b32 s11, s11, 1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 @@ -4913,7 +4913,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 @@ -4923,22 +4923,22 @@ ; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: s_ashr_i32 s3, s11, 31 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_add_u32 s0, s3, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s3, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s2, s3, 0 -; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s4, s4, 1 @@ -4967,16 +4967,16 @@ ; GFX10-LABEL: s_ssubsat_i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s8, s0, s4 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_subb_u32 s9, s1, s5 -; GFX10-NEXT: s_cselect_b32 s10, 1, 0 +; GFX10-NEXT: s_cselect_b32 s10, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1] ; GFX10-NEXT: s_and_b32 s10, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_subb_u32 s10, s2, s6 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s11, s11, 1 ; GFX10-NEXT: v_mov_b32_e32 v3, s10 @@ -4984,14 +4984,14 @@ ; GFX10-NEXT: s_subb_u32 s11, s3, s7 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3] ; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], s[2:3] -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v4, s11 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[4:5], 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_ashr_i32 s3, s11, 31 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 @@ -5000,20 +5000,20 @@ ; GFX10-NEXT: s_and_b32 s0, 1, s1 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: s_add_u32 s0, s3, 0 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, s9 ; GFX10-NEXT: s_addc_u32 s1, s3, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_and_b32 s2, s2, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, s8 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 @@ -5229,7 +5229,7 @@ ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0 @@ -5268,7 +5268,7 @@ ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3] -; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0 @@ -5298,7 +5298,7 @@ ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo ; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1] ; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0 @@ -5586,15 +5586,15 @@ ; GFX6-LABEL: s_ssubsat_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s16, s0, s8 -; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 ; GFX6-NEXT: s_and_b32 s17, s17, 1 ; GFX6-NEXT: s_cmp_lg_u32 s17, 0 ; GFX6-NEXT: s_subb_u32 s17, s1, s9 -; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 ; GFX6-NEXT: s_and_b32 s18, s18, 1 ; GFX6-NEXT: s_cmp_lg_u32 s18, 0 ; GFX6-NEXT: s_subb_u32 s18, s2, s10 -; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v3, s1 ; GFX6-NEXT: s_and_b32 s19, s19, 1 ; GFX6-NEXT: v_mov_b32_e32 v2, s0 @@ -5614,15 +5614,15 @@ ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX6-NEXT: s_add_u32 s0, s3, 0 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: s_addc_u32 s1, s3, 0 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s2, s3, 0 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0 ; GFX6-NEXT: s_brev_b32 s8, 1 @@ -5633,14 +5633,14 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s0 ; GFX6-NEXT: s_sub_u32 s0, s4, s12 ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_subb_u32 s1, s5, s13 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_mov_b32_e32 v0, s2 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: v_mov_b32_e32 v4, s17 @@ -5651,7 +5651,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s3 ; GFX6-NEXT: v_mov_b32_e32 v3, s19 ; GFX6-NEXT: s_subb_u32 s2, s6, s14 -; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cselect_b32 s3, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc ; GFX6-NEXT: v_mov_b32_e32 v2, s4 @@ -5673,16 +5673,16 @@ ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX6-NEXT: s_add_u32 s4, s7, 0 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_and_b32 s5, s5, 1 ; GFX6-NEXT: s_cmp_lg_u32 s5, 0 ; GFX6-NEXT: s_addc_u32 s5, s7, 0 -; GFX6-NEXT: s_cselect_b32 s6, 1, 0 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 ; GFX6-NEXT: s_and_b32 s6, s6, 1 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 ; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0 ; GFX6-NEXT: s_addc_u32 s6, s7, 0 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 @@ -5715,15 +5715,15 @@ ; GFX8-LABEL: s_ssubsat_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s16, s0, s8 -; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_and_b32 s17, s17, 1 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_subb_u32 s17, s1, s9 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: s_cmp_lg_u32 s18, 0 ; GFX8-NEXT: s_subb_u32 s18, s2, s10 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_and_b32 s19, s19, 1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: s_cmp_lg_u32 s19, 0 @@ -5733,7 +5733,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 @@ -5743,22 +5743,22 @@ ; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s2 ; GFX8-NEXT: s_ashr_i32 s3, s19, 31 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: s_add_u32 s0, s3, 0 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_addc_u32 s1, s3, 0 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s2, s3, 0 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_brev_b32 s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 @@ -5768,14 +5768,14 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s0 ; GFX8-NEXT: s_sub_u32 s0, s4, s12 ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_subb_u32 s1, s5, s13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: v_mov_b32_e32 v4, s17 @@ -5784,7 +5784,7 @@ ; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: v_mov_b32_e32 v2, s18 ; GFX8-NEXT: v_mov_b32_e32 v3, s19 ; GFX8-NEXT: s_and_b32 s3, s3, 1 @@ -5798,7 +5798,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s4, 1, s6 @@ -5808,22 +5808,22 @@ ; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX8-NEXT: s_and_b32 s4, 1, s6 ; GFX8-NEXT: s_ashr_i32 s7, s3, 31 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: s_add_u32 s4, s7, 0 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_and_b32 s5, s5, 1 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 ; GFX8-NEXT: s_addc_u32 s5, s7, 0 -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: s_and_b32 s6, s6, 1 ; GFX8-NEXT: s_cmp_lg_u32 s6, 0 ; GFX8-NEXT: s_addc_u32 s6, s7, 0 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 @@ -5856,15 +5856,15 @@ ; GFX9-LABEL: s_ssubsat_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s16, s0, s8 -; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_and_b32 s17, s17, 1 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_subb_u32 s17, s1, s9 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_and_b32 s18, s18, 1 ; GFX9-NEXT: s_cmp_lg_u32 s18, 0 ; GFX9-NEXT: s_subb_u32 s18, s2, s10 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_and_b32 s19, s19, 1 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 ; GFX9-NEXT: s_cmp_lg_u32 s19, 0 @@ -5874,7 +5874,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v1, s3 ; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 @@ -5884,22 +5884,22 @@ ; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s2 ; GFX9-NEXT: s_ashr_i32 s3, s19, 31 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_add_u32 s0, s3, 0 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s3, 0 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s2, s3, 0 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_brev_b32 s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 @@ -5909,14 +5909,14 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: s_sub_u32 s0, s4, s12 ; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_subb_u32 s1, s5, s13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, s17 @@ -5925,7 +5925,7 @@ ; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cselect_b32 s3, -1, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, s18 ; GFX9-NEXT: v_mov_b32_e32 v3, s19 ; GFX9-NEXT: s_and_b32 s3, s3, 1 @@ -5939,7 +5939,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s4, 1, s6 @@ -5949,22 +5949,22 @@ ; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] ; GFX9-NEXT: s_and_b32 s4, 1, s6 ; GFX9-NEXT: s_ashr_i32 s7, s3, 31 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: s_add_u32 s4, s7, 0 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_and_b32 s5, s5, 1 ; GFX9-NEXT: s_cmp_lg_u32 s5, 0 ; GFX9-NEXT: s_addc_u32 s5, s7, 0 -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: s_and_b32 s6, s6, 1 ; GFX9-NEXT: s_cmp_lg_u32 s6, 0 ; GFX9-NEXT: s_addc_u32 s6, s7, 0 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc ; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 @@ -5997,17 +5997,17 @@ ; GFX10-LABEL: s_ssubsat_v2i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s16, s0, s8 -; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: s_and_b32 s17, s17, 1 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_subb_u32 s17, s1, s9 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1] ; GFX10-NEXT: s_and_b32 s18, s18, 1 ; GFX10-NEXT: v_cmp_gt_u64_e64 s1, s[8:9], 0 ; GFX10-NEXT: s_cmp_lg_u32 s18, 0 ; GFX10-NEXT: s_subb_u32 s18, s2, s10 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s19, s19, 1 ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 @@ -6015,12 +6015,12 @@ ; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3] ; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3] ; GFX10-NEXT: v_mov_b32_e32 v3, s19 -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_ashr_i32 s3, s19, 31 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo @@ -6030,41 +6030,41 @@ ; GFX10-NEXT: s_add_u32 s0, s3, 0 ; GFX10-NEXT: s_brev_b32 s10, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, s17 ; GFX10-NEXT: s_addc_u32 s1, s3, 0 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0 ; GFX10-NEXT: s_and_b32 s2, s2, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, s16 ; GFX10-NEXT: s_cmp_lg_u32 s2, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_addc_u32 s2, s3, 0 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, s10 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo ; GFX10-NEXT: s_sub_u32 s0, s4, s12 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_mov_b32_e32 v2, s18 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo ; GFX10-NEXT: s_subb_u32 s1, s5, s13 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: v_cmp_gt_u64_e64 s3, s[12:13], 0 ; GFX10-NEXT: s_subb_u32 s8, s6, s14 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_mov_b32_e32 v7, s8 @@ -6072,13 +6072,13 @@ ; GFX10-NEXT: s_subb_u32 s9, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[6:7] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[6:7] -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: v_mov_b32_e32 v8, s9 ; GFX10-NEXT: s_and_b32 s2, 1, s2 ; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2 ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4 -; GFX10-NEXT: s_cselect_b32 s2, 1, 0 +; GFX10-NEXT: s_cselect_b32 s2, -1, 0 ; GFX10-NEXT: s_ashr_i32 s5, s9, 31 ; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3 @@ -6087,13 +6087,13 @@ ; GFX10-NEXT: s_and_b32 s3, 1, s2 ; GFX10-NEXT: s_add_u32 s2, s5, 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: v_mov_b32_e32 v6, s1 ; GFX10-NEXT: s_addc_u32 s3, s5, 0 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: v_mov_b32_e32 v5, s0 @@ -6101,7 +6101,7 @@ ; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_and_b32_e32 v4, 1, v4 ; GFX10-NEXT: s_addc_u32 s4, s5, 0 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_and_b32 s6, s6, 1 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll @@ -2607,7 +2607,7 @@ ; GFX6-LABEL: s_uaddsat_i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s0, s0, s2 -; GFX6-NEXT: s_cselect_b32 s4, 1, 0 +; GFX6-NEXT: s_cselect_b32 s4, -1, 0 ; GFX6-NEXT: s_and_b32 s4, s4, 1 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s2 @@ -2625,7 +2625,7 @@ ; GFX8-LABEL: s_uaddsat_i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s0, s0, s2 -; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: s_and_b32 s4, s4, 1 ; GFX8-NEXT: s_cmp_lg_u32 s4, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 @@ -2643,7 +2643,7 @@ ; GFX9-LABEL: s_uaddsat_i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: s_and_b32 s4, s4, 1 ; GFX9-NEXT: s_cmp_lg_u32 s4, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2 @@ -2661,7 +2661,7 @@ ; GFX10-LABEL: s_uaddsat_i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s0, s0, s2 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s3 @@ -2832,7 +2832,7 @@ ; GFX6-LABEL: s_uaddsat_v2i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s0, s0, s4 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s4 @@ -2842,7 +2842,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v2, s0 ; GFX6-NEXT: s_add_u32 s0, s2, s6 ; GFX6-NEXT: v_mov_b32_e32 v3, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s6 @@ -2864,7 +2864,7 @@ ; GFX8-LABEL: s_uaddsat_v2i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s0, s0, s4 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 @@ -2874,7 +2874,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: s_add_u32 s0, s2, s6 ; GFX8-NEXT: v_mov_b32_e32 v3, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 @@ -2896,7 +2896,7 @@ ; GFX9-LABEL: s_uaddsat_v2i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s0, s0, s4 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 @@ -2906,7 +2906,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-NEXT: s_add_u32 s0, s2, s6 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 @@ -2928,12 +2928,12 @@ ; GFX10-LABEL: s_uaddsat_v2i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s0, s0, s4 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s6 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 @@ -2956,15 +2956,15 @@ ; GFX6-LABEL: s_uaddsat_i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s0, s0, s4 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: s_addc_u32 s1, s1, s5 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: s_cmp_lg_u32 s8, 0 ; GFX6-NEXT: s_addc_u32 s2, s2, s6 -; GFX6-NEXT: s_cselect_b32 s8, 1, 0 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: s_and_b32 s8, s8, 1 ; GFX6-NEXT: v_mov_b32_e32 v3, s5 @@ -2997,15 +2997,15 @@ ; GFX8-LABEL: s_uaddsat_i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s0, s0, s4 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_addc_u32 s1, s1, s5 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 ; GFX8-NEXT: s_addc_u32 s2, s2, s6 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: s_and_b32 s8, s8, 1 ; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: s_cmp_lg_u32 s8, 0 @@ -3015,7 +3015,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s4, 1, s6 @@ -3041,15 +3041,15 @@ ; GFX9-LABEL: s_uaddsat_i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s0, s0, s4 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, s5 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 ; GFX9-NEXT: s_addc_u32 s2, s2, s6 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: s_and_b32 s8, s8, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: s_cmp_lg_u32 s8, 0 @@ -3059,7 +3059,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s4, 1, s6 @@ -3085,23 +3085,23 @@ ; GFX10-LABEL: s_uaddsat_i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s0, s0, s4 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s5 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5] ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s2, s2, s6 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, s7 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] ; GFX10-NEXT: v_cmp_lt_u64_e64 s5, s[2:3], s[6:7] -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: s_and_b32 s4, 1, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s5 @@ -3466,15 +3466,15 @@ ; GFX6-LABEL: s_uaddsat_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_add_u32 s0, s0, s8 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_and_b32 s16, s16, 1 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_addc_u32 s1, s1, s9 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: s_and_b32 s16, s16, 1 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_addc_u32 s2, s2, s10 -; GFX6-NEXT: s_cselect_b32 s16, 1, 0 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v2, s8 ; GFX6-NEXT: s_and_b32 s16, s16, 1 ; GFX6-NEXT: v_mov_b32_e32 v3, s9 @@ -3491,20 +3491,20 @@ ; GFX6-NEXT: s_add_u32 s0, s4, s12 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_addc_u32 s1, s5, s13 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_mov_b32_e32 v0, s2 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s2, s6, s14 ; GFX6-NEXT: v_cndmask_b32_e64 v4, v1, -1, vcc ; GFX6-NEXT: v_mov_b32_e32 v1, s3 -; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cselect_b32 s3, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e64 v5, v2, -1, vcc ; GFX6-NEXT: v_mov_b32_e32 v2, s12 ; GFX6-NEXT: s_and_b32 s3, s3, 1 @@ -3544,15 +3544,15 @@ ; GFX8-LABEL: s_uaddsat_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_add_u32 s0, s0, s8 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_and_b32 s16, s16, 1 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_addc_u32 s1, s1, s9 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_and_b32 s16, s16, 1 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 ; GFX8-NEXT: s_addc_u32 s2, s2, s10 -; GFX8-NEXT: s_cselect_b32 s16, 1, 0 +; GFX8-NEXT: s_cselect_b32 s16, -1, 0 ; GFX8-NEXT: s_and_b32 s16, s16, 1 ; GFX8-NEXT: v_mov_b32_e32 v2, s8 ; GFX8-NEXT: s_cmp_lg_u32 s16, 0 @@ -3562,7 +3562,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s8, 1, s10 @@ -3572,20 +3572,20 @@ ; GFX8-NEXT: s_add_u32 s0, s4, s12 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_mov_b32_e32 v2, s1 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_addc_u32 s1, s5, s13 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_addc_u32 s2, s6, s14 ; GFX8-NEXT: v_cndmask_b32_e64 v4, v1, -1, vcc ; GFX8-NEXT: v_mov_b32_e32 v1, s3 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: s_and_b32 s3, s3, 1 ; GFX8-NEXT: v_cndmask_b32_e64 v5, v2, -1, vcc ; GFX8-NEXT: v_mov_b32_e32 v2, s12 @@ -3598,7 +3598,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s14 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[14:15] ; GFX8-NEXT: v_mov_b32_e32 v1, s15 -; GFX8-NEXT: s_cselect_b32 s4, 1, 0 +; GFX8-NEXT: s_cselect_b32 s4, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s4, 1, s4 @@ -3628,15 +3628,15 @@ ; GFX9-LABEL: s_uaddsat_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_add_u32 s0, s0, s8 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_and_b32 s16, s16, 1 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, s9 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_and_b32 s16, s16, 1 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 ; GFX9-NEXT: s_addc_u32 s2, s2, s10 -; GFX9-NEXT: s_cselect_b32 s16, 1, 0 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 ; GFX9-NEXT: s_and_b32 s16, s16, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, s8 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 @@ -3646,7 +3646,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s10 ; GFX9-NEXT: v_mov_b32_e32 v1, s11 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s8, 1, s10 @@ -3656,20 +3656,20 @@ ; GFX9-NEXT: s_add_u32 s0, s4, s12 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_addc_u32 s1, s5, s13 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, s2 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: s_addc_u32 s2, s6, s14 ; GFX9-NEXT: v_cndmask_b32_e64 v4, v1, -1, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, s3 -; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cselect_b32 s3, -1, 0 ; GFX9-NEXT: s_and_b32 s3, s3, 1 ; GFX9-NEXT: v_cndmask_b32_e64 v5, v2, -1, vcc ; GFX9-NEXT: v_mov_b32_e32 v2, s12 @@ -3682,7 +3682,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s14 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[14:15] ; GFX9-NEXT: v_mov_b32_e32 v1, s15 -; GFX9-NEXT: s_cselect_b32 s4, 1, 0 +; GFX9-NEXT: s_cselect_b32 s4, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s4, 1, s4 @@ -3712,38 +3712,38 @@ ; GFX10-LABEL: s_uaddsat_v2i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_add_u32 s0, s0, s8 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_and_b32 s16, s16, 1 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, s9 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s8, s[0:1], s[8:9] ; GFX10-NEXT: s_and_b32 s16, s16, 1 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_addc_u32 s2, s2, s10 -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s8 ; GFX10-NEXT: s_and_b32 s16, s16, 1 ; GFX10-NEXT: s_cmp_lg_u32 s16, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, s11 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] ; GFX10-NEXT: v_cmp_lt_u64_e64 s10, s[2:3], s[10:11] -; GFX10-NEXT: s_cselect_b32 s16, 1, 0 +; GFX10-NEXT: s_cselect_b32 s16, -1, 0 ; GFX10-NEXT: s_and_b32 s8, 1, s16 ; GFX10-NEXT: s_add_u32 s4, s4, s12 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s10 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_addc_u32 s5, s5, s13 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s9, s[4:5], s[12:13] ; GFX10-NEXT: s_addc_u32 s6, s6, s14 -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s8, s8, 1 ; GFX10-NEXT: s_cmp_lg_u32 s8, 0 @@ -3751,7 +3751,7 @@ ; GFX10-NEXT: s_addc_u32 s7, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], s[14:15] ; GFX10-NEXT: v_cmp_lt_u64_e64 s9, s[6:7], s[14:15] -; GFX10-NEXT: s_cselect_b32 s8, 1, 0 +; GFX10-NEXT: s_cselect_b32 s8, -1, 0 ; GFX10-NEXT: s_and_b32 s8, 1, s8 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s8 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s9 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll @@ -196,7 +196,7 @@ ; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: s_sub_u32 s6, 0, s2 -; CHECK-NEXT: s_cselect_b32 s4, 1, 0 +; CHECK-NEXT: s_cselect_b32 s4, -1, 0 ; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: s_and_b32 s4, s4, 1 @@ -1108,7 +1108,7 @@ ; GISEL-NEXT: s_movk_i32 s12, 0x1000 ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 ; GISEL-NEXT: s_sub_u32 s8, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 ; GISEL-NEXT: s_and_b32 s4, s4, 1 @@ -1124,7 +1124,7 @@ ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GISEL-NEXT: s_sub_u32 s13, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: s_and_b32 s4, s4, 1 @@ -1769,7 +1769,7 @@ ; GISEL-NEXT: s_mov_b32 s12, 0x12d8fb ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 ; GISEL-NEXT: s_sub_u32 s8, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 ; GISEL-NEXT: s_and_b32 s4, s4, 1 @@ -1785,7 +1785,7 @@ ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GISEL-NEXT: s_sub_u32 s13, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: s_and_b32 s4, s4, 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udivrem.ll @@ -117,7 +117,7 @@ ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX8-NEXT: s_sub_u32 s2, 0, s10 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 @@ -270,7 +270,7 @@ ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX9-NEXT: s_sub_u32 s2, 0, s10 -; GFX9-NEXT: s_cselect_b32 s0, 1, 0 +; GFX9-NEXT: s_cselect_b32 s0, -1, 0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 @@ -414,7 +414,7 @@ ; GFX10-NEXT: v_cvt_f32_u32_e32 v0, s11 ; GFX10-NEXT: v_cvt_f32_u32_e32 v1, s10 ; GFX10-NEXT: s_sub_u32 s1, 0, s10 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 @@ -1039,7 +1039,7 @@ ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX8-NEXT: s_sub_u32 s2, 0, s8 -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX8-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0 @@ -1188,7 +1188,7 @@ ; GFX8-NEXT: v_mul_f32_e32 v6, 0xcf800000, v3 ; GFX8-NEXT: v_add_f32_e32 v2, v6, v2 ; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v10, s[0:1] -; GFX8-NEXT: s_cselect_b32 s0, 1, 0 +; GFX8-NEXT: s_cselect_b32 s0, -1, 0 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3 ; GFX8-NEXT: s_and_b32 s0, s0, 1 @@ -1335,7 +1335,7 @@ ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s9 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s8 ; GFX9-NEXT: s_sub_u32 s2, 0, s8 -; GFX9-NEXT: s_cselect_b32 s0, 1, 0 +; GFX9-NEXT: s_cselect_b32 s0, -1, 0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX9-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 @@ -1470,7 +1470,7 @@ ; GFX9-NEXT: v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1] ; GFX9-NEXT: v_add_f32_e32 v5, v12, v5 ; GFX9-NEXT: s_sub_u32 s8, 0, s10 -; GFX9-NEXT: s_cselect_b32 s0, 1, 0 +; GFX9-NEXT: s_cselect_b32 s0, -1, 0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v5 ; GFX9-NEXT: v_cvt_u32_f32_e32 v11, v11 ; GFX9-NEXT: s_and_b32 s0, s0, 1 @@ -1623,7 +1623,7 @@ ; GFX10-NEXT: s_sub_u32 s2, 0, s8 ; GFX10-NEXT: v_mul_f32_e32 v0, 0x4f800000, v0 ; GFX10-NEXT: v_mul_f32_e32 v2, 0x4f800000, v2 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: v_add_f32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_f32_e32 v1, v2, v3 @@ -1632,7 +1632,7 @@ ; GFX10-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX10-NEXT: v_rcp_iflag_f32_e32 v1, v1 ; GFX10-NEXT: s_sub_u32 s3, 0, s10 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_subb_u32 s6, 0, s11 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll @@ -193,7 +193,7 @@ ; CHECK-NEXT: v_mov_b32_e32 v1, s3 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s3 ; CHECK-NEXT: s_sub_u32 s6, 0, s2 -; CHECK-NEXT: s_cselect_b32 s4, 1, 0 +; CHECK-NEXT: s_cselect_b32 s4, -1, 0 ; CHECK-NEXT: v_mov_b32_e32 v3, s1 ; CHECK-NEXT: v_mac_f32_e32 v0, 0x4f800000, v2 ; CHECK-NEXT: s_and_b32 s4, s4, 1 @@ -968,12 +968,12 @@ ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_movk_i32 s4, 0x1000 ; GISEL-NEXT: s_add_u32 s5, s4, -1 -; GISEL-NEXT: s_cselect_b32 s6, 1, 0 +; GISEL-NEXT: s_cselect_b32 s6, -1, 0 ; GISEL-NEXT: s_and_b32 s6, s6, 1 ; GISEL-NEXT: s_cmp_lg_u32 s6, 0 ; GISEL-NEXT: s_addc_u32 s6, 0, -1 ; GISEL-NEXT: s_add_u32 s4, s4, -1 -; GISEL-NEXT: s_cselect_b32 s7, 1, 0 +; GISEL-NEXT: s_cselect_b32 s7, -1, 0 ; GISEL-NEXT: v_and_b32_e32 v0, s5, v0 ; GISEL-NEXT: s_and_b32 s5, s7, 1 ; GISEL-NEXT: v_and_b32_e32 v1, s6, v1 @@ -1137,7 +1137,7 @@ ; GISEL-NEXT: s_mov_b32 s12, 0x12d8fb ; GISEL-NEXT: v_cvt_f32_u32_e32 v4, s12 ; GISEL-NEXT: s_sub_u32 s8, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0 ; GISEL-NEXT: v_mov_b32_e32 v6, v4 ; GISEL-NEXT: s_and_b32 s4, s4, 1 @@ -1153,7 +1153,7 @@ ; GISEL-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; GISEL-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; GISEL-NEXT: s_sub_u32 s13, 0, s12 -; GISEL-NEXT: s_cselect_b32 s4, 1, 0 +; GISEL-NEXT: s_cselect_b32 s4, -1, 0 ; GISEL-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; GISEL-NEXT: v_trunc_f32_e32 v6, v6 ; GISEL-NEXT: s_and_b32 s4, s4, 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll @@ -2477,7 +2477,7 @@ ; GFX6-LABEL: s_usubsat_i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s4, s0, s2 -; GFX6-NEXT: s_cselect_b32 s5, 1, 0 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 ; GFX6-NEXT: s_and_b32 s5, s5, 1 ; GFX6-NEXT: v_mov_b32_e32 v0, s2 ; GFX6-NEXT: s_cmp_lg_u32 s5, 0 @@ -2495,7 +2495,7 @@ ; GFX8-LABEL: s_usubsat_i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s4, s0, s2 -; GFX8-NEXT: s_cselect_b32 s5, 1, 0 +; GFX8-NEXT: s_cselect_b32 s5, -1, 0 ; GFX8-NEXT: s_and_b32 s5, s5, 1 ; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: s_cmp_lg_u32 s5, 0 @@ -2513,7 +2513,7 @@ ; GFX9-LABEL: s_usubsat_i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s4, s0, s2 -; GFX9-NEXT: s_cselect_b32 s5, 1, 0 +; GFX9-NEXT: s_cselect_b32 s5, -1, 0 ; GFX9-NEXT: s_and_b32 s5, s5, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: s_cmp_lg_u32 s5, 0 @@ -2531,7 +2531,7 @@ ; GFX10-LABEL: s_usubsat_i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s4, s0, s2 -; GFX10-NEXT: s_cselect_b32 s5, 1, 0 +; GFX10-NEXT: s_cselect_b32 s5, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[2:3] ; GFX10-NEXT: s_and_b32 s5, s5, 1 ; GFX10-NEXT: s_cmp_lg_u32 s5, 0 @@ -2702,7 +2702,7 @@ ; GFX6-LABEL: s_usubsat_v2i64: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s8, s0, s4 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 ; GFX6-NEXT: v_mov_b32_e32 v0, s4 @@ -2710,7 +2710,7 @@ ; GFX6-NEXT: v_mov_b32_e32 v1, s5 ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1] ; GFX6-NEXT: s_sub_u32 s0, s2, s6 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: s_and_b32 s1, s1, 1 ; GFX6-NEXT: v_mov_b32_e32 v0, s6 ; GFX6-NEXT: s_cmp_lg_u32 s1, 0 @@ -2734,7 +2734,7 @@ ; GFX8-LABEL: s_usubsat_v2i64: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s8, s0, s4 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: v_mov_b32_e32 v0, s4 @@ -2742,7 +2742,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v1, s5 ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1] ; GFX8-NEXT: s_sub_u32 s0, s2, s6 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 @@ -2766,7 +2766,7 @@ ; GFX9-LABEL: s_usubsat_v2i64: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s8, s0, s4 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, s4 @@ -2774,7 +2774,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v1, s5 ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1] ; GFX9-NEXT: s_sub_u32 s0, s2, s6 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 @@ -2798,13 +2798,13 @@ ; GFX10-LABEL: s_usubsat_v2i64: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s8, s0, s4 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_subb_u32 s9, s1, s5 ; GFX10-NEXT: v_cmp_lt_u64_e64 s1, s[0:1], s[4:5] ; GFX10-NEXT: s_sub_u32 s0, s2, s6 -; GFX10-NEXT: s_cselect_b32 s4, 1, 0 +; GFX10-NEXT: s_cselect_b32 s4, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7] ; GFX10-NEXT: s_and_b32 s4, s4, 1 ; GFX10-NEXT: s_cmp_lg_u32 s4, 0 @@ -2826,7 +2826,7 @@ ; GFX6-LABEL: s_usubsat_i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s8, s0, s4 -; GFX6-NEXT: s_cselect_b32 s9, 1, 0 +; GFX6-NEXT: s_cselect_b32 s9, -1, 0 ; GFX6-NEXT: s_and_b32 s9, s9, 1 ; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: s_cmp_lg_u32 s9, 0 @@ -2834,7 +2834,7 @@ ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3] ; GFX6-NEXT: s_subb_u32 s9, s1, s5 ; GFX6-NEXT: v_mov_b32_e32 v0, s6 -; GFX6-NEXT: s_cselect_b32 s10, 1, 0 +; GFX6-NEXT: s_cselect_b32 s10, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, s7 ; GFX6-NEXT: s_and_b32 s10, s10, 1 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc @@ -2843,7 +2843,7 @@ ; GFX6-NEXT: s_subb_u32 s10, s2, s6 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1] -; GFX6-NEXT: s_cselect_b32 s11, 1, 0 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: s_and_b32 s11, s11, 1 ; GFX6-NEXT: s_cmp_lg_u32 s11, 0 @@ -2867,15 +2867,15 @@ ; GFX8-LABEL: s_usubsat_i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s8, s0, s4 -; GFX8-NEXT: s_cselect_b32 s9, 1, 0 +; GFX8-NEXT: s_cselect_b32 s9, -1, 0 ; GFX8-NEXT: s_and_b32 s9, s9, 1 ; GFX8-NEXT: s_cmp_lg_u32 s9, 0 ; GFX8-NEXT: s_subb_u32 s9, s1, s5 -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: s_and_b32 s10, s10, 1 ; GFX8-NEXT: s_cmp_lg_u32 s10, 0 ; GFX8-NEXT: s_subb_u32 s10, s2, s6 -; GFX8-NEXT: s_cselect_b32 s11, 1, 0 +; GFX8-NEXT: s_cselect_b32 s11, -1, 0 ; GFX8-NEXT: s_and_b32 s11, s11, 1 ; GFX8-NEXT: v_mov_b32_e32 v2, s4 ; GFX8-NEXT: s_cmp_lg_u32 s11, 0 @@ -2885,7 +2885,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s7 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX8-NEXT: s_cselect_b32 s6, 1, 0 +; GFX8-NEXT: s_cselect_b32 s6, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s6 @@ -2911,15 +2911,15 @@ ; GFX9-LABEL: s_usubsat_i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s8, s0, s4 -; GFX9-NEXT: s_cselect_b32 s9, 1, 0 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 ; GFX9-NEXT: s_and_b32 s9, s9, 1 ; GFX9-NEXT: s_cmp_lg_u32 s9, 0 ; GFX9-NEXT: s_subb_u32 s9, s1, s5 -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: s_and_b32 s10, s10, 1 ; GFX9-NEXT: s_cmp_lg_u32 s10, 0 ; GFX9-NEXT: s_subb_u32 s10, s2, s6 -; GFX9-NEXT: s_cselect_b32 s11, 1, 0 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 ; GFX9-NEXT: s_and_b32 s11, s11, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, s4 ; GFX9-NEXT: s_cmp_lg_u32 s11, 0 @@ -2929,7 +2929,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s6 ; GFX9-NEXT: v_mov_b32_e32 v1, s7 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] -; GFX9-NEXT: s_cselect_b32 s6, 1, 0 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s6 @@ -2955,23 +2955,23 @@ ; GFX10-LABEL: s_usubsat_i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s8, s0, s4 -; GFX10-NEXT: s_cselect_b32 s9, 1, 0 +; GFX10-NEXT: s_cselect_b32 s9, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[4:5] ; GFX10-NEXT: s_and_b32 s9, s9, 1 ; GFX10-NEXT: s_cmp_lg_u32 s9, 0 ; GFX10-NEXT: s_subb_u32 s9, s1, s5 -; GFX10-NEXT: s_cselect_b32 s10, 1, 0 +; GFX10-NEXT: s_cselect_b32 s10, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s10, s10, 1 ; GFX10-NEXT: s_cmp_lg_u32 s10, 0 ; GFX10-NEXT: s_subb_u32 s10, s2, s6 -; GFX10-NEXT: s_cselect_b32 s11, 1, 0 +; GFX10-NEXT: s_cselect_b32 s11, -1, 0 ; GFX10-NEXT: s_and_b32 s11, s11, 1 ; GFX10-NEXT: s_cmp_lg_u32 s11, 0 ; GFX10-NEXT: s_subb_u32 s1, s3, s7 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7] ; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[6:7] -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2 @@ -3336,12 +3336,12 @@ ; GFX6-LABEL: s_usubsat_v2i128: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_sub_u32 s16, s0, s8 -; GFX6-NEXT: s_cselect_b32 s17, 1, 0 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 ; GFX6-NEXT: s_and_b32 s17, s17, 1 ; GFX6-NEXT: s_cmp_lg_u32 s17, 0 ; GFX6-NEXT: s_subb_u32 s17, s1, s9 ; GFX6-NEXT: v_mov_b32_e32 v2, s8 -; GFX6-NEXT: s_cselect_b32 s18, 1, 0 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v3, s9 ; GFX6-NEXT: s_and_b32 s18, s18, 1 ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3] @@ -3351,7 +3351,7 @@ ; GFX6-NEXT: s_subb_u32 s18, s2, s10 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] -; GFX6-NEXT: s_cselect_b32 s19, 1, 0 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 ; GFX6-NEXT: s_and_b32 s19, s19, 1 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1] @@ -3360,7 +3360,7 @@ ; GFX6-NEXT: s_subb_u32 s19, s3, s11 ; GFX6-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX6-NEXT: s_sub_u32 s0, s4, s12 -; GFX6-NEXT: s_cselect_b32 s1, 1, 0 +; GFX6-NEXT: s_cselect_b32 s1, -1, 0 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX6-NEXT: v_mov_b32_e32 v2, s17 ; GFX6-NEXT: s_and_b32 s1, s1, 1 @@ -3377,7 +3377,7 @@ ; GFX6-NEXT: v_cndmask_b32_e64 v7, v1, 0, vcc ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[2:3] ; GFX6-NEXT: v_mov_b32_e32 v0, s14 -; GFX6-NEXT: s_cselect_b32 s2, 1, 0 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 ; GFX6-NEXT: v_mov_b32_e32 v1, s15 ; GFX6-NEXT: s_and_b32 s2, s2, 1 ; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc @@ -3386,7 +3386,7 @@ ; GFX6-NEXT: s_subb_u32 s2, s6, s14 ; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[6:7], v[0:1] -; GFX6-NEXT: s_cselect_b32 s3, 1, 0 +; GFX6-NEXT: s_cselect_b32 s3, -1, 0 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX6-NEXT: s_and_b32 s3, s3, 1 ; GFX6-NEXT: s_cmp_lg_u32 s3, 0 @@ -3414,15 +3414,15 @@ ; GFX8-LABEL: s_usubsat_v2i128: ; GFX8: ; %bb.0: ; GFX8-NEXT: s_sub_u32 s16, s0, s8 -; GFX8-NEXT: s_cselect_b32 s17, 1, 0 +; GFX8-NEXT: s_cselect_b32 s17, -1, 0 ; GFX8-NEXT: s_and_b32 s17, s17, 1 ; GFX8-NEXT: s_cmp_lg_u32 s17, 0 ; GFX8-NEXT: s_subb_u32 s17, s1, s9 -; GFX8-NEXT: s_cselect_b32 s18, 1, 0 +; GFX8-NEXT: s_cselect_b32 s18, -1, 0 ; GFX8-NEXT: s_and_b32 s18, s18, 1 ; GFX8-NEXT: s_cmp_lg_u32 s18, 0 ; GFX8-NEXT: s_subb_u32 s18, s2, s10 -; GFX8-NEXT: s_cselect_b32 s19, 1, 0 +; GFX8-NEXT: s_cselect_b32 s19, -1, 0 ; GFX8-NEXT: s_and_b32 s19, s19, 1 ; GFX8-NEXT: v_mov_b32_e32 v2, s8 ; GFX8-NEXT: s_cmp_lg_u32 s19, 0 @@ -3432,24 +3432,24 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s10 ; GFX8-NEXT: v_mov_b32_e32 v1, s11 ; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] -; GFX8-NEXT: s_cselect_b32 s10, 1, 0 +; GFX8-NEXT: s_cselect_b32 s10, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX8-NEXT: s_and_b32 s0, 1, s10 ; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX8-NEXT: s_sub_u32 s0, s4, s12 -; GFX8-NEXT: s_cselect_b32 s1, 1, 0 +; GFX8-NEXT: s_cselect_b32 s1, -1, 0 ; GFX8-NEXT: s_and_b32 s1, s1, 1 ; GFX8-NEXT: s_cmp_lg_u32 s1, 0 ; GFX8-NEXT: s_subb_u32 s1, s5, s13 -; GFX8-NEXT: s_cselect_b32 s2, 1, 0 +; GFX8-NEXT: s_cselect_b32 s2, -1, 0 ; GFX8-NEXT: s_and_b32 s2, s2, 1 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX8-NEXT: s_subb_u32 s2, s6, s14 -; GFX8-NEXT: s_cselect_b32 s3, 1, 0 +; GFX8-NEXT: s_cselect_b32 s3, -1, 0 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_mov_b32_e32 v2, s17 ; GFX8-NEXT: s_and_b32 s3, s3, 1 @@ -3468,7 +3468,7 @@ ; GFX8-NEXT: v_mov_b32_e32 v0, s14 ; GFX8-NEXT: s_cmp_eq_u64 s[6:7], s[14:15] ; GFX8-NEXT: v_mov_b32_e32 v1, s15 -; GFX8-NEXT: s_cselect_b32 s8, 1, 0 +; GFX8-NEXT: s_cselect_b32 s8, -1, 0 ; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GFX8-NEXT: s_and_b32 s4, 1, s8 @@ -3498,15 +3498,15 @@ ; GFX9-LABEL: s_usubsat_v2i128: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_sub_u32 s16, s0, s8 -; GFX9-NEXT: s_cselect_b32 s17, 1, 0 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 ; GFX9-NEXT: s_and_b32 s17, s17, 1 ; GFX9-NEXT: s_cmp_lg_u32 s17, 0 ; GFX9-NEXT: s_subb_u32 s17, s1, s9 -; GFX9-NEXT: s_cselect_b32 s18, 1, 0 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 ; GFX9-NEXT: s_and_b32 s18, s18, 1 ; GFX9-NEXT: s_cmp_lg_u32 s18, 0 ; GFX9-NEXT: s_subb_u32 s18, s2, s10 -; GFX9-NEXT: s_cselect_b32 s19, 1, 0 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 ; GFX9-NEXT: s_and_b32 s19, s19, 1 ; GFX9-NEXT: v_mov_b32_e32 v2, s8 ; GFX9-NEXT: s_cmp_lg_u32 s19, 0 @@ -3516,24 +3516,24 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s10 ; GFX9-NEXT: v_mov_b32_e32 v1, s11 ; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] -; GFX9-NEXT: s_cselect_b32 s10, 1, 0 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1] ; GFX9-NEXT: s_and_b32 s0, 1, s10 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0 ; GFX9-NEXT: s_sub_u32 s0, s4, s12 -; GFX9-NEXT: s_cselect_b32 s1, 1, 0 +; GFX9-NEXT: s_cselect_b32 s1, -1, 0 ; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_subb_u32 s1, s5, s13 -; GFX9-NEXT: s_cselect_b32 s2, 1, 0 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 ; GFX9-NEXT: s_and_b32 s2, s2, 1 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: s_cmp_lg_u32 s2, 0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: s_subb_u32 s2, s6, s14 -; GFX9-NEXT: s_cselect_b32 s3, 1, 0 +; GFX9-NEXT: s_cselect_b32 s3, -1, 0 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; GFX9-NEXT: v_mov_b32_e32 v2, s17 ; GFX9-NEXT: s_and_b32 s3, s3, 1 @@ -3552,7 +3552,7 @@ ; GFX9-NEXT: v_mov_b32_e32 v0, s14 ; GFX9-NEXT: s_cmp_eq_u64 s[6:7], s[14:15] ; GFX9-NEXT: v_mov_b32_e32 v1, s15 -; GFX9-NEXT: s_cselect_b32 s8, 1, 0 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 ; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1] ; GFX9-NEXT: s_and_b32 s4, 1, s8 @@ -3582,38 +3582,38 @@ ; GFX10-LABEL: s_usubsat_v2i128: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_sub_u32 s16, s0, s8 -; GFX10-NEXT: s_cselect_b32 s17, 1, 0 +; GFX10-NEXT: s_cselect_b32 s17, -1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[0:1], s[8:9] ; GFX10-NEXT: s_and_b32 s17, s17, 1 ; GFX10-NEXT: s_cmp_lg_u32 s17, 0 ; GFX10-NEXT: s_subb_u32 s17, s1, s9 -; GFX10-NEXT: s_cselect_b32 s18, 1, 0 +; GFX10-NEXT: s_cselect_b32 s18, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0 ; GFX10-NEXT: s_and_b32 s18, s18, 1 ; GFX10-NEXT: s_cmp_lg_u32 s18, 0 ; GFX10-NEXT: s_subb_u32 s18, s2, s10 -; GFX10-NEXT: s_cselect_b32 s19, 1, 0 +; GFX10-NEXT: s_cselect_b32 s19, -1, 0 ; GFX10-NEXT: s_and_b32 s19, s19, 1 ; GFX10-NEXT: s_cmp_lg_u32 s19, 0 ; GFX10-NEXT: s_subb_u32 s19, s3, s11 ; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[10:11] ; GFX10-NEXT: v_cmp_lt_u64_e64 s2, s[2:3], s[10:11] -; GFX10-NEXT: s_cselect_b32 s20, 1, 0 +; GFX10-NEXT: s_cselect_b32 s20, -1, 0 ; GFX10-NEXT: s_and_b32 s0, 1, s20 ; GFX10-NEXT: s_sub_u32 s8, s4, s12 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s2 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: s_subb_u32 s3, s5, s13 -; GFX10-NEXT: s_cselect_b32 s1, 1, 0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo ; GFX10-NEXT: s_and_b32 s1, s1, 1 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: v_cmp_lt_u64_e64 s1, s[4:5], s[12:13] ; GFX10-NEXT: s_subb_u32 s10, s6, s14 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 @@ -3621,7 +3621,7 @@ ; GFX10-NEXT: s_subb_u32 s9, s7, s15 ; GFX10-NEXT: s_cmp_eq_u64 s[6:7], s[14:15] ; GFX10-NEXT: v_cmp_lt_u64_e64 s1, s[6:7], s[14:15] -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s0, 1, s0 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0 ; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll @@ -190,7 +190,7 @@ ; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3] ; GCN-NEXT: s_not_b64 s[4:5], s[2:3] ; GCN-NEXT: s_add_u32 s2, s2, s0 -; GCN-NEXT: s_cselect_b32 s0, 1, 0 +; GCN-NEXT: s_cselect_b32 s0, -1, 0 ; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_addc_u32 s3, s3, s1 @@ -203,7 +203,7 @@ ; GFX10-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3] ; GFX10-NEXT: s_not_b64 s[4:5], s[2:3] ; GFX10-NEXT: s_add_u32 s2, s2, s0 -; GFX10-NEXT: s_cselect_b32 s0, 1, 0 +; GFX10-NEXT: s_cselect_b32 s0, -1, 0 ; GFX10-NEXT: s_and_b32 s0, s0, 1 ; GFX10-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10-NEXT: s_mov_b32 s0, s4 diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -14,7 +14,7 @@ ; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0 ; GFX7-NEXT: s_addc_u32 s4, s6, 0 -; GFX7-NEXT: s_cselect_b64 vcc, 1, 0 +; GFX7-NEXT: s_cselect_b64 vcc, -1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, s4 ; GFX7-NEXT: s_cmp_gt_u32 s6, 31 ; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -31,7 +31,7 @@ ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s4, s6, 0 -; GFX9-NEXT: s_cselect_b64 vcc, 1, 0 +; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, s4 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31 ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc @@ -49,7 +49,7 @@ ; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4 ; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0 ; GFX10-NEXT: s_addc_u32 s5, s4, 0 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0