diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -2479,8 +2479,8 @@
   LLVMContext &Ctx = *DAG.getContext();
   EVT PackedSVT = EVT::getIntegerVT(Ctx, SrcVT.getScalarSizeInBits() / 2);
 
-  // Pack to the largest type possible:
-  // vXi64/vXi32 -> PACK*SDW and vXi16 -> PACK*SWB.
+  // Narrow to the largest type possible:
+  // vXi64/vXi32 -> i16x8.narrow_i32x4_u and vXi16 -> i8x16.narrow_i16x8_u.
   EVT InVT = MVT::i16, OutVT = MVT::i8;
   if (SrcVT.getScalarSizeInBits() > 16) {
     InVT = MVT::i32;
@@ -2494,7 +2494,7 @@
   SDValue Lo = extractSubVector(In, 0, DAG, DL, SubSizeInBits);
   SDValue Hi = extractSubVector(In, NumElems / 2, DAG, DL, SubSizeInBits);
 
-  // 256bit -> 128bit truncate - PACK lower/upper 128-bit subvectors.
+  // 256bit -> 128bit truncate - Narrow lower/upper 128-bit subvectors.
   if (SrcVT.is256BitVector() && DstVT.is128BitVector()) {
     Lo = DAG.getBitcast(InVT, Lo);
     Hi = DAG.getBitcast(InVT, Hi);
@@ -2502,7 +2502,7 @@
     return DAG.getBitcast(DstVT, Res);
   }
 
-  // Recursively pack lower/upper subvectors, concat result and pack again.
+  // Recursively narrow lower/upper subvectors, concat result and narrow again.
   EVT PackedVT = EVT::getVectorVT(Ctx, PackedSVT, NumElems / 2);
   Lo = truncateVectorWithNARROW(Opcode, PackedVT, Lo, DL, DAG);
   Hi = truncateVectorWithNARROW(Opcode, PackedVT, Hi, DL, DAG);