diff --git a/llvm/lib/MC/MCWin64EH.cpp b/llvm/lib/MC/MCWin64EH.cpp
--- a/llvm/lib/MC/MCWin64EH.cpp
+++ b/llvm/lib/MC/MCWin64EH.cpp
@@ -144,8 +144,8 @@
   MCContext &context = streamer.getContext();
 
   streamer.emitValueToAlignment(4);
-  EmitSymbolRefWithOfs(streamer, info->Function, info->Begin);
-  EmitSymbolRefWithOfs(streamer, info->Function, info->End);
+  EmitSymbolRefWithOfs(streamer, info->Begin, info->Begin);
+  EmitSymbolRefWithOfs(streamer, info->Begin, info->End);
   streamer.emitValue(MCSymbolRefExpr::create(info->Symbol,
                                              MCSymbolRefExpr::VK_COFF_IMGREL32,
                                              context), 4);
@@ -1073,7 +1073,7 @@
   MCContext &context = streamer.getContext();
 
   streamer.emitValueToAlignment(4);
-  EmitSymbolRefWithOfs(streamer, info->Function, info->Begin);
+  EmitSymbolRefWithOfs(streamer, info->Begin, info->Begin);
   if (info->PackedInfo)
     streamer.emitInt32(info->PackedInfo);
   else
diff --git a/llvm/test/MC/AArch64/seh.s b/llvm/test/MC/AArch64/seh.s
--- a/llvm/test/MC/AArch64/seh.s
+++ b/llvm/test/MC/AArch64/seh.s
@@ -44,7 +44,7 @@
 // CHECK-NEXT:     0x28 IMAGE_REL_ARM64_ADDR32NB __C_specific_handler
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section (5) .pdata {
-// CHECK-NEXT:     0x0 IMAGE_REL_ARM64_ADDR32NB func
+// CHECK-NEXT:     0x0 IMAGE_REL_ARM64_ADDR32NB .text
 // CHECK-NEXT:     0x4 IMAGE_REL_ARM64_ADDR32NB .xdata
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
diff --git a/llvm/test/MC/COFF/seh-align1.s b/llvm/test/MC/COFF/seh-align1.s
--- a/llvm/test/MC/COFF/seh-align1.s
+++ b/llvm/test/MC/COFF/seh-align1.s
@@ -28,8 +28,8 @@
 // CHECK-NEXT:       IMAGE_SCN_MEM_READ
 // CHECK-NEXT:     ]
 // CHECK:          Relocations [
-// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB smallFunc
-// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB smallFunc
+// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:       [[UnwindDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata
 // CHECK-NEXT:     ]
 // CHECK:          SectionData (
diff --git a/llvm/test/MC/COFF/seh-align2.s b/llvm/test/MC/COFF/seh-align2.s
--- a/llvm/test/MC/COFF/seh-align2.s
+++ b/llvm/test/MC/COFF/seh-align2.s
@@ -29,18 +29,18 @@
 // CHECK-NEXT:       IMAGE_SCN_MEM_READ
 // CHECK-NEXT:     ]
 // CHECK:          Relocations [
-// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB func
-// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB func
+// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:       [[UnwindDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata
 // CHECK-NEXT:     ]
 // CHECK:          SectionData (
-// CHECK-NEXT:       0000: FCFFFFFF 05000000 00000000
+// CHECK-NEXT:       0000: 00000000 09000000 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 // CHECK:      UnwindInformation [
 // CHECK-NEXT:   RuntimeFunction {
-// CHECK-NEXT:     StartAddress: func {{(\+0x[A-F0-9]+ )?}}([[BeginDisp]])
+// CHECK-NEXT:     StartAddress: .text ([[BeginDisp]])
 // CHECK-NEXT:     EndAddress: func {{(\+0x[A-F0-9]+ )?}}([[EndDisp]])
 // CHECK-NEXT:     UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDisp]])
 // CHECK-NEXT:     UnwindInfo {
diff --git a/llvm/test/MC/COFF/seh-align3.s b/llvm/test/MC/COFF/seh-align3.s
--- a/llvm/test/MC/COFF/seh-align3.s
+++ b/llvm/test/MC/COFF/seh-align3.s
@@ -29,18 +29,18 @@
 // CHECK-NEXT:       IMAGE_SCN_MEM_READ
 // CHECK-NEXT:     ]
 // CHECK:          Relocations [
-// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB func
-// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB func
+// CHECK-NEXT:       [[BeginDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:       [[EndDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:       [[UnwindDisp:0x[A-F0-9]+]] IMAGE_REL_AMD64_ADDR32NB .xdata
 // CHECK-NEXT:     ]
 // CHECK:          SectionData (
-// CHECK-NEXT:       0000: FCFFFFFF 05000000 00000000
+// CHECK-NEXT:       0000: 00000000 09000000 00000000
 // CHECK-NEXT:     )
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 // CHECK:      UnwindInformation [
 // CHECK-NEXT:   RuntimeFunction {
-// CHECK-NEXT:     StartAddress: func {{(\+0x[A-F0-9]+ )?}}([[BeginDisp]])
+// CHECK-NEXT:     StartAddress: .text ([[BeginDisp]])
 // CHECK-NEXT:     EndAddress: func {{(\+0x[A-F0-9]+ )?}}([[EndDisp]])
 // CHECK-NEXT:     UnwindInfoAddress: .xdata {{(\+0x[A-F0-9]+ )?}}([[UnwindDisp]])
 // CHECK-NEXT:     UnwindInfo {
diff --git a/llvm/test/MC/COFF/seh.s b/llvm/test/MC/COFF/seh.s
--- a/llvm/test/MC/COFF/seh.s
+++ b/llvm/test/MC/COFF/seh.s
@@ -37,19 +37,19 @@
 // CHECK-NEXT: Relocations [
 // CHECK-NEXT:   Section (4) .xdata {
 // CHECK-NEXT:     0x14 IMAGE_REL_AMD64_ADDR32NB __C_specific_handler
-// CHECK-NEXT:     0x20 IMAGE_REL_AMD64_ADDR32NB func
-// CHECK-NEXT:     0x24 IMAGE_REL_AMD64_ADDR32NB func
+// CHECK-NEXT:     0x20 IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:     0x24 IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:     0x28 IMAGE_REL_AMD64_ADDR32NB .xdata
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section (5) .pdata {
-// CHECK-NEXT:     0x0 IMAGE_REL_AMD64_ADDR32NB func
-// CHECK-NEXT:     0x4 IMAGE_REL_AMD64_ADDR32NB func
+// CHECK-NEXT:     0x0 IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:     0x4 IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:     0x8 IMAGE_REL_AMD64_ADDR32NB .xdata
-// CHECK-NEXT:     0xC IMAGE_REL_AMD64_ADDR32NB func
-// CHECK-NEXT:     0x10 IMAGE_REL_AMD64_ADDR32NB func
+// CHECK-NEXT:     0xC IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:     0x10 IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:     0x14 IMAGE_REL_AMD64_ADDR32NB .xdata
-// CHECK-NEXT:     0x18 IMAGE_REL_AMD64_ADDR32NB smallFunc
-// CHECK-NEXT:     0x1C IMAGE_REL_AMD64_ADDR32NB smallFunc
+// CHECK-NEXT:     0x18 IMAGE_REL_AMD64_ADDR32NB .text
+// CHECK-NEXT:     0x1C IMAGE_REL_AMD64_ADDR32NB .text
 // CHECK-NEXT:     0x20 IMAGE_REL_AMD64_ADDR32NB .xdata
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]