diff --git a/llvm/lib/Target/ARC/ARCISelLowering.cpp b/llvm/lib/Target/ARC/ARCISelLowering.cpp
--- a/llvm/lib/Target/ARC/ARCISelLowering.cpp
+++ b/llvm/lib/Target/ARC/ARCISelLowering.cpp
@@ -121,6 +121,11 @@
   setOperationAction(ISD::SMAX, MVT::i32, Legal);
   setOperationAction(ISD::SMIN, MVT::i32, Legal);
 
+  setOperationAction(ISD::ADDC, MVT::i32, Legal);
+  setOperationAction(ISD::ADDE, MVT::i32, Legal);
+  setOperationAction(ISD::SUBC, MVT::i32, Legal);
+  setOperationAction(ISD::SUBE, MVT::i32, Legal);
+
   // Need barrel shifter.
   setOperationAction(ISD::SHL, MVT::i32, Legal);
   setOperationAction(ISD::SRA, MVT::i32, Legal);
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td
--- a/llvm/lib/Target/ARC/ARCInstrInfo.td
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.td
@@ -328,6 +328,11 @@
 defm : MultiPat<mulhs, MPYM_rrr, MPYM_rru6, MPYM_rrlimm>;
 defm : MultiPat<mulhu, MPYMU_rrr, MPYMU_rru6, MPYMU_rrlimm>;
 
+defm : MultiPat<addc, ADD_f_rrr, ADD_f_rru6, ADD_f_rrlimm>;
+defm : MultiPat<adde, ADC_f_rrr, ADC_f_rru6, ADC_f_rrlimm>;
+defm : MultiPat<subc, SUB_f_rrr, SUB_f_rru6, SUB_f_rrlimm>;
+defm : MultiPat<sube, SBC_f_rrr, SBC_f_rru6, SBC_f_rrlimm>;
+
 // ---------------------------------------------------------------------------
 // Unary Instruction definitions.
 // ---------------------------------------------------------------------------
diff --git a/llvm/test/CodeGen/ARC/alu.ll b/llvm/test/CodeGen/ARC/alu.ll
--- a/llvm/test/CodeGen/ARC/alu.ll
+++ b/llvm/test/CodeGen/ARC/alu.ll
@@ -253,3 +253,20 @@
   ret i64 %v
 }
 
+; CHECK-LABEL: long_long_add
+; CHECK:      add.f %r0, %r0, %r2
+; CHECK-NEXT: adc.f %r1, %r1, %r3
+define i64 @long_long_add(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %add = add nsw i64 %a, %b
+  ret i64 %add
+}
+
+; CHECK-LABEL: long_long_sub
+; CHECK:      sub.f %r0, %r0, %r2
+; CHECK-NEXT: sbc.f %r1, %r1, %r3
+define i64 @long_long_sub(i64 inreg %a, i64 inreg %b) #0 {
+entry:
+  %sub = sub nsw i64 %a, %b
+  ret i64 %sub
+}