Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp =================================================================== --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -234,6 +234,9 @@ Parser.addAliasForDirective(".dword", ".8byte"); setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + MCAsmParserExtension::Initialize(Parser); + getTargetStreamer().emitTargetAttributes(STI); + auto ABIName = StringRef(Options.ABIName); if (ABIName.endswith("f") && !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { Index: llvm/test/CodeGen/RISCV/branch-relaxation.ll =================================================================== --- llvm/test/CodeGen/RISCV/branch-relaxation.ll +++ llvm/test/CodeGen/RISCV/branch-relaxation.ll @@ -15,6 +15,8 @@ ; CHECK-NEXT: j .LBB0_2 ; CHECK-NEXT: .LBB0_1: # %iftrue ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv32i2p0" ; CHECK-NEXT: .zero 4096 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: .LBB0_2: # %tail @@ -40,6 +42,8 @@ ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv32i2p0" ; CHECK-NEXT: .zero 1048576 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: addi a0, zero, 1 Index: llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll +++ llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll @@ -8,6 +8,8 @@ ; RV32-LABEL: constraint_S: ; RV32: # %bb.0: ; RV32-NEXT: #APP +; RV32-NEXT: .attribute 4, 16 +; RV32-NEXT: .attribute 5, "rv32i2p0" ; RV32-NEXT: lui a0, %hi(var) ; RV32-NEXT: addi a0, a0, %lo(var) ; RV32-NEXT: #NO_APP @@ -16,6 +18,8 @@ ; RV64-LABEL: constraint_S: ; RV64: # %bb.0: ; RV64-NEXT: #APP +; RV64-NEXT: .attribute 4, 16 +; RV64-NEXT: .attribute 5, "rv64i2p0" ; RV64-NEXT: lui a0, %hi(var) ; RV64-NEXT: addi a0, a0, %lo(var) ; RV64-NEXT: #NO_APP @@ -31,6 +35,8 @@ ; RV32-NEXT: .Ltmp0: # Block address taken ; RV32-NEXT: # %bb.1: # %L1 ; RV32-NEXT: #APP +; RV32-NEXT: .attribute 4, 16 +; RV32-NEXT: .attribute 5, "rv32i2p0" ; RV32-NEXT: lui a0, %hi(.Ltmp0) ; RV32-NEXT: addi a0, a0, %lo(.Ltmp0) ; RV32-NEXT: #NO_APP @@ -41,6 +47,8 @@ ; RV64-NEXT: .Ltmp0: # Block address taken ; RV64-NEXT: # %bb.1: # %L1 ; RV64-NEXT: #APP +; RV64-NEXT: .attribute 4, 16 +; RV64-NEXT: .attribute 5, "rv64i2p0" ; RV64-NEXT: lui a0, %hi(.Ltmp0) ; RV64-NEXT: addi a0, a0, %lo(.Ltmp0) ; RV64-NEXT: #NO_APP Index: llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll +++ llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll @@ -20,6 +20,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft0, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -28,6 +30,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft0, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -40,6 +44,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft0, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -48,6 +54,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft0, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -60,6 +68,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -68,6 +78,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -80,6 +92,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -88,6 +102,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -100,6 +116,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -108,6 +126,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -120,6 +140,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -128,6 +150,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -140,6 +164,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -148,6 +174,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -160,6 +188,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -168,6 +198,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -180,6 +212,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -188,6 +222,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -200,6 +236,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -208,6 +246,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -220,6 +260,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -228,6 +270,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -240,6 +284,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -248,6 +294,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -260,6 +308,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -268,6 +318,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -280,6 +332,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -288,6 +342,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -300,6 +356,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -308,6 +366,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -320,6 +380,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -328,6 +390,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -344,6 +408,8 @@ ; RV32IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload @@ -356,6 +422,8 @@ ; RV64IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload @@ -373,6 +441,8 @@ ; RV32IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload @@ -385,6 +455,8 @@ ; RV64IFD-NEXT: fsd fs0, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload @@ -402,6 +474,8 @@ ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload @@ -414,6 +488,8 @@ ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload @@ -431,6 +507,8 @@ ; RV32IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload @@ -443,6 +521,8 @@ ; RV64IFD-NEXT: fsd fs1, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs1, 8(sp) # 8-byte Folded Reload @@ -456,6 +536,8 @@ ; RV32IFD-LABEL: explicit_register_f10: ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -463,6 +545,8 @@ ; RV64IFD-LABEL: explicit_register_f10: ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -474,6 +558,8 @@ ; RV32IFD-LABEL: explicit_register_fa0: ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa0 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -481,6 +567,8 @@ ; RV64IFD-LABEL: explicit_register_fa0: ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa0 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -493,6 +581,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -501,6 +591,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -513,6 +605,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa1, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa1 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -521,6 +615,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa1, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa1 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -533,6 +629,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -541,6 +639,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -553,6 +653,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -561,6 +663,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -573,6 +677,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -581,6 +687,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -593,6 +701,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -601,6 +711,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -613,6 +725,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -621,6 +735,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -633,6 +749,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -641,6 +759,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -653,6 +773,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -661,6 +783,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -673,6 +797,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -681,6 +807,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -693,6 +821,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -701,6 +831,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -713,6 +845,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -721,6 +855,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -733,6 +869,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -741,6 +879,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -753,6 +893,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d fa7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fa7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -761,6 +903,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d fa7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fa7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -776,6 +920,8 @@ ; RV32IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload @@ -788,6 +934,8 @@ ; RV64IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload @@ -805,6 +953,8 @@ ; RV32IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs2, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs2 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload @@ -817,6 +967,8 @@ ; RV64IFD-NEXT: fsd fs2, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs2, 8(sp) # 8-byte Folded Reload @@ -834,6 +986,8 @@ ; RV32IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload @@ -846,6 +1000,8 @@ ; RV64IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload @@ -863,6 +1019,8 @@ ; RV32IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs3, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs3 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload @@ -875,6 +1033,8 @@ ; RV64IFD-NEXT: fsd fs3, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs3, 8(sp) # 8-byte Folded Reload @@ -892,6 +1052,8 @@ ; RV32IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload @@ -904,6 +1066,8 @@ ; RV64IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload @@ -921,6 +1085,8 @@ ; RV32IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs4, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs4 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload @@ -933,6 +1099,8 @@ ; RV64IFD-NEXT: fsd fs4, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs4, 8(sp) # 8-byte Folded Reload @@ -950,6 +1118,8 @@ ; RV32IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload @@ -962,6 +1132,8 @@ ; RV64IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload @@ -979,6 +1151,8 @@ ; RV32IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs5, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs5 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload @@ -991,6 +1165,8 @@ ; RV64IFD-NEXT: fsd fs5, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs5, 8(sp) # 8-byte Folded Reload @@ -1008,6 +1184,8 @@ ; RV32IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload @@ -1020,6 +1198,8 @@ ; RV64IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload @@ -1037,6 +1217,8 @@ ; RV32IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs6, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs6 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload @@ -1049,6 +1231,8 @@ ; RV64IFD-NEXT: fsd fs6, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs6, 8(sp) # 8-byte Folded Reload @@ -1066,6 +1250,8 @@ ; RV32IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload @@ -1078,6 +1264,8 @@ ; RV64IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload @@ -1095,6 +1283,8 @@ ; RV32IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs7, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs7 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload @@ -1107,6 +1297,8 @@ ; RV64IFD-NEXT: fsd fs7, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs7, 8(sp) # 8-byte Folded Reload @@ -1124,6 +1316,8 @@ ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs8, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs8 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload @@ -1136,6 +1330,8 @@ ; RV64IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload @@ -1153,6 +1349,8 @@ ; RV32IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs8, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs8 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload @@ -1165,6 +1363,8 @@ ; RV64IFD-NEXT: fsd fs8, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs8, 8(sp) # 8-byte Folded Reload @@ -1182,6 +1382,8 @@ ; RV32IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs9, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs9 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload @@ -1194,6 +1396,8 @@ ; RV64IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload @@ -1211,6 +1415,8 @@ ; RV32IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs9, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs9 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload @@ -1223,6 +1429,8 @@ ; RV64IFD-NEXT: fsd fs9, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs9, 8(sp) # 8-byte Folded Reload @@ -1240,6 +1448,8 @@ ; RV32IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs10, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs10 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload @@ -1252,6 +1462,8 @@ ; RV64IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload @@ -1269,6 +1481,8 @@ ; RV32IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs10, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs10 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload @@ -1281,6 +1495,8 @@ ; RV64IFD-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs10, 8(sp) # 8-byte Folded Reload @@ -1298,6 +1514,8 @@ ; RV32IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs11, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs11 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload @@ -1310,6 +1528,8 @@ ; RV64IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload @@ -1327,6 +1547,8 @@ ; RV32IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill ; RV32IFD-NEXT: fmv.d fs11, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, fs11 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload @@ -1339,6 +1561,8 @@ ; RV64IFD-NEXT: fsd fs11, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: fld fs11, 8(sp) # 8-byte Folded Reload @@ -1353,6 +1577,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft8, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft8 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1361,6 +1587,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft8, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft8 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1373,6 +1601,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft8, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft8 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1381,6 +1611,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft8, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft8 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1393,6 +1625,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft9, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft9 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1401,6 +1635,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft9, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft9 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1413,6 +1649,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft9, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft9 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1421,6 +1659,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft9, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft9 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1433,6 +1673,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft10, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft10 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1441,6 +1683,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft10, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft10 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1453,6 +1697,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft10, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft10 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1461,6 +1707,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft10, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft10 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1473,6 +1721,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft11, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft11 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1481,6 +1731,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft11, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft11 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret @@ -1493,6 +1745,8 @@ ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: fmv.d ft11, fa0 ; RV32IFD-NEXT: #APP +; RV32IFD-NEXT: .attribute 4, 16 +; RV32IFD-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32IFD-NEXT: fcvt.w.d a0, ft11 ; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: ret @@ -1501,6 +1755,8 @@ ; RV64IFD: # %bb.0: ; RV64IFD-NEXT: fmv.d ft11, fa0 ; RV64IFD-NEXT: #APP +; RV64IFD-NEXT: .attribute 4, 16 +; RV64IFD-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64IFD-NEXT: fcvt.w.d a0, ft11 ; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: ret Index: llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll +++ llvm/test/CodeGen/RISCV/inline-asm-d-constraint-f.ll @@ -16,6 +16,8 @@ ; RV32F-NEXT: lui a0, %hi(gd) ; RV32F-NEXT: fld ft1, %lo(gd)(a0) ; RV32F-NEXT: #APP +; RV32F-NEXT: .attribute 4, 16 +; RV32F-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32F-NEXT: fadd.d ft0, ft0, ft1 ; RV32F-NEXT: #NO_APP ; RV32F-NEXT: fsd ft0, 8(sp) @@ -30,6 +32,8 @@ ; RV64F-NEXT: fld ft0, %lo(gd)(a1) ; RV64F-NEXT: fmv.d.x ft1, a0 ; RV64F-NEXT: #APP +; RV64F-NEXT: .attribute 4, 16 +; RV64F-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64F-NEXT: fadd.d ft0, ft1, ft0 ; RV64F-NEXT: #NO_APP ; RV64F-NEXT: fmv.x.d a0, ft0 @@ -49,6 +53,8 @@ ; RV32F-NEXT: lui a0, %hi(gd) ; RV32F-NEXT: fld fs0, %lo(gd)(a0) ; RV32F-NEXT: #APP +; RV32F-NEXT: .attribute 4, 16 +; RV32F-NEXT: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32F-NEXT: fadd.d ft0, fa1, fs0 ; RV32F-NEXT: #NO_APP ; RV32F-NEXT: fsd ft0, 8(sp) @@ -63,6 +69,8 @@ ; RV64F-NEXT: fld fs0, %lo(gd)(a1) ; RV64F-NEXT: fmv.d.x fa1, a0 ; RV64F-NEXT: #APP +; RV64F-NEXT: .attribute 4, 16 +; RV64F-NEXT: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64F-NEXT: fadd.d ft0, fa1, fs0 ; RV64F-NEXT: #NO_APP ; RV64F-NEXT: fmv.x.d a0, ft0 Index: llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll +++ llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll @@ -20,6 +20,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft0, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -28,6 +30,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft0, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -40,6 +44,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft0, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -48,6 +54,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft0, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -60,6 +68,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -68,6 +78,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -80,6 +92,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -88,6 +102,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -100,6 +116,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -108,6 +126,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -120,6 +140,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -128,6 +150,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -140,6 +164,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -148,6 +174,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -160,6 +188,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -168,6 +198,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -180,6 +212,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -188,6 +222,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -200,6 +236,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -208,6 +246,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -220,6 +260,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -228,6 +270,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -240,6 +284,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -248,6 +294,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -260,6 +308,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -268,6 +318,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -280,6 +332,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -288,6 +342,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -300,6 +356,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -308,6 +366,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -320,6 +380,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -328,6 +390,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -344,6 +408,8 @@ ; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload @@ -356,6 +422,8 @@ ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload @@ -373,6 +441,8 @@ ; RV32IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload @@ -385,6 +455,8 @@ ; RV64IF-NEXT: fsw fs0, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs0, 12(sp) # 4-byte Folded Reload @@ -402,6 +474,8 @@ ; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload @@ -414,6 +488,8 @@ ; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload @@ -431,6 +507,8 @@ ; RV32IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload @@ -443,6 +521,8 @@ ; RV64IF-NEXT: fsw fs1, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs1, 12(sp) # 4-byte Folded Reload @@ -456,6 +536,8 @@ ; RV32IF-LABEL: explicit_register_f10: ; RV32IF: # %bb.0: ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -463,6 +545,8 @@ ; RV64IF-LABEL: explicit_register_f10: ; RV64IF: # %bb.0: ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -474,6 +558,8 @@ ; RV32IF-LABEL: explicit_register_fa0: ; RV32IF: # %bb.0: ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa0 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -481,6 +567,8 @@ ; RV64IF-LABEL: explicit_register_fa0: ; RV64IF: # %bb.0: ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa0 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -493,6 +581,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -501,6 +591,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -513,6 +605,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa1, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa1 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -521,6 +615,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa1, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa1 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -533,6 +629,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -541,6 +639,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -553,6 +653,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -561,6 +663,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -573,6 +677,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -581,6 +687,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -593,6 +701,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -601,6 +711,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -613,6 +725,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -621,6 +735,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -633,6 +749,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -641,6 +759,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -653,6 +773,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -661,6 +783,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -673,6 +797,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -681,6 +807,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -693,6 +821,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -701,6 +831,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -713,6 +845,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -721,6 +855,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -733,6 +869,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -741,6 +879,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -753,6 +893,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s fa7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fa7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -761,6 +903,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s fa7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fa7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -776,6 +920,8 @@ ; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload @@ -788,6 +934,8 @@ ; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload @@ -805,6 +953,8 @@ ; RV32IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs2, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs2 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload @@ -817,6 +967,8 @@ ; RV64IF-NEXT: fsw fs2, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs2, 12(sp) # 4-byte Folded Reload @@ -834,6 +986,8 @@ ; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload @@ -846,6 +1000,8 @@ ; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload @@ -863,6 +1019,8 @@ ; RV32IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs3, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs3 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload @@ -875,6 +1033,8 @@ ; RV64IF-NEXT: fsw fs3, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs3, 12(sp) # 4-byte Folded Reload @@ -892,6 +1052,8 @@ ; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload @@ -904,6 +1066,8 @@ ; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload @@ -921,6 +1085,8 @@ ; RV32IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs4, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs4 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload @@ -933,6 +1099,8 @@ ; RV64IF-NEXT: fsw fs4, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs4, 12(sp) # 4-byte Folded Reload @@ -950,6 +1118,8 @@ ; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload @@ -962,6 +1132,8 @@ ; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload @@ -979,6 +1151,8 @@ ; RV32IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs5, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs5 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload @@ -991,6 +1165,8 @@ ; RV64IF-NEXT: fsw fs5, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs5, 12(sp) # 4-byte Folded Reload @@ -1008,6 +1184,8 @@ ; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload @@ -1020,6 +1198,8 @@ ; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload @@ -1037,6 +1217,8 @@ ; RV32IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs6, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs6 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload @@ -1049,6 +1231,8 @@ ; RV64IF-NEXT: fsw fs6, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs6, 12(sp) # 4-byte Folded Reload @@ -1066,6 +1250,8 @@ ; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload @@ -1078,6 +1264,8 @@ ; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload @@ -1095,6 +1283,8 @@ ; RV32IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs7, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs7 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload @@ -1107,6 +1297,8 @@ ; RV64IF-NEXT: fsw fs7, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs7, 12(sp) # 4-byte Folded Reload @@ -1124,6 +1316,8 @@ ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs8, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs8 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload @@ -1136,6 +1330,8 @@ ; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload @@ -1153,6 +1349,8 @@ ; RV32IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs8, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs8 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload @@ -1165,6 +1363,8 @@ ; RV64IF-NEXT: fsw fs8, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs8, 12(sp) # 4-byte Folded Reload @@ -1182,6 +1382,8 @@ ; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs9, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs9 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload @@ -1194,6 +1396,8 @@ ; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload @@ -1211,6 +1415,8 @@ ; RV32IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs9, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs9 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload @@ -1223,6 +1429,8 @@ ; RV64IF-NEXT: fsw fs9, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs9, 12(sp) # 4-byte Folded Reload @@ -1240,6 +1448,8 @@ ; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs10, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs10 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload @@ -1252,6 +1462,8 @@ ; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload @@ -1269,6 +1481,8 @@ ; RV32IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs10, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs10 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload @@ -1281,6 +1495,8 @@ ; RV64IF-NEXT: fsw fs10, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs10, 12(sp) # 4-byte Folded Reload @@ -1298,6 +1514,8 @@ ; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs11, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs11 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload @@ -1310,6 +1528,8 @@ ; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload @@ -1327,6 +1547,8 @@ ; RV32IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs11, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, fs11 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload @@ -1339,6 +1561,8 @@ ; RV64IF-NEXT: fsw fs11, 12(sp) # 4-byte Folded Spill ; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: flw fs11, 12(sp) # 4-byte Folded Reload @@ -1353,6 +1577,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft8, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft8 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1361,6 +1587,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft8, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft8 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1373,6 +1601,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft8, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft8 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1381,6 +1611,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft8, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft8 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1393,6 +1625,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft9, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft9 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1401,6 +1635,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft9, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft9 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1413,6 +1649,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft9, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft9 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1421,6 +1659,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft9, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft9 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1433,6 +1673,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft10, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft10 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1441,6 +1683,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft10, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft10 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1453,6 +1697,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft10, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft10 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1461,6 +1707,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft10, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft10 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1473,6 +1721,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft11, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft11 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1481,6 +1731,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft11, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft11 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret @@ -1493,6 +1745,8 @@ ; RV32IF: # %bb.0: ; RV32IF-NEXT: fmv.s ft11, fa0 ; RV32IF-NEXT: #APP +; RV32IF-NEXT: .attribute 4, 16 +; RV32IF-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32IF-NEXT: fcvt.w.s a0, ft11 ; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: ret @@ -1501,6 +1755,8 @@ ; RV64IF: # %bb.0: ; RV64IF-NEXT: fmv.s ft11, fa0 ; RV64IF-NEXT: #APP +; RV64IF-NEXT: .attribute 4, 16 +; RV64IF-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64IF-NEXT: fcvt.w.s a0, ft11 ; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: ret Index: llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll =================================================================== --- llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll +++ llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll @@ -13,6 +13,8 @@ ; RV32F-NEXT: flw ft0, %lo(gf)(a1) ; RV32F-NEXT: fmv.w.x ft1, a0 ; RV32F-NEXT: #APP +; RV32F-NEXT: .attribute 4, 16 +; RV32F-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32F-NEXT: fadd.s ft0, ft1, ft0 ; RV32F-NEXT: #NO_APP ; RV32F-NEXT: fmv.x.w a0, ft0 @@ -24,6 +26,8 @@ ; RV64F-NEXT: flw ft0, %lo(gf)(a1) ; RV64F-NEXT: fmv.w.x ft1, a0 ; RV64F-NEXT: #APP +; RV64F-NEXT: .attribute 4, 16 +; RV64F-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64F-NEXT: fadd.s ft0, ft1, ft0 ; RV64F-NEXT: #NO_APP ; RV64F-NEXT: fmv.x.w a0, ft0 @@ -40,6 +44,8 @@ ; RV32F-NEXT: flw fs0, %lo(gf)(a1) ; RV32F-NEXT: fmv.w.x fa0, a0 ; RV32F-NEXT: #APP +; RV32F-NEXT: .attribute 4, 16 +; RV32F-NEXT: .attribute 5, "rv32i2p0_f2p0" ; RV32F-NEXT: fadd.s ft0, fa0, fs0 ; RV32F-NEXT: #NO_APP ; RV32F-NEXT: fmv.x.w a0, ft0 @@ -51,6 +57,8 @@ ; RV64F-NEXT: flw fs0, %lo(gf)(a1) ; RV64F-NEXT: fmv.w.x fa0, a0 ; RV64F-NEXT: #APP +; RV64F-NEXT: .attribute 4, 16 +; RV64F-NEXT: .attribute 5, "rv64i2p0_f2p0" ; RV64F-NEXT: fadd.s ft0, fa0, fs0 ; RV64F-NEXT: #NO_APP ; RV64F-NEXT: fmv.x.w a0, ft0 Index: llvm/test/CodeGen/RISCV/large-stack.ll =================================================================== --- llvm/test/CodeGen/RISCV/large-stack.ll +++ llvm/test/CodeGen/RISCV/large-stack.ll @@ -63,11 +63,15 @@ ; RV32I-FPELIM-NEXT: addi a2, sp, 8 ; RV32I-FPELIM-NEXT: add a1, a2, a1 ; RV32I-FPELIM-NEXT: #APP +; RV32I-FPELIM-NEXT: .attribute 4, 16 +; RV32I-FPELIM-NEXT: .attribute 5, "rv32i2p0" ; RV32I-FPELIM-NEXT: nop ; RV32I-FPELIM-EMPTY: ; RV32I-FPELIM-NEXT: #NO_APP ; RV32I-FPELIM-NEXT: sw a0, 0(a1) ; RV32I-FPELIM-NEXT: #APP +; RV32I-FPELIM-NEXT: .attribute 4, 16 +; RV32I-FPELIM-NEXT: .attribute 5, "rv32i2p0" ; RV32I-FPELIM-NEXT: nop ; RV32I-FPELIM-EMPTY: ; RV32I-FPELIM-NEXT: #NO_APP @@ -103,11 +107,15 @@ ; RV32I-WITHFP-NEXT: add a2, s0, a2 ; RV32I-WITHFP-NEXT: add a1, a2, a1 ; RV32I-WITHFP-NEXT: #APP +; RV32I-WITHFP-NEXT: .attribute 4, 16 +; RV32I-WITHFP-NEXT: .attribute 5, "rv32i2p0" ; RV32I-WITHFP-NEXT: nop ; RV32I-WITHFP-EMPTY: ; RV32I-WITHFP-NEXT: #NO_APP ; RV32I-WITHFP-NEXT: sw a0, 0(a1) ; RV32I-WITHFP-NEXT: #APP +; RV32I-WITHFP-NEXT: .attribute 4, 16 +; RV32I-WITHFP-NEXT: .attribute 5, "rv32i2p0" ; RV32I-WITHFP-NEXT: nop ; RV32I-WITHFP-EMPTY: ; RV32I-WITHFP-NEXT: #NO_APP Index: llvm/test/CodeGen/RISCV/rvv/inline-asm.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/inline-asm.ll +++ llvm/test/CodeGen/RISCV/rvv/inline-asm.ll @@ -6,6 +6,8 @@ ; CHECK-LABEL: test_1xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -18,6 +20,8 @@ ; CHECK-LABEL: test_2xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -30,6 +34,8 @@ ; CHECK-LABEL: test_4xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -42,6 +48,8 @@ ; CHECK-LABEL: test_8xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -54,6 +62,8 @@ ; CHECK-LABEL: test_16xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -66,6 +76,8 @@ ; CHECK-LABEL: test_32xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -78,6 +90,8 @@ ; CHECK-LABEL: test_64xi1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -90,6 +104,8 @@ ; CHECK-LABEL: test_1xi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -102,6 +118,8 @@ ; CHECK-LABEL: test_2xi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -114,6 +132,8 @@ ; CHECK-LABEL: test_4xi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -126,6 +146,8 @@ ; CHECK-LABEL: test_8xi64: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -138,6 +160,8 @@ ; CHECK-LABEL: test_1xi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -150,6 +174,8 @@ ; CHECK-LABEL: test_2xi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -162,6 +188,8 @@ ; CHECK-LABEL: test_4xi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -174,6 +202,8 @@ ; CHECK-LABEL: test_8xi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -186,6 +216,8 @@ ; CHECK-LABEL: test_16xi32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -198,6 +230,8 @@ ; CHECK-LABEL: test_1xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -210,6 +244,8 @@ ; CHECK-LABEL: test_2xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -222,6 +258,8 @@ ; CHECK-LABEL: test_4xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -234,6 +272,8 @@ ; CHECK-LABEL: test_8xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -246,6 +286,8 @@ ; CHECK-LABEL: test_16xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -258,6 +300,8 @@ ; CHECK-LABEL: test_32xi16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -270,6 +314,8 @@ ; CHECK-LABEL: test_1xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -282,6 +328,8 @@ ; CHECK-LABEL: test_2xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -294,6 +342,8 @@ ; CHECK-LABEL: test_4xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -306,6 +356,8 @@ ; CHECK-LABEL: test_8xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -318,6 +370,8 @@ ; CHECK-LABEL: test_16xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v10 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -330,6 +384,8 @@ ; CHECK-LABEL: test_32xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v12 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -342,6 +398,8 @@ ; CHECK-LABEL: test_64xi8: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret @@ -356,6 +414,8 @@ ; CHECK-NEXT: vmv1r.v v2, v9 ; CHECK-NEXT: vmv1r.v v1, v8 ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v0, v1, v2 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vmv1r.v v8, v0 @@ -371,6 +431,8 @@ ; CHECK-NEXT: vmv1r.v v2, v9 ; CHECK-NEXT: vmv1r.v v1, v8 ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v0, v1, v2 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vmv1r.v v8, v0 @@ -386,6 +448,8 @@ ; CHECK-NEXT: vmv2r.v v4, v10 ; CHECK-NEXT: vmv2r.v v2, v8 ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vadd.vv v0, v2, v4 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: vmv2r.v v8, v0 @@ -401,6 +465,8 @@ ; CHECK-NEXT: vmv1r.v v2, v8 ; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: #APP +; CHECK-NEXT: .attribute 4, 16 +; CHECK-NEXT: .attribute 5, "rv64i2p0_v0p10" ; CHECK-NEXT: vmand.mm v0, v1, v2 ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret Index: llvm/test/MC/RISCV/fde-reloc.s =================================================================== --- llvm/test/MC/RISCV/fde-reloc.s +++ llvm/test/MC/RISCV/fde-reloc.s @@ -11,7 +11,7 @@ ret .cfi_endproc -# CHECK: Section (4) .rela.eh_frame { +# CHECK: Section (5) .rela.eh_frame { # CHECK-NEXT: 0x1C R_RISCV_32_PCREL - 0x0 # CHECK-NEXT: 0x20 R_RISCV_ADD32 - 0x0 # CHECK-NEXT: 0x20 R_RISCV_SUB32 - 0x0 Index: llvm/test/MC/RISCV/rvf-user-csr-names.s =================================================================== --- llvm/test/MC/RISCV/rvf-user-csr-names.s +++ llvm/test/MC/RISCV/rvf-user-csr-names.s @@ -3,7 +3,7 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ # RUN: | llvm-objdump -d --mattr=+f - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s # @@ -12,7 +12,7 @@ # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ # RUN: | llvm-objdump -d --mattr=+f - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \ +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s