diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -2675,7 +2675,7 @@ QualType EltTy = VecTy->castAs()->getElementType(); unsigned EltSize = Info.Ctx.getTypeSize(EltTy); bool BigEndian = Info.Ctx.getTargetInfo().isBigEndian(); - Res = llvm::APInt::getNullValue(VecSize); + Res = llvm::APInt::getZero(VecSize); for (unsigned i = 0; i < SVal.getVectorLength(); i++) { APValue &Elt = SVal.getVectorElt(i); llvm::APInt EltAsInt; diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -1642,7 +1642,7 @@ } else { assert(NumPositiveBits <= Bitwidth); End = llvm::APInt(Bitwidth, 1) << NumPositiveBits; - Min = llvm::APInt(Bitwidth, 0); + Min = llvm::APInt::getZero(Bitwidth); } } return true; diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -2247,8 +2247,7 @@ } IntegerLiteral AllocationSizeLiteral( - Context, - AllocationSize.getValueOr(llvm::APInt::getNullValue(SizeTyWidth)), + Context, AllocationSize.getValueOr(llvm::APInt::getZero(SizeTyWidth)), SizeTy, SourceLocation()); // Otherwise, if we failed to constant-fold the allocation size, we'll // just give up and pass-in something opaque, that isn't a null pointer. @@ -2593,10 +2592,9 @@ // FIXME: Should the Sema create the expression and embed it in the syntax // tree? Or should the consumer just recalculate the value? // FIXME: Using a dummy value will interact poorly with attribute enable_if. - IntegerLiteral Size(Context, llvm::APInt::getNullValue( - Context.getTargetInfo().getPointerWidth(0)), - Context.getSizeType(), - SourceLocation()); + IntegerLiteral Size( + Context, llvm::APInt::getZero(Context.getTargetInfo().getPointerWidth(0)), + Context.getSizeType(), SourceLocation()); AllocArgs.push_back(&Size); QualType AlignValT = Context.VoidTy; diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -17153,7 +17153,7 @@ } else if (Type->isScalarType()) { uint64_t Size = Context.getTypeSize(Type); QualType IntTy = Context.getIntTypeForBitwidth(Size, /*Signed=*/0); - llvm::APInt InitValue = llvm::APInt::getAllOnesValue(Size); + llvm::APInt InitValue = llvm::APInt::getAllOnes(Size); Init = IntegerLiteral::Create(Context, InitValue, IntTy, ELoc); } if (Init && OrigType->isAnyComplexType()) { @@ -18361,7 +18361,7 @@ Expr::EvalResult Result; if (Length && !Length->isValueDependent() && Length->EvaluateAsInt(Result, Context) && - Result.Val.getInt().isNullValue()) { + Result.Val.getInt().isZero()) { Diag(ELoc, diag::err_omp_depend_zero_length_array_section_not_allowed) << SimpleExpr->getSourceRange(); @@ -18754,7 +18754,7 @@ Expr::EvalResult Result; if (!AE->getIdx()->isValueDependent() && AE->getIdx()->EvaluateAsInt(Result, SemaRef.getASTContext()) && - !Result.Val.getInt().isNullValue()) { + !Result.Val.getInt().isZero()) { SemaRef.Diag(AE->getIdx()->getExprLoc(), diag::err_omp_invalid_map_this_expr); SemaRef.Diag(AE->getIdx()->getExprLoc(), @@ -18842,7 +18842,7 @@ if (OASE->getLowerBound() && !OASE->getLowerBound()->isValueDependent() && OASE->getLowerBound()->EvaluateAsInt(ResultL, SemaRef.getASTContext()) && - !ResultL.Val.getInt().isNullValue()) { + !ResultL.Val.getInt().isZero()) { SemaRef.Diag(OASE->getLowerBound()->getExprLoc(), diag::err_omp_invalid_map_this_expr); SemaRef.Diag(OASE->getLowerBound()->getExprLoc(), diff --git a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp --- a/clang/lib/StaticAnalyzer/Core/MemRegion.cpp +++ b/clang/lib/StaticAnalyzer/Core/MemRegion.cpp @@ -789,7 +789,7 @@ if (const auto *CAT = dyn_cast(AT)) { const llvm::APInt &Size = CAT->getSize(); - if (Size.isNullValue()) + if (Size.isZero()) return true; const AnalyzerOptions &Opts = SVB.getAnalyzerOptions(); diff --git a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp --- a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp +++ b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp @@ -2946,9 +2946,9 @@ bool bnz) { bool success = false; int32_t target = 0; - llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt wr_val = llvm::APInt::getZero(128); llvm::APInt fail_value = llvm::APInt::getMaxValue(128); - llvm::APInt zero_value = llvm::APInt::getNullValue(128); + llvm::APInt zero_value = llvm::APInt::getZero(128); RegisterValue reg_value; uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); diff --git a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp --- a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp +++ b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp @@ -2258,9 +2258,9 @@ bool bnz) { bool success = false; int64_t target = 0; - llvm::APInt wr_val = llvm::APInt::getNullValue(128); + llvm::APInt wr_val = llvm::APInt::getZero(128); llvm::APInt fail_value = llvm::APInt::getMaxValue(128); - llvm::APInt zero_value = llvm::APInt::getNullValue(128); + llvm::APInt zero_value = llvm::APInt::getZero(128); RegisterValue reg_value; uint32_t wt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); diff --git a/lldb/source/Utility/Scalar.cpp b/lldb/source/Utility/Scalar.cpp --- a/lldb/source/Utility/Scalar.cpp +++ b/lldb/source/Utility/Scalar.cpp @@ -714,7 +714,7 @@ return Status("insufficient data"); m_type = e_int; m_integer = - APSInt(APInt::getNullValue(8 * byte_size), encoding == eEncodingUint); + APSInt(APInt::getZero(8 * byte_size), encoding == eEncodingUint); if (data.GetByteOrder() == endian::InlHostByteOrder()) { llvm::LoadIntFromMemory(m_integer, data.GetDataStart(), byte_size); } else { diff --git a/llvm/include/llvm/ADT/APInt.h b/llvm/include/llvm/ADT/APInt.h --- a/llvm/include/llvm/ADT/APInt.h +++ b/llvm/include/llvm/ADT/APInt.h @@ -173,10 +173,11 @@ /// \name Value Generators /// @{ - /// Get the '0' value. - /// - /// \returns the '0' value for an APInt of the specified bit-width. - static APInt getNullValue(unsigned numBits) { return APInt(numBits, 0); } + /// Get the '0' value for the specified bit-width. + static APInt getZero(unsigned numBits) { return APInt(numBits, 0); } + + /// NOTE: This is soft-deprecated. Please use `getZero()` instead. + static APInt getNullValue(unsigned numBits) { return getZero(numBits); } /// Gets maximum unsigned value of APInt for specific bit width. static APInt getMaxValue(unsigned numBits) { @@ -208,13 +209,14 @@ return getSignedMinValue(BitWidth); } - /// Get the all-ones value. - /// - /// \returns the all-ones value for an APInt of the specified bit-width. - static APInt getAllOnesValue(unsigned numBits) { + /// Return an APInt of a specified width with all bits set. + static APInt getAllOnes(unsigned numBits) { return APInt(numBits, WORDTYPE_MAX, true); } + /// NOTE: This is soft-deprecated. Please use `getAllOnes()` instead. + static APInt getAllOnesValue(unsigned numBits) { return getAllOnes(numBits); } + /// Return an APInt with exactly one bit set in the result. static APInt getOneBitSet(unsigned numBits, unsigned BitNo) { APInt Res(numBits, 0); @@ -340,42 +342,46 @@ /// that 0 is not a positive value. /// /// \returns true if this APInt is positive. - bool isStrictlyPositive() const { return isNonNegative() && !isNullValue(); } + bool isStrictlyPositive() const { return isNonNegative() && !isZero(); } /// Determine if this APInt Value is non-positive (<= 0). /// /// \returns true if this APInt is non-positive. bool isNonPositive() const { return !isStrictlyPositive(); } - /// Determine if all bits are set - /// - /// This checks to see if the value has all bits of the APInt are set or not. - bool isAllOnesValue() const { + /// Determine if all bits are set. + bool isAllOnes() const { if (isSingleWord()) return U.VAL == WORDTYPE_MAX >> (APINT_BITS_PER_WORD - BitWidth); return countTrailingOnesSlowCase() == BitWidth; } - /// Determine if all bits are clear - /// - /// This checks to see if the value has all bits of the APInt are clear or - /// not. - bool isNullValue() const { return !*this; } + /// NOTE: This is soft-deprecated. Please use `isAllOnes()` instead. + bool isAllOnesValue() const { return isAllOnes(); } + + /// Determine if this value is zero, i.e. all bits are clear. + bool isZero() const { return !*this; } + + /// NOTE: This is soft-deprecated. Please use `isZero()` instead. + bool isNullValue() const { return isZero(); } /// Determine if this is a value of 1. /// /// This checks to see if the value of this APInt is one. - bool isOneValue() const { + bool isOne() const { if (isSingleWord()) return U.VAL == 1; return countLeadingZerosSlowCase() == BitWidth - 1; } + /// NOTE: This is soft-deprecated. Please use `isOne()` instead. + bool isOneValue() const { return isOne(); } + /// Determine if this is the largest unsigned value. /// /// This checks to see if the value of this APInt is the maximum unsigned /// value for the APInt's bit width. - bool isMaxValue() const { return isAllOnesValue(); } + bool isMaxValue() const { return isAllOnes(); } /// Determine if this is the largest signed value. /// @@ -391,7 +397,7 @@ /// /// This checks to see if the value of this APInt is the minimum unsigned /// value for the APInt's bit width. - bool isMinValue() const { return isNullValue(); } + bool isMinValue() const { return isZero(); } /// Determine if this is the smallest signed value. /// diff --git a/llvm/include/llvm/ADT/APSInt.h b/llvm/include/llvm/ADT/APSInt.h --- a/llvm/include/llvm/ADT/APSInt.h +++ b/llvm/include/llvm/ADT/APSInt.h @@ -58,7 +58,7 @@ /// that 0 is not a positive value. /// /// \returns true if this APSInt is positive. - bool isStrictlyPositive() const { return isNonNegative() && !isNullValue(); } + bool isStrictlyPositive() const { return isNonNegative() && !isZero(); } APSInt &operator=(APInt RHS) { // Retain our current sign. diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -697,7 +697,7 @@ bool Extract) { auto *Ty = cast(InTy); - APInt DemandedElts = APInt::getAllOnesValue(Ty->getNumElements()); + APInt DemandedElts = APInt::getAllOnes(Ty->getNumElements()); return thisT()->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract); } diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -127,7 +127,7 @@ return false; LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLT SrcTy = MRI.getType(SrcReg); - APInt MaskVal = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits()); + APInt MaskVal = APInt::getAllOnes(SrcTy.getScalarSizeInBits()); auto Mask = Builder.buildConstant( DstTy, MaskVal.zext(DstTy.getScalarSizeInBits())); if (SextSrc && (DstTy != MRI.getType(SextSrc))) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -621,8 +621,8 @@ SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget = false, bool IsOpaque = false) { - return getConstant(APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, - VT, IsTarget, IsOpaque); + return getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT, + IsTarget, IsOpaque); } SDValue getConstant(const ConstantInt &Val, const SDLoc &DL, EVT VT, diff --git a/llvm/include/llvm/IR/Constants.h b/llvm/include/llvm/IR/Constants.h --- a/llvm/include/llvm/IR/Constants.h +++ b/llvm/include/llvm/IR/Constants.h @@ -191,13 +191,13 @@ /// This is just a convenience method to make client code smaller for a /// common code. It also correctly performs the comparison without the /// potential for an assertion from getZExtValue(). - bool isZero() const { return Val.isNullValue(); } + bool isZero() const { return Val.isZero(); } /// This is just a convenience method to make client code smaller for a /// common case. It also correctly performs the comparison without the /// potential for an assertion from getZExtValue(). /// Determine if the value is one. - bool isOne() const { return Val.isOneValue(); } + bool isOne() const { return Val.isOne(); } /// This function will return true iff every bit in this constant is set /// to true. diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -515,7 +515,7 @@ } struct is_zero_int { - bool isValue(const APInt &C) { return C.isNullValue(); } + bool isValue(const APInt &C) { return C.isZero(); } }; /// Match an integer 0 or a vector with all elements equal to 0. /// For vectors, this includes constants with undefined elements. diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h --- a/llvm/include/llvm/Support/KnownBits.h +++ b/llvm/include/llvm/Support/KnownBits.h @@ -60,7 +60,7 @@ } /// Returns true if we don't know any bits. - bool isUnknown() const { return Zero.isNullValue() && One.isNullValue(); } + bool isUnknown() const { return Zero.isZero() && One.isZero(); } /// Resets the known state of all bits. void resetAll() { @@ -99,10 +99,12 @@ bool isNonNegative() const { return Zero.isSignBitSet(); } /// Returns true if this value is known to be non-zero. - bool isNonZero() const { return !One.isNullValue(); } + bool isNonZero() const { return !One.isZero(); } /// Returns true if this value is known to be positive. - bool isStrictlyPositive() const { return Zero.isSignBitSet() && !One.isNullValue(); } + bool isStrictlyPositive() const { + return Zero.isSignBitSet() && !One.isZero(); + } /// Make this value negative. void makeNegative() { diff --git a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h --- a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h +++ b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h @@ -165,7 +165,7 @@ switch (Pred) { case ICmpInst::ICMP_SLT: // True if LHS s< 0 TrueIfSigned = true; - return RHS.isNullValue(); + return RHS.isZero(); case ICmpInst::ICMP_SLE: // True if LHS s<= -1 TrueIfSigned = true; return RHS.isAllOnesValue(); @@ -174,7 +174,7 @@ return RHS.isAllOnesValue(); case ICmpInst::ICMP_SGE: // True if LHS s>= 0 TrueIfSigned = false; - return RHS.isNullValue(); + return RHS.isZero(); case ICmpInst::ICMP_UGT: // True if LHS u> RHS and RHS == sign-bit-mask - 1 TrueIfSigned = true; diff --git a/llvm/lib/Analysis/DemandedBits.cpp b/llvm/lib/Analysis/DemandedBits.cpp --- a/llvm/lib/Analysis/DemandedBits.cpp +++ b/llvm/lib/Analysis/DemandedBits.cpp @@ -362,7 +362,7 @@ if (Instruction *J = dyn_cast(OI)) { Type *T = J->getType(); if (T->isIntOrIntVectorTy()) - AliveBits[J] = APInt::getAllOnesValue(T->getScalarSizeInBits()); + AliveBits[J] = APInt::getAllOnes(T->getScalarSizeInBits()); else Visited.insert(J); Worklist.insert(J); @@ -407,7 +407,7 @@ Type *T = OI->getType(); if (T->isIntOrIntVectorTy()) { unsigned BitWidth = T->getScalarSizeInBits(); - APInt AB = APInt::getAllOnesValue(BitWidth); + APInt AB = APInt::getAllOnes(BitWidth); if (InputIsKnownDead) { AB = APInt(BitWidth, 0); } else { @@ -417,7 +417,7 @@ Known, Known2, KnownBitsComputed); // Keep track of uses which have no demanded bits. - if (AB.isNullValue()) + if (AB.isZero()) DeadUses.insert(&OI); else DeadUses.erase(&OI); @@ -448,8 +448,7 @@ return Found->second; const DataLayout &DL = I->getModule()->getDataLayout(); - return APInt::getAllOnesValue( - DL.getTypeSizeInBits(I->getType()->getScalarType())); + return APInt::getAllOnes(DL.getTypeSizeInBits(I->getType()->getScalarType())); } APInt DemandedBits::getDemandedBits(Use *U) { @@ -461,7 +460,7 @@ // We only track integer uses, everything else produces a mask with all bits // set if (!T->isIntOrIntVectorTy()) - return APInt::getAllOnesValue(BitWidth); + return APInt::getAllOnes(BitWidth); if (isUseDead(U)) return APInt(BitWidth, 0); @@ -469,7 +468,7 @@ performAnalysis(); APInt AOut = getDemandedBits(UserI); - APInt AB = APInt::getAllOnesValue(BitWidth); + APInt AB = APInt::getAllOnes(BitWidth); KnownBits Known, Known2; bool KnownBitsComputed = false; @@ -504,7 +503,7 @@ // is dead. These uses might not be explicitly present in the DeadUses map. if (UserI->getType()->isIntOrIntVectorTy()) { auto Found = AliveBits.find(UserI); - if (Found != AliveBits.end() && Found->second.isNullValue()) + if (Found != AliveBits.end() && Found->second.isZero()) return true; } diff --git a/llvm/lib/Analysis/DependenceAnalysis.cpp b/llvm/lib/Analysis/DependenceAnalysis.cpp --- a/llvm/lib/Analysis/DependenceAnalysis.cpp +++ b/llvm/lib/Analysis/DependenceAnalysis.cpp @@ -2325,7 +2325,7 @@ LLVM_DEBUG(dbgs() << "starting gcd\n"); ++GCDapplications; unsigned BitWidth = SE->getTypeSizeInBits(Src->getType()); - APInt RunningGCD = APInt::getNullValue(BitWidth); + APInt RunningGCD = APInt::getZero(BitWidth); // Examine Src coefficients. // Compute running GCD and record source constant. @@ -2365,7 +2365,7 @@ } const SCEV *DstConst = Coefficients; - APInt ExtraGCD = APInt::getNullValue(BitWidth); + APInt ExtraGCD = APInt::getZero(BitWidth); const SCEV *Delta = SE->getMinusSCEV(DstConst, SrcConst); LLVM_DEBUG(dbgs() << " Delta = " << *Delta << "\n"); const SCEVConstant *Constant = dyn_cast(Delta); diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -1370,7 +1370,7 @@ // Or could we skip the getPointerSizeInBits call completely? As far as I can // see the ZeroOffset is used as a dummy value, so we can probably use any // bit width for the ZeroOffset? - APInt ZeroOffset = APInt::getNullValue(DL.getPointerSizeInBits(0)); + APInt ZeroOffset = APInt::getZero(DL.getPointerSizeInBits(0)); bool CheckSROA = I.getType()->isPointerTy(); // Track the constant or pointer with constant offset we've seen so far. @@ -2462,7 +2462,7 @@ unsigned AS = V->getType()->getPointerAddressSpace(); unsigned IntPtrWidth = DL.getIndexSizeInBits(AS); - APInt Offset = APInt::getNullValue(IntPtrWidth); + APInt Offset = APInt::getZero(IntPtrWidth); // Even though we don't look through PHI nodes, we could be called on an // instruction in an unreachable block, which may be on a cycle. diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -699,7 +699,7 @@ assert(V->getType()->isPtrOrPtrVectorTy()); Type *IntIdxTy = DL.getIndexType(V->getType())->getScalarType(); - APInt Offset = APInt::getNullValue(IntIdxTy->getIntegerBitWidth()); + APInt Offset = APInt::getZero(IntIdxTy->getIntegerBitWidth()); V = V->stripAndAccumulateConstantOffsets(DL, Offset, AllowNonInbounds); // As that strip may trace through `addrspacecast`, need to sext or trunc @@ -1765,7 +1765,7 @@ if (match(Cmp0->getOperand(1), m_APInt(C))) MinMaxC = HasNotOp ? ~*C : *C; else if (isa(Cmp0->getOperand(1))) - MinMaxC = APInt::getNullValue(8); + MinMaxC = APInt::getZero(8); else return nullptr; diff --git a/llvm/lib/Analysis/LazyValueInfo.cpp b/llvm/lib/Analysis/LazyValueInfo.cpp --- a/llvm/lib/Analysis/LazyValueInfo.cpp +++ b/llvm/lib/Analysis/LazyValueInfo.cpp @@ -846,7 +846,7 @@ } if (SPR.Flavor == SPF_NABS) { - ConstantRange Zero(APInt::getNullValue(TrueCR.getBitWidth())); + ConstantRange Zero(APInt::getZero(TrueCR.getBitWidth())); if (LHS == SI->getTrueValue()) return ValueLatticeElement::getRange( Zero.sub(TrueCR.abs()), FalseVal.isConstantRangeIncludingUndef()); @@ -1122,7 +1122,7 @@ unsigned BitWidth = Ty->getIntegerBitWidth(); return ValueLatticeElement::getRange(ConstantRange::getNonEmpty( APInt::getOneBitSet(BitWidth, Mask->countTrailingZeros()), - APInt::getNullValue(BitWidth))); + APInt::getZero(BitWidth))); } } diff --git a/llvm/lib/Analysis/MemoryBuiltins.cpp b/llvm/lib/Analysis/MemoryBuiltins.cpp --- a/llvm/lib/Analysis/MemoryBuiltins.cpp +++ b/llvm/lib/Analysis/MemoryBuiltins.cpp @@ -610,7 +610,7 @@ SizeOffsetType ObjectSizeOffsetVisitor::compute(Value *V) { IntTyBits = DL.getIndexTypeSizeInBits(V->getType()); - Zero = APInt::getNullValue(IntTyBits); + Zero = APInt::getZero(IntTyBits); V = V->stripPointerCasts(); if (Instruction *I = dyn_cast(V)) { diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp --- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp +++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp @@ -167,7 +167,7 @@ if (Overflow) return R; } - R = ConstantRange(APInt::getNullValue(PointerSize), APSize); + R = ConstantRange(APInt::getZero(PointerSize), APSize); assert(!isUnsafe(R)); return R; } @@ -297,8 +297,8 @@ APInt APSize(PointerSize, Size.getFixedSize(), true); if (APSize.isNegative()) return UnknownRange; - return getAccessRange( - Addr, Base, ConstantRange(APInt::getNullValue(PointerSize), APSize)); + return getAccessRange(Addr, Base, + ConstantRange(APInt::getZero(PointerSize), APSize)); } ConstantRange StackSafetyLocalAnalysis::getMemIntrinsicAccessRange( @@ -321,8 +321,7 @@ if (Sizes.getUpper().isNegative() || isUnsafe(Sizes)) return UnknownRange; Sizes = Sizes.sextOrTrunc(PointerSize); - ConstantRange SizeRange(APInt::getNullValue(PointerSize), - Sizes.getUpper() - 1); + ConstantRange SizeRange(APInt::getZero(PointerSize), Sizes.getUpper() - 1); return getAccessRange(U, Base, SizeRange); } diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -165,7 +165,7 @@ int NumElts = cast(Shuf->getOperand(0)->getType())->getNumElements(); int NumMaskElts = cast(Shuf->getType())->getNumElements(); - DemandedLHS = DemandedRHS = APInt::getNullValue(NumElts); + DemandedLHS = DemandedRHS = APInt::getZero(NumElts); if (DemandedElts.isNullValue()) return true; // Simple case of a shuffle with zeroinitializer. @@ -206,7 +206,7 @@ auto *FVTy = dyn_cast(V->getType()); APInt DemandedElts = - FVTy ? APInt::getAllOnesValue(FVTy->getNumElements()) : APInt(1, 1); + FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1); computeKnownBits(V, DemandedElts, Known, Depth, Q); } @@ -378,7 +378,7 @@ auto *FVTy = dyn_cast(V->getType()); APInt DemandedElts = - FVTy ? APInt::getAllOnesValue(FVTy->getNumElements()) : APInt(1, 1); + FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1); return ComputeNumSignBits(V, DemandedElts, Depth, Q); } @@ -582,7 +582,7 @@ return false; ConstantRange TrueValues = ConstantRange::makeExactICmpRegion(Pred, *C); - return !TrueValues.contains(APInt::getNullValue(C->getBitWidth())); + return !TrueValues.contains(APInt::getZero(C->getBitWidth())); } static bool isKnownNonZeroFromAssume(const Value *V, const Query &Q) { @@ -1210,7 +1210,7 @@ // (dependent on endian) to form the full result of known bits. unsigned NumElts = DemandedElts.getBitWidth(); unsigned SubScale = BitWidth / SubBitWidth; - APInt SubDemandedElts = APInt::getNullValue(NumElts * SubScale); + APInt SubDemandedElts = APInt::getZero(NumElts * SubScale); for (unsigned i = 0; i != NumElts; ++i) { if (DemandedElts[i]) SubDemandedElts.setBit(i * SubScale); @@ -1763,7 +1763,7 @@ break; } unsigned NumElts = cast(Vec->getType())->getNumElements(); - APInt DemandedVecElts = APInt::getAllOnesValue(NumElts); + APInt DemandedVecElts = APInt::getAllOnes(NumElts); if (CIdx && CIdx->getValue().ult(NumElts)) DemandedVecElts = APInt::getOneBitSet(NumElts, CIdx->getZExtValue()); computeKnownBits(Vec, DemandedVecElts, Known, Depth + 1, Q); @@ -2532,7 +2532,7 @@ auto *CIdx = dyn_cast(Idx); if (auto *VecTy = dyn_cast(Vec->getType())) { unsigned NumElts = VecTy->getNumElements(); - APInt DemandedVecElts = APInt::getAllOnesValue(NumElts); + APInt DemandedVecElts = APInt::getAllOnes(NumElts); if (CIdx && CIdx->getValue().ult(NumElts)) DemandedVecElts = APInt::getOneBitSet(NumElts, CIdx->getZExtValue()); return isKnownNonZero(Vec, DemandedVecElts, Depth, Q); @@ -2559,7 +2559,7 @@ auto *FVTy = dyn_cast(V->getType()); APInt DemandedElts = - FVTy ? APInt::getAllOnesValue(FVTy->getNumElements()) : APInt(1, 1); + FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1); return isKnownNonZero(V, DemandedElts, Depth, Q); } @@ -6746,7 +6746,7 @@ case Instruction::LShr: if (match(BO.getOperand(1), m_APInt(C)) && C->ult(Width)) { // 'lshr x, C' produces [0, UINT_MAX >> C]. - Upper = APInt::getAllOnesValue(Width).lshr(*C) + 1; + Upper = APInt::getAllOnes(Width).lshr(*C) + 1; } else if (match(BO.getOperand(0), m_APInt(C))) { // 'lshr C, x' produces [C >> (Width-1), C]. unsigned ShiftAmount = Width - 1; @@ -6956,7 +6956,7 @@ // If the negation part of the abs (in RHS) has the NSW flag, // then the result of abs(X) is [0..SIGNED_MAX], // otherwise it is [0..SIGNED_MIN], as -SIGNED_MIN == SIGNED_MIN. - Lower = APInt::getNullValue(BitWidth); + Lower = APInt::getZero(BitWidth); if (match(RHS, m_Neg(m_Specific(LHS))) && IIQ.hasNoSignedWrap(cast(RHS))) Upper = APInt::getSignedMaxValue(BitWidth) + 1; diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -946,7 +946,7 @@ const unsigned VWidth = cast(Mask->getType())->getNumElements(); - APInt DemandedElts = APInt::getAllOnesValue(VWidth); + APInt DemandedElts = APInt::getAllOnes(VWidth); if (auto *CV = dyn_cast(Mask)) for (unsigned i = 0; i < VWidth; i++) if (CV->getAggregateElement(i)->isNullValue()) diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -2652,14 +2652,14 @@ // // Check if we can replace AndDst with the LHS of the G_AND if (canReplaceReg(AndDst, LHS, MRI) && - (LHSBits.Zero | RHSBits.One).isAllOnesValue()) { + (LHSBits.Zero | RHSBits.One).isAllOnes()) { Replacement = LHS; return true; } // Check if we can replace AndDst with the RHS of the G_AND if (canReplaceReg(AndDst, RHS, MRI) && - (LHSBits.One | RHSBits.Zero).isAllOnesValue()) { + (LHSBits.One | RHSBits.Zero).isAllOnes()) { Replacement = RHS; return true; } diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp --- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -57,7 +57,7 @@ KnownBits GISelKnownBits::getKnownBits(Register R) { const LLT Ty = MRI.getType(R); APInt DemandedElts = - Ty.isVector() ? APInt::getAllOnesValue(Ty.getNumElements()) : APInt(1, 1); + Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); return getKnownBits(R, DemandedElts); } @@ -198,8 +198,8 @@ case TargetOpcode::COPY: case TargetOpcode::G_PHI: case TargetOpcode::PHI: { - Known.One = APInt::getAllOnesValue(BitWidth); - Known.Zero = APInt::getAllOnesValue(BitWidth); + Known.One = APInt::getAllOnes(BitWidth); + Known.Zero = APInt::getAllOnes(BitWidth); // Destination registers should not have subregisters at this // point of the pipeline, otherwise the main live-range will be // defined more than once, which is against SSA. @@ -688,9 +688,8 @@ unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned Depth) { LLT Ty = MRI.getType(R); - APInt DemandedElts = Ty.isVector() - ? APInt::getAllOnesValue(Ty.getNumElements()) - : APInt(1, 1); + APInt DemandedElts = + Ty.isVector() ? APInt::getAllOnes(Ty.getNumElements()) : APInt(1, 1); return computeNumSignBits(R, DemandedElts, Depth); } diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -2670,7 +2670,7 @@ // Now figure out the amount we need to shift to get the target bits. auto OffsetMask = B.buildConstant( - IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); + IdxTy, ~(APInt::getAllOnes(IdxTy.getSizeInBits()) << Log2EltRatio)); auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); return B.buildShl(IdxTy, OffsetIdx, B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); @@ -6287,7 +6287,7 @@ APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() : APFloat::IEEEdouble(), - APInt::getNullValue(SrcTy.getSizeInBits())); + APInt::getZero(SrcTy.getSizeInBits())); TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); diff --git a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp --- a/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp +++ b/llvm/lib/CodeGen/InterleavedLoadCombinePass.cpp @@ -313,7 +313,7 @@ } // Multiplying by zero removes the coefficient B and defines all bits. - if (C.isNullValue()) { + if (C.isZero()) { ErrorMSBs = 0; deleteB(); } @@ -464,7 +464,7 @@ return *this; } - if (C.isNullValue()) + if (C.isZero()) return *this; // Test if the result will be zero @@ -571,7 +571,7 @@ bool isProvenEqualTo(const Polynomial &o) { // Subtract both polynomials and test if it is fully defined and zero. Polynomial r = *this - o; - return (r.ErrorMSBs == 0) && (!r.isFirstOrder()) && (r.A.isNullValue()); + return (r.ErrorMSBs == 0) && (!r.isFirstOrder()) && (r.A.isZero()); } /// Print the polynomial into a stream. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -319,7 +319,7 @@ /// If so, return true. bool SimplifyDemandedBits(SDValue Op) { unsigned BitWidth = Op.getScalarValueSizeInBits(); - APInt DemandedBits = APInt::getAllOnesValue(BitWidth); + APInt DemandedBits = APInt::getAllOnes(BitWidth); return SimplifyDemandedBits(Op, DemandedBits); } @@ -345,7 +345,7 @@ return false; unsigned NumElts = Op.getValueType().getVectorNumElements(); - APInt DemandedElts = APInt::getAllOnesValue(NumElts); + APInt DemandedElts = APInt::getAllOnes(NumElts); return SimplifyDemandedVectorElts(Op, DemandedElts); } @@ -5640,11 +5640,11 @@ // fold (and x, 0) -> 0, vector edition if (ISD::isConstantSplatVectorAllZeros(N0.getNode())) // do not return N0, because undef node may exist in N0 - return DAG.getConstant(APInt::getNullValue(N0.getScalarValueSizeInBits()), + return DAG.getConstant(APInt::getZero(N0.getScalarValueSizeInBits()), SDLoc(N), N0.getValueType()); if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) // do not return N1, because undef node may exist in N1 - return DAG.getConstant(APInt::getNullValue(N1.getScalarValueSizeInBits()), + return DAG.getConstant(APInt::getZero(N1.getScalarValueSizeInBits()), SDLoc(N), N1.getValueType()); // fold (and x, -1) -> x, vector edition @@ -5695,8 +5695,7 @@ // if (and x, c) is known to be zero, return 0 unsigned BitWidth = VT.getScalarSizeInBits(); - if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), - APInt::getAllOnesValue(BitWidth))) + if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(BitWidth))) return DAG.getConstant(0, SDLoc(N), VT); if (SDValue NewSel = foldBinOpIntoSelect(N)) @@ -5758,7 +5757,7 @@ // Get the constant (if applicable) the zero'th operand is being ANDed with. // This can be a pure constant or a vector splat, in which case we treat the // vector as a scalar and use the splat value. - APInt Constant = APInt::getNullValue(1); + APInt Constant = APInt::getZero(1); if (const ConstantSDNode *C = dyn_cast(N1)) { Constant = C->getAPIntValue(); } else if (BuildVectorSDNode *Vector = dyn_cast(N1)) { @@ -5789,7 +5788,7 @@ // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value. if ((SplatBitSize % EltBitWidth) == 0) { - Constant = APInt::getAllOnesValue(EltBitWidth); + Constant = APInt::getAllOnes(EltBitWidth); for (unsigned i = 0, n = (SplatBitSize / EltBitWidth); i < n; ++i) Constant &= SplatValue.extractBits(EltBitWidth, i * EltBitWidth); } @@ -7915,7 +7914,7 @@ // shift has been simplified to undef. uint64_t ShiftAmt = ShiftC->getLimitedValue(); if (ShiftAmt < BitWidth) { - APInt Ones = APInt::getAllOnesValue(BitWidth); + APInt Ones = APInt::getAllOnes(BitWidth); Ones = N0Opcode == ISD::SHL ? Ones.shl(ShiftAmt) : Ones.lshr(ShiftAmt); if (XorC->getAPIntValue() == Ones) { // If the xor constant is a shifted -1, do a 'not' before the shift: @@ -8271,8 +8270,7 @@ return NewSel; // if (shl x, c) is known to be zero, return 0 - if (DAG.MaskedValueIsZero(SDValue(N, 0), - APInt::getAllOnesValue(OpSizeInBits))) + if (DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) return DAG.getConstant(0, SDLoc(N), VT); // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). @@ -8790,8 +8788,8 @@ return NewSel; // if (srl x, c) is known to be zero, return 0 - if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), - APInt::getAllOnesValue(OpSizeInBits))) + if (N1C && + DAG.MaskedValueIsZero(SDValue(N, 0), APInt::getAllOnes(OpSizeInBits))) return DAG.getConstant(0, SDLoc(N), VT); // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) @@ -16733,7 +16731,7 @@ unsigned BitWidth = N1.getValueSizeInBits(); APInt Imm = cast(N1)->getAPIntValue(); if (Opc == ISD::AND) - Imm ^= APInt::getAllOnesValue(BitWidth); + Imm ^= APInt::getAllOnes(BitWidth); if (Imm == 0 || Imm.isAllOnesValue()) return SDValue(); unsigned ShAmt = Imm.countTrailingZeros(); @@ -16761,7 +16759,7 @@ if ((Imm & Mask) == Imm) { APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); if (Opc == ISD::AND) - NewImm ^= APInt::getAllOnesValue(NewBW); + NewImm ^= APInt::getAllOnes(NewBW); uint64_t PtrOff = ShAmt / 8; // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. @@ -18911,7 +18909,7 @@ Use->getOperand(0) == VecOp && isa(Use->getOperand(1)); })) { - APInt DemandedElts = APInt::getNullValue(NumElts); + APInt DemandedElts = APInt::getZero(NumElts); for (SDNode *Use : VecOp->uses()) { auto *CstElt = cast(Use->getOperand(1)); if (CstElt->getAPIntValue().ult(NumElts)) @@ -18924,7 +18922,7 @@ AddToWorklist(N); return SDValue(N, 0); } - APInt DemandedBits = APInt::getAllOnesValue(VecEltBitWidth); + APInt DemandedBits = APInt::getAllOnes(VecEltBitWidth); if (SimplifyDemandedBits(VecOp, DemandedBits, DemandedElts, true)) { // We simplified the vector operand of this extract element. If this // extract is not dead, visit it again so it is folded properly. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3240,9 +3240,9 @@ assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) && "Don't know how to expand this subtraction!"); - Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), - DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, - VT)); + Tmp1 = DAG.getNode( + ISD::XOR, dl, VT, Node->getOperand(1), + DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT)); Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT)); Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); break; diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -257,7 +257,7 @@ unsigned Size = NVT.getSizeInBits(); // Mask = ~(1 << (Size-1)) - APInt API = APInt::getAllOnesValue(Size); + APInt API = APInt::getAllOnes(Size); API.clearBit(Size - 1); SDValue Mask = DAG.getConstant(API, SDLoc(N), NVT); SDValue Op = GetSoftenedFloat(N->getOperand(0)); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -832,7 +832,7 @@ unsigned NewBits = PromotedType.getScalarSizeInBits(); if (Opcode == ISD::UADDSAT) { - APInt MaxVal = APInt::getAllOnesValue(OldBits).zext(NewBits); + APInt MaxVal = APInt::getAllOnes(OldBits).zext(NewBits); SDValue SatMax = DAG.getConstant(MaxVal, dl, PromotedType); SDValue Add = DAG.getNode(ISD::ADD, dl, PromotedType, Op1Promoted, Op2Promoted); @@ -3698,7 +3698,7 @@ // Saturate to signed maximum. APInt MaxHi = APInt::getSignedMaxValue(NVTSize); - APInt MaxLo = APInt::getAllOnesValue(NVTSize); + APInt MaxLo = APInt::getAllOnes(NVTSize); Hi = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxHi, dl, NVT), Hi); Lo = DAG.getSelect(dl, NVT, SatMax, DAG.getConstant(MaxLo, dl, NVT), Lo); // Saturate to signed minimum. diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -943,10 +943,10 @@ // What is the size of each element in the vector mask. EVT BitTy = MaskTy.getScalarType(); - Mask = DAG.getSelect(DL, BitTy, Mask, - DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, - BitTy), - DAG.getConstant(0, DL, BitTy)); + Mask = DAG.getSelect( + DL, BitTy, Mask, + DAG.getConstant(APInt::getAllOnes(BitTy.getSizeInBits()), DL, BitTy), + DAG.getConstant(0, DL, BitTy)); // Broadcast the mask so that the entire vector is all one or all zero. if (VT.isFixedLengthVector()) @@ -960,8 +960,8 @@ Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); - SDValue AllOnes = DAG.getConstant( - APInt::getAllOnesValue(BitTy.getSizeInBits()), DL, MaskTy); + SDValue AllOnes = + DAG.getConstant(APInt::getAllOnes(BitTy.getSizeInBits()), DL, MaskTy); SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); @@ -1207,8 +1207,8 @@ Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); - SDValue AllOnes = DAG.getConstant( - APInt::getAllOnesValue(VT.getScalarSizeInBits()), DL, VT); + SDValue AllOnes = + DAG.getConstant(APInt::getAllOnes(VT.getScalarSizeInBits()), DL, VT); SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); @@ -1501,10 +1501,10 @@ if (Node->getOpcode() == ISD::STRICT_FSETCC || Node->getOpcode() == ISD::STRICT_FSETCCS) - ScalarResult = DAG.getSelect(dl, EltVT, ScalarResult, - DAG.getConstant(APInt::getAllOnesValue - (EltVT.getSizeInBits()), dl, EltVT), - DAG.getConstant(0, dl, EltVT)); + ScalarResult = DAG.getSelect( + dl, EltVT, ScalarResult, + DAG.getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), dl, EltVT), + DAG.getConstant(0, dl, EltVT)); OpValues.push_back(ScalarResult); OpChains.push_back(ScalarChain); @@ -1536,10 +1536,10 @@ TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), TmpEltVT), LHSElem, RHSElem, CC); - Ops[i] = DAG.getSelect(dl, EltVT, Ops[i], - DAG.getConstant(APInt::getAllOnesValue - (EltVT.getSizeInBits()), dl, EltVT), - DAG.getConstant(0, dl, EltVT)); + Ops[i] = DAG.getSelect( + dl, EltVT, Ops[i], + DAG.getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), dl, EltVT), + DAG.getConstant(0, dl, EltVT)); } return DAG.getBuildVector(VT, dl, Ops); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1349,7 +1349,7 @@ SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { EVT EltVT = VT.getScalarType(); SDValue NegOne = - getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), DL, VT); + getConstant(APInt::getAllOnes(EltVT.getSizeInBits()), DL, VT); return getNode(ISD::XOR, DL, VT, Val, NegOne); } @@ -2408,7 +2408,7 @@ return SDValue(); APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return GetDemandedBits(V, DemandedBits, DemandedElts); } @@ -2503,7 +2503,7 @@ switch (V.getOpcode()) { case ISD::SPLAT_VECTOR: UndefElts = V.getOperand(0).isUndef() - ? APInt::getAllOnesValue(DemandedElts.getBitWidth()) + ? APInt::getAllOnes(DemandedElts.getBitWidth()) : APInt(DemandedElts.getBitWidth(), 0); return true; case ISD::ADD: @@ -2535,7 +2535,7 @@ unsigned NumElts = VT.getVectorNumElements(); assert(NumElts == DemandedElts.getBitWidth() && "Vector size mismatch"); - UndefElts = APInt::getNullValue(NumElts); + UndefElts = APInt::getZero(NumElts); switch (V.getOpcode()) { case ISD::BUILD_VECTOR: { @@ -2604,7 +2604,7 @@ // For now we don't support this with scalable vectors. if (!VT.isScalableVector()) - DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); return isSplatValue(V, DemandedElts, UndefElts) && (AllowUndefs || !UndefElts); } @@ -2620,7 +2620,7 @@ APInt DemandedElts; if (!VT.isScalableVector()) - DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); if (isSplatValue(V, DemandedElts, UndefElts)) { if (VT.isScalableVector()) { @@ -2768,7 +2768,7 @@ } APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return computeKnownBits(Op, DemandedElts, Depth); } @@ -2906,7 +2906,7 @@ unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); APInt DemandedSrcElts = DemandedElts; - DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); + DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); Known.One.setAllBits(); Known.Zero.setAllBits(); @@ -3443,7 +3443,7 @@ // If we know the element index, just demand that vector element, else for // an unknown element index, ignore DemandedElts and demand them all. - APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts); + APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts); auto *ConstEltNo = dyn_cast(EltNo); if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts)) DemandedSrcElts = @@ -3697,7 +3697,7 @@ return 1; APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return ComputeNumSignBits(Op, DemandedElts, Depth); } @@ -4114,7 +4114,7 @@ // If we know the element index, just demand that vector element, else for // an unknown element index, ignore DemandedElts and demand them all. - APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts); + APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts); auto *ConstEltNo = dyn_cast(EltNo); if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts)) DemandedSrcElts = @@ -4160,7 +4160,7 @@ unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); APInt DemandedSrcElts = DemandedElts; - DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); + DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); Tmp = std::numeric_limits::max(); if (!!DemandedSubElts) { @@ -4294,7 +4294,7 @@ return false; APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return isGuaranteedNotToBeUndefOrPoison(Op, DemandedElts, PoisonOnly, Depth); } @@ -4720,7 +4720,7 @@ case ISD::UINT_TO_FP: case ISD::SINT_TO_FP: { APFloat apf(EVTToAPFloatSemantics(VT), - APInt::getNullValue(VT.getSizeInBits())); + APInt::getZero(VT.getSizeInBits())); (void)apf.convertFromAPInt(Val, Opcode==ISD::SINT_TO_FP, APFloat::rmNearestTiesToEven); @@ -10799,7 +10799,7 @@ } SDValue BuildVectorSDNode::getSplatValue(BitVector *UndefElements) const { - APInt DemandedElts = APInt::getAllOnesValue(getNumOperands()); + APInt DemandedElts = APInt::getAllOnes(getNumOperands()); return getSplatValue(DemandedElts, UndefElements); } @@ -10851,7 +10851,7 @@ bool BuildVectorSDNode::getRepeatedSequence(SmallVectorImpl &Sequence, BitVector *UndefElements) const { - APInt DemandedElts = APInt::getAllOnesValue(getNumOperands()); + APInt DemandedElts = APInt::getAllOnes(getNumOperands()); return getRepeatedSequence(DemandedElts, Sequence, UndefElements); } diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -537,7 +537,7 @@ TargetLoweringOpt &TLO) const { EVT VT = Op.getValueType(); APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return ShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO); } @@ -621,7 +621,7 @@ } APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, Known, TLO, Depth, AssumeSingleUse); @@ -667,8 +667,8 @@ DAG.getDataLayout().isLittleEndian()) { unsigned Scale = NumDstEltBits / NumSrcEltBits; unsigned NumSrcElts = SrcVT.getVectorNumElements(); - APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); - APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); + APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); + APInt DemandedSrcElts = APInt::getZero(NumSrcElts); for (unsigned i = 0; i != Scale; ++i) { unsigned Offset = i * NumSrcEltBits; APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); @@ -690,8 +690,8 @@ DAG.getDataLayout().isLittleEndian()) { unsigned Scale = NumSrcEltBits / NumDstEltBits; unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; - APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); - APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); + APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); + APInt DemandedSrcElts = APInt::getZero(NumSrcElts); for (unsigned i = 0; i != NumElts; ++i) if (DemandedElts[i]) { unsigned Offset = (i % Scale) * NumDstEltBits; @@ -874,7 +874,7 @@ unsigned Depth) const { EVT VT = Op.getValueType(); APInt DemandedElts = VT.isVector() - ? APInt::getAllOnesValue(VT.getVectorNumElements()) + ? APInt::getAllOnes(VT.getVectorNumElements()) : APInt(1, 1); return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, Depth); @@ -883,7 +883,7 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedVectorElts( SDValue Op, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const { - APInt DemandedBits = APInt::getAllOnesValue(Op.getScalarValueSizeInBits()); + APInt DemandedBits = APInt::getAllOnes(Op.getScalarValueSizeInBits()); return SimplifyMultipleUseDemandedBits(Op, DemandedBits, DemandedElts, DAG, Depth); } @@ -950,8 +950,8 @@ } // If this is the root being simplified, allow it to have multiple uses, // just set the DemandedBits/Elts to all bits. - DemandedBits = APInt::getAllOnesValue(BitWidth); - DemandedElts = APInt::getAllOnesValue(NumElts); + DemandedBits = APInt::getAllOnes(BitWidth); + DemandedElts = APInt::getAllOnes(NumElts); } else if (OriginalDemandedBits == 0 || OriginalDemandedElts == 0) { // Not demanding any bits/elts from Op. return TLO.CombineTo(Op, TLO.DAG.getUNDEF(VT)); @@ -1046,7 +1046,7 @@ unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); APInt DemandedSrcElts = DemandedElts; - DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); + DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); KnownBits KnownSub, KnownSrc; if (SimplifyDemandedBits(Sub, DemandedBits, DemandedSubElts, KnownSub, TLO, @@ -1064,8 +1064,8 @@ Known = KnownBits::commonBits(Known, KnownSrc); // Attempt to avoid multi-use src if we don't need anything from it. - if (!DemandedBits.isAllOnesValue() || !DemandedSubElts.isAllOnesValue() || - !DemandedSrcElts.isAllOnesValue()) { + if (!DemandedBits.isAllOnes() || !DemandedSubElts.isAllOnes() || + !DemandedSrcElts.isAllOnes()) { SDValue NewSub = SimplifyMultipleUseDemandedBits( Sub, DemandedBits, DemandedSubElts, TLO.DAG, Depth + 1); SDValue NewSrc = SimplifyMultipleUseDemandedBits( @@ -1094,7 +1094,7 @@ return true; // Attempt to avoid multi-use src if we don't need anything from it. - if (!DemandedBits.isAllOnesValue() || !DemandedSrcElts.isAllOnesValue()) { + if (!DemandedBits.isAllOnes() || !DemandedSrcElts.isAllOnes()) { SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( Src, DemandedBits, DemandedSrcElts, TLO.DAG, Depth + 1); if (DemandedSrc) { @@ -1224,7 +1224,7 @@ assert(!Known2.hasConflict() && "Bits known to be one AND zero?"); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { + if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( @@ -1271,7 +1271,7 @@ assert(!Known2.hasConflict() && "Bits known to be one AND zero?"); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { + if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( @@ -1314,7 +1314,7 @@ assert(!Known2.hasConflict() && "Bits known to be one AND zero?"); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedBits.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { + if (!DemandedBits.isAllOnes() || !DemandedElts.isAllOnes()) { SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( Op0, DemandedBits, DemandedElts, TLO.DAG, Depth + 1); SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( @@ -1663,7 +1663,7 @@ Known.One.setHighBits(ShAmt); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!InDemandedMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { + if (!InDemandedMask.isAllOnes() || !DemandedElts.isAllOnes()) { SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( Op0, InDemandedMask, DemandedElts, TLO.DAG, Depth + 1); if (DemandedOp0) { @@ -2079,7 +2079,7 @@ // Demand the bits from every vector element without a constant index. unsigned NumSrcElts = SrcEltCnt.getFixedValue(); - APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts); + APInt DemandedSrcElts = APInt::getAllOnes(NumSrcElts); if (auto *CIdx = dyn_cast(Idx)) if (CIdx->getAPIntValue().ult(NumSrcElts)) DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue()); @@ -2095,8 +2095,7 @@ return true; // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedSrcBits.isAllOnesValue() || - !DemandedSrcElts.isAllOnesValue()) { + if (!DemandedSrcBits.isAllOnes() || !DemandedSrcElts.isAllOnes()) { if (SDValue DemandedSrc = SimplifyMultipleUseDemandedBits( Src, DemandedSrcBits, DemandedSrcElts, TLO.DAG, Depth + 1)) { SDValue NewOp = @@ -2146,8 +2145,8 @@ TLO.DAG.getDataLayout().isLittleEndian()) { unsigned Scale = BitWidth / NumSrcEltBits; unsigned NumSrcElts = SrcVT.getVectorNumElements(); - APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); - APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); + APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); + APInt DemandedSrcElts = APInt::getZero(NumSrcElts); for (unsigned i = 0; i != Scale; ++i) { unsigned Offset = i * NumSrcEltBits; APInt Sub = DemandedBits.extractBits(NumSrcEltBits, Offset); @@ -2172,8 +2171,8 @@ TLO.DAG.getDataLayout().isLittleEndian()) { unsigned Scale = NumSrcEltBits / BitWidth; unsigned NumSrcElts = SrcVT.isVector() ? SrcVT.getVectorNumElements() : 1; - APInt DemandedSrcBits = APInt::getNullValue(NumSrcEltBits); - APInt DemandedSrcElts = APInt::getNullValue(NumSrcElts); + APInt DemandedSrcBits = APInt::getZero(NumSrcEltBits); + APInt DemandedSrcElts = APInt::getZero(NumSrcElts); for (unsigned i = 0; i != NumElts; ++i) if (DemandedElts[i]) { unsigned Offset = (i % Scale) * BitWidth; @@ -2230,7 +2229,7 @@ } // Attempt to avoid multi-use ops if we don't need anything from them. - if (!LoMask.isAllOnesValue() || !DemandedElts.isAllOnesValue()) { + if (!LoMask.isAllOnes() || !DemandedElts.isAllOnes()) { SDValue DemandedOp0 = SimplifyMultipleUseDemandedBits( Op0, LoMask, DemandedElts, TLO.DAG, Depth + 1); SDValue DemandedOp1 = SimplifyMultipleUseDemandedBits( @@ -2254,7 +2253,7 @@ ConstantSDNode *C = isConstOrConstSplat(Op1); APInt HighMask = APInt::getHighBitsSet(BitWidth, DemandedBitsLZ); if (C && !C->isAllOnesValue() && !C->isOne() && - (C->getAPIntValue() | HighMask).isAllOnesValue()) { + (C->getAPIntValue() | HighMask).isAllOnes()) { SDValue Neg1 = TLO.DAG.getAllOnesConstant(dl, VT); // Disable the nsw and nuw flags. We can no longer guarantee that we // won't wrap after simplification. @@ -2352,7 +2351,7 @@ return SDValue(); }; - APInt KnownUndef = APInt::getNullValue(NumElts); + APInt KnownUndef = APInt::getZero(NumElts); for (unsigned i = 0; i != NumElts; ++i) { // If both inputs for this element are either constant or undef and match // the element type, compute the constant/undef result for this element of @@ -2379,7 +2378,7 @@ unsigned NumElts = DemandedElts.getBitWidth(); assert(VT.isVector() && "Expected vector op"); - KnownUndef = KnownZero = APInt::getNullValue(NumElts); + KnownUndef = KnownZero = APInt::getZero(NumElts); // TODO: For now we assume we know nothing about scalable vectors. if (VT.isScalableVector()) @@ -2472,7 +2471,7 @@ KnownZero, TLO, Depth + 1); APInt SrcZero, SrcUndef; - APInt SrcDemandedElts = APInt::getNullValue(NumSrcElts); + APInt SrcDemandedElts = APInt::getZero(NumSrcElts); // Bitcast from 'large element' src vector to 'small element' vector, we // must demand a source element if any DemandedElt maps to it. @@ -2491,7 +2490,7 @@ // TODO - bigendian once we have test coverage. if (TLO.DAG.getDataLayout().isLittleEndian()) { unsigned SrcEltSizeInBits = SrcVT.getScalarSizeInBits(); - APInt SrcDemandedBits = APInt::getNullValue(SrcEltSizeInBits); + APInt SrcDemandedBits = APInt::getZero(SrcEltSizeInBits); for (unsigned i = 0; i != NumElts; ++i) if (DemandedElts[i]) { unsigned Ofs = (i % Scale) * EltSizeInBits; @@ -2533,9 +2532,9 @@ // the output element will be as well, assuming it was demanded. for (unsigned i = 0; i != NumElts; ++i) { if (DemandedElts[i]) { - if (SrcZero.extractBits(Scale, i * Scale).isAllOnesValue()) + if (SrcZero.extractBits(Scale, i * Scale).isAllOnes()) KnownZero.setBit(i); - if (SrcUndef.extractBits(Scale, i * Scale).isAllOnesValue()) + if (SrcUndef.extractBits(Scale, i * Scale).isAllOnes()) KnownUndef.setBit(i); } } @@ -2544,7 +2543,7 @@ } case ISD::BUILD_VECTOR: { // Check all elements and simplify any unused elements with UNDEF. - if (!DemandedElts.isAllOnesValue()) { + if (!DemandedElts.isAllOnes()) { // Don't simplify BROADCASTS. if (llvm::any_of(Op->op_values(), [&](SDValue Elt) { return Op.getOperand(0) != Elt; })) { @@ -2597,7 +2596,7 @@ unsigned NumSubElts = Sub.getValueType().getVectorNumElements(); APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx); APInt DemandedSrcElts = DemandedElts; - DemandedSrcElts.insertBits(APInt::getNullValue(NumSubElts), Idx); + DemandedSrcElts.insertBits(APInt::getZero(NumSubElts), Idx); APInt SubUndef, SubZero; if (SimplifyDemandedVectorElts(Sub, DemandedSubElts, SubUndef, SubZero, TLO, @@ -2617,8 +2616,7 @@ KnownZero.insertBits(SubZero, Idx); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedSrcElts.isAllOnesValue() || - !DemandedSubElts.isAllOnesValue()) { + if (!DemandedSrcElts.isAllOnes() || !DemandedSubElts.isAllOnes()) { SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( Src, DemandedSrcElts, TLO.DAG, Depth + 1); SDValue NewSub = SimplifyMultipleUseDemandedVectorElts( @@ -2650,7 +2648,7 @@ KnownZero = SrcZero.extractBits(NumElts, Idx); // Attempt to avoid multi-use ops if we don't need anything from them. - if (!DemandedElts.isAllOnesValue()) { + if (!DemandedElts.isAllOnes()) { SDValue NewSrc = SimplifyMultipleUseDemandedVectorElts( Src, DemandedSrcElts, TLO.DAG, Depth + 1); if (NewSrc) { @@ -2850,7 +2848,7 @@ // Attempt to avoid multi-use ops if we don't need anything from them. // TODO - use KnownUndef to relax the demandedelts? - if (!DemandedElts.isAllOnesValue()) + if (!DemandedElts.isAllOnes()) if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) return true; break; @@ -2877,7 +2875,7 @@ // Attempt to avoid multi-use ops if we don't need anything from them. // TODO - use KnownUndef to relax the demandedelts? - if (!DemandedElts.isAllOnesValue()) + if (!DemandedElts.isAllOnes()) if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) return true; break; @@ -2905,7 +2903,7 @@ // Attempt to avoid multi-use ops if we don't need anything from them. // TODO - use KnownUndef to relax the demandedelts? - if (!DemandedElts.isAllOnesValue()) + if (!DemandedElts.isAllOnes()) if (SimplifyDemandedVectorEltsBinOp(Op0, Op1)) return true; break; @@ -2931,7 +2929,7 @@ return true; } else { KnownBits Known; - APInt DemandedBits = APInt::getAllOnesValue(EltSizeInBits); + APInt DemandedBits = APInt::getAllOnes(EltSizeInBits); if (SimplifyDemandedBits(Op, DemandedBits, OriginalDemandedElts, Known, TLO, Depth, AssumeSingleUse)) return true; @@ -3121,7 +3119,7 @@ case ZeroOrOneBooleanContent: return CVal.isOneValue(); case ZeroOrNegativeOneBooleanContent: - return CVal.isAllOnesValue(); + return CVal.isAllOnes(); } llvm_unreachable("Invalid boolean contents"); @@ -4030,7 +4028,7 @@ // all bits clear: (X | (Y<<32)) == 0 --> (X | Y) == 0 // all bits set: (X | (Y<<32)) == -1 --> (X & Y) == -1 bool CmpZero = N1C->getAPIntValue().isNullValue(); - bool CmpNegOne = N1C->getAPIntValue().isAllOnesValue(); + bool CmpNegOne = N1C->getAPIntValue().isAllOnes(); if ((CmpZero || CmpNegOne) && N0.hasOneUse()) { // Match or(lo,shl(hi,bw/2)) pattern. auto IsConcat = [&](SDValue V, SDValue &Lo, SDValue &Hi) { @@ -5157,7 +5155,7 @@ APInt nc, delta, q1, r1, q2, r2; struct mu magu; magu.a = 0; // initialize "add" indicator - APInt allOnes = APInt::getAllOnesValue(d.getBitWidth()).lshr(LeadingZeros); + APInt allOnes = APInt::getAllOnes(d.getBitWidth()).lshr(LeadingZeros); APInt signedMin = APInt::getSignedMinValue(d.getBitWidth()); APInt signedMax = APInt::getSignedMaxValue(d.getBitWidth()); @@ -5285,7 +5283,7 @@ int NumeratorFactor = 0; int ShiftMask = -1; - if (Divisor.isOneValue() || Divisor.isAllOnesValue()) { + if (Divisor.isOneValue() || Divisor.isAllOnes()) { // If d is +1/-1, we just multiply the numerator by +1/-1. NumeratorFactor = Divisor.getSExtValue(); magics.m = 0; @@ -5456,7 +5454,7 @@ MagicFactors.push_back(DAG.getConstant(Magic, dl, SVT)); NPQFactors.push_back( DAG.getConstant(SelNPQ ? APInt::getOneBitSet(EltBits, EltBits - 1) - : APInt::getNullValue(EltBits), + : APInt::getZero(EltBits), dl, SVT)); PostShifts.push_back(DAG.getConstant(PostShift, dl, ShSVT)); UseNPQ |= SelNPQ; @@ -5687,14 +5685,14 @@ // Q = floor((2^W - 1) u/ D) // R = ((2^W - 1) u% D) APInt Q, R; - APInt::udivrem(APInt::getAllOnesValue(W), D, Q, R); + APInt::udivrem(APInt::getAllOnes(W), D, Q, R); // If we are comparing with zero, then that comparison constant is okay, // else it may need to be one less than that. if (Cmp.ugt(R)) Q -= 1; - assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && + assert(APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT"); // If the lane is tautological the result can be constant-folded. @@ -5943,9 +5941,9 @@ // Q = floor((2 * A) / (2^K)) APInt Q = (2 * A).udiv(APInt::getOneBitSet(W, K)); - assert(APInt::getAllOnesValue(SVT.getSizeInBits()).ugt(A) && + assert(APInt::getAllOnes(SVT.getSizeInBits()).ugt(A) && "We are expecting that A is always less than all-ones for SVT"); - assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) && + assert(APInt::getAllOnes(ShSVT.getSizeInBits()).ugt(K) && "We are expecting that K is always less than all-ones for ShSVT"); // If the divisor is 1 the result can be constant-folded. Likewise, we @@ -6076,7 +6074,7 @@ SDValue IntMax = DAG.getConstant( APInt::getSignedMaxValue(SVT.getScalarSizeInBits()), DL, VT); SDValue Zero = - DAG.getConstant(APInt::getNullValue(SVT.getScalarSizeInBits()), DL, VT); + DAG.getConstant(APInt::getZero(SVT.getScalarSizeInBits()), DL, VT); // Which lanes had INT_MIN divisors? Divisor is constant, so const-folded. SDValue DivisorIsIntMin = DAG.getSetCC(DL, SETCCVT, D, IntMin, ISD::SETEQ); @@ -6902,7 +6900,7 @@ // the destination signmask can't be represented by the float, so we can // just use FP_TO_SINT directly. const fltSemantics &APFSem = DAG.EVTToAPFloatSemantics(SrcVT); - APFloat APF(APFSem, APInt::getNullValue(SrcVT.getScalarSizeInBits())); + APFloat APF(APFSem, APInt::getZero(SrcVT.getScalarSizeInBits())); APInt SignMask = APInt::getSignMask(DstVT.getScalarSizeInBits()); if (APFloat::opOverflow & APF.convertFromAPInt(SignMask, false, APFloat::rmNearestTiesToEven)) { diff --git a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp --- a/llvm/lib/CodeGen/SwitchLoweringUtils.cpp +++ b/llvm/lib/CodeGen/SwitchLoweringUtils.cpp @@ -405,7 +405,7 @@ if (Low.isStrictlyPositive() && High.slt(BitWidth)) { // Optimize the case where all the case values fit in a word without having // to subtract minValue. In this case, we can optimize away the subtraction. - LowBound = APInt::getNullValue(Low.getBitWidth()); + LowBound = APInt::getZero(Low.getBitWidth()); CmpRange = High; ContiguousRange = false; } else { diff --git a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp --- a/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp +++ b/llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp @@ -1945,7 +1945,7 @@ static std::string scalarConstantToHexString(const Constant *C) { Type *Ty = C->getType(); if (isa(C)) { - return APIntToHexString(APInt::getNullValue(Ty->getPrimitiveSizeInBits())); + return APIntToHexString(APInt::getZero(Ty->getPrimitiveSizeInBits())); } else if (const auto *CFP = dyn_cast(C)) { return APIntToHexString(CFP->getValueAPF().bitcastToAPInt()); } else if (const auto *CI = dyn_cast(C)) { diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp --- a/llvm/lib/CodeGen/TypePromotion.cpp +++ b/llvm/lib/CodeGen/TypePromotion.cpp @@ -364,7 +364,7 @@ Total += OverflowConst->getValue().getBitWidth() < 32 ? OverflowConst->getValue().abs().zext(32) : OverflowConst->getValue().abs(); - APInt Max = APInt::getAllOnesValue(TypePromotion::TypeSize); + APInt Max = APInt::getAllOnes(TypePromotion::TypeSize); if (Total.getBitWidth() > Max.getBitWidth()) { if (Total.ugt(Max.zext(Total.getBitWidth()))) diff --git a/llvm/lib/IR/ConstantFold.cpp b/llvm/lib/IR/ConstantFold.cpp --- a/llvm/lib/IR/ConstantFold.cpp +++ b/llvm/lib/IR/ConstantFold.cpp @@ -479,7 +479,7 @@ if (ConstantInt *CI = dyn_cast(V)) { const APInt &api = CI->getValue(); APFloat apf(DestTy->getFltSemantics(), - APInt::getNullValue(DestTy->getPrimitiveSizeInBits())); + APInt::getZero(DestTy->getPrimitiveSizeInBits())); apf.convertFromAPInt(api, opc==Instruction::SIToFP, APFloat::rmNearestTiesToEven); return ConstantFP::get(V->getContext(), apf); diff --git a/llvm/lib/IR/ConstantRange.cpp b/llvm/lib/IR/ConstantRange.cpp --- a/llvm/lib/IR/ConstantRange.cpp +++ b/llvm/lib/IR/ConstantRange.cpp @@ -110,7 +110,7 @@ APInt UMin(CR.getUnsignedMin()); if (UMin.isMaxValue()) return getEmpty(W); - return ConstantRange(std::move(UMin) + 1, APInt::getNullValue(W)); + return ConstantRange(std::move(UMin) + 1, APInt::getZero(W)); } case CmpInst::ICMP_SGT: { APInt SMin(CR.getSignedMin()); @@ -119,7 +119,7 @@ return ConstantRange(std::move(SMin) + 1, APInt::getSignedMinValue(W)); } case CmpInst::ICMP_UGE: - return getNonEmpty(CR.getUnsignedMin(), APInt::getNullValue(W)); + return getNonEmpty(CR.getUnsignedMin(), APInt::getZero(W)); case CmpInst::ICMP_SGE: return getNonEmpty(CR.getSignedMin(), APInt::getSignedMinValue(W)); } @@ -248,8 +248,7 @@ case Instruction::Add: { if (Unsigned) - return getNonEmpty(APInt::getNullValue(BitWidth), - -Other.getUnsignedMax()); + return getNonEmpty(APInt::getZero(BitWidth), -Other.getUnsignedMax()); APInt SignedMinVal = APInt::getSignedMinValue(BitWidth); APInt SMin = Other.getSignedMin(), SMax = Other.getSignedMax(); @@ -291,7 +290,7 @@ // to be at most bitwidth-1, which results in most conservative range. APInt ShAmtUMax = ShAmt.getUnsignedMax(); if (Unsigned) - return getNonEmpty(APInt::getNullValue(BitWidth), + return getNonEmpty(APInt::getZero(BitWidth), APInt::getMaxValue(BitWidth).lshr(ShAmtUMax) + 1); return getNonEmpty(APInt::getSignedMinValue(BitWidth).ashr(ShAmtUMax), APInt::getSignedMaxValue(BitWidth).ashr(ShAmtUMax) + 1); @@ -316,7 +315,7 @@ } bool ConstantRange::isWrappedSet() const { - return Lower.ugt(Upper) && !Upper.isNullValue(); + return Lower.ugt(Upper) && !Upper.isZero(); } bool ConstantRange::isUpperWrapped() const { @@ -595,7 +594,7 @@ APInt L = CR.Lower.ult(Lower) ? CR.Lower : Lower; APInt U = (CR.Upper - 1).ugt(Upper - 1) ? CR.Upper : Upper; - if (L.isNullValue() && U.isNullValue()) + if (L.isZero() && U.isZero()) return getFull(); return ConstantRange(std::move(L), std::move(U)); @@ -1113,13 +1112,13 @@ ConstantRange ConstantRange::udiv(const ConstantRange &RHS) const { - if (isEmptySet() || RHS.isEmptySet() || RHS.getUnsignedMax().isNullValue()) + if (isEmptySet() || RHS.isEmptySet() || RHS.getUnsignedMax().isZero()) return getEmpty(); APInt Lower = getUnsignedMin().udiv(RHS.getUnsignedMax()); APInt RHS_umin = RHS.getUnsignedMin(); - if (RHS_umin.isNullValue()) { + if (RHS_umin.isZero()) { // We want the lowest value in RHS excluding zero. Usually that would be 1 // except for a range in the form of [X, 1) in which case it would be X. if (RHS.getUpper() == 1) @@ -1136,7 +1135,7 @@ // We split up the LHS and RHS into positive and negative components // and then also compute the positive and negative components of the result // separately by combining division results with the appropriate signs. - APInt Zero = APInt::getNullValue(getBitWidth()); + APInt Zero = APInt::getZero(getBitWidth()); APInt SignedMin = APInt::getSignedMinValue(getBitWidth()); ConstantRange PosFilter(APInt(getBitWidth(), 1), SignedMin); ConstantRange NegFilter(SignedMin, Zero); @@ -1159,7 +1158,7 @@ // (For APInts the operation is well-defined and yields SignedMin.) We // handle this by dropping either SignedMin from the LHS or -1 from the RHS. APInt Lo = (NegL.Upper - 1).sdiv(NegR.Lower); - if (NegL.Lower.isMinSignedValue() && NegR.Upper.isNullValue()) { + if (NegL.Lower.isMinSignedValue() && NegR.Upper.isZero()) { // Remove -1 from the LHS. Skip if it's the only element, as this would // leave us with an empty set. if (!NegR.Lower.isAllOnesValue()) { @@ -1218,12 +1217,12 @@ } ConstantRange ConstantRange::urem(const ConstantRange &RHS) const { - if (isEmptySet() || RHS.isEmptySet() || RHS.getUnsignedMax().isNullValue()) + if (isEmptySet() || RHS.isEmptySet() || RHS.getUnsignedMax().isZero()) return getEmpty(); if (const APInt *RHSInt = RHS.getSingleElement()) { // UREM by null is UB. - if (RHSInt->isNullValue()) + if (RHSInt->isZero()) return getEmpty(); // Use APInt's implementation of UREM for single element ranges. if (const APInt *LHSInt = getSingleElement()) @@ -1236,7 +1235,7 @@ // L % R is <= L and < R. APInt Upper = APIntOps::umin(getUnsignedMax(), RHS.getUnsignedMax() - 1) + 1; - return getNonEmpty(APInt::getNullValue(getBitWidth()), std::move(Upper)); + return getNonEmpty(APInt::getZero(getBitWidth()), std::move(Upper)); } ConstantRange ConstantRange::srem(const ConstantRange &RHS) const { @@ -1245,7 +1244,7 @@ if (const APInt *RHSInt = RHS.getSingleElement()) { // SREM by null is UB. - if (RHSInt->isNullValue()) + if (RHSInt->isZero()) return getEmpty(); // Use APInt's implementation of SREM for single element ranges. if (const APInt *LHSInt = getSingleElement()) @@ -1257,10 +1256,10 @@ APInt MaxAbsRHS = AbsRHS.getUnsignedMax(); // Modulus by zero is UB. - if (MaxAbsRHS.isNullValue()) + if (MaxAbsRHS.isZero()) return getEmpty(); - if (MinAbsRHS.isNullValue()) + if (MinAbsRHS.isZero()) ++MinAbsRHS; APInt MinLHS = getSignedMin(), MaxLHS = getSignedMax(); @@ -1272,7 +1271,7 @@ // L % R is <= L and < R. APInt Upper = APIntOps::umin(MaxLHS, MaxAbsRHS - 1) + 1; - return ConstantRange(APInt::getNullValue(getBitWidth()), std::move(Upper)); + return ConstantRange(APInt::getZero(getBitWidth()), std::move(Upper)); } // Same basic logic as above, but the result is negative. @@ -1291,7 +1290,7 @@ } ConstantRange ConstantRange::binaryNot() const { - return ConstantRange(APInt::getAllOnesValue(getBitWidth())).sub(*this); + return ConstantRange(APInt::getAllOnes(getBitWidth())).sub(*this); } ConstantRange @@ -1306,7 +1305,7 @@ // TODO: replace this with something less conservative APInt umin = APIntOps::umin(Other.getUnsignedMax(), getUnsignedMax()); - return getNonEmpty(APInt::getNullValue(getBitWidth()), std::move(umin) + 1); + return getNonEmpty(APInt::getZero(getBitWidth()), std::move(umin) + 1); } ConstantRange @@ -1321,7 +1320,7 @@ // TODO: replace this with something less conservative APInt umax = APIntOps::umax(getUnsignedMin(), Other.getUnsignedMin()); - return getNonEmpty(std::move(umax), APInt::getNullValue(getBitWidth())); + return getNonEmpty(std::move(umax), APInt::getZero(getBitWidth())); } ConstantRange ConstantRange::binaryXor(const ConstantRange &Other) const { @@ -1352,7 +1351,7 @@ // If we are shifting by maximum amount of // zero return return the original range. - if (Other_umax.isNullValue()) + if (Other_umax.isZero()) return *this; // there's overflow! if (Other_umax.ugt(max.countLeadingZeros())) @@ -1535,7 +1534,7 @@ APInt Lo; // Check whether the range crosses zero. if (Upper.isStrictlyPositive() || !Lower.isStrictlyPositive()) - Lo = APInt::getNullValue(getBitWidth()); + Lo = APInt::getZero(getBitWidth()); else Lo = APIntOps::umin(Lower, -Upper + 1); @@ -1565,7 +1564,7 @@ return ConstantRange(-SMax, -SMin + 1); // Range crosses zero. - return ConstantRange(APInt::getNullValue(getBitWidth()), + return ConstantRange(APInt::getZero(getBitWidth()), APIntOps::umax(-SMin, SMax) + 1); } diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp --- a/llvm/lib/IR/Constants.cpp +++ b/llvm/lib/IR/Constants.cpp @@ -366,9 +366,8 @@ return ConstantFP::get(Ty->getContext(), APFloat::getZero(APFloat::IEEEquad())); case Type::PPC_FP128TyID: - return ConstantFP::get(Ty->getContext(), - APFloat(APFloat::PPCDoubleDouble(), - APInt::getNullValue(128))); + return ConstantFP::get(Ty->getContext(), APFloat(APFloat::PPCDoubleDouble(), + APInt::getZero(128))); case Type::PointerTyID: return ConstantPointerNull::get(cast(Ty)); case Type::StructTyID: @@ -404,7 +403,7 @@ Constant *Constant::getAllOnesValue(Type *Ty) { if (IntegerType *ITy = dyn_cast(Ty)) return ConstantInt::get(Ty->getContext(), - APInt::getAllOnesValue(ITy->getBitWidth())); + APInt::getAllOnes(ITy->getBitWidth())); if (Ty->isFloatingPointTy()) { APFloat FL = APFloat::getAllOnesValue(Ty->getFltSemantics(), diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -2271,9 +2271,9 @@ return false; // Determine which mask elements are attributed to which source. - APInt UndefElts = APInt::getNullValue(NumMaskElts); - APInt Src0Elts = APInt::getNullValue(NumMaskElts); - APInt Src1Elts = APInt::getNullValue(NumMaskElts); + APInt UndefElts = APInt::getZero(NumMaskElts); + APInt Src0Elts = APInt::getZero(NumMaskElts); + APInt Src1Elts = APInt::getZero(NumMaskElts); bool Src0Identity = true; bool Src1Identity = true; diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp --- a/llvm/lib/IR/Type.cpp +++ b/llvm/lib/IR/Type.cpp @@ -296,9 +296,7 @@ return Entry; } -APInt IntegerType::getMask() const { - return APInt::getAllOnesValue(getBitWidth()); -} +APInt IntegerType::getMask() const { return APInt::getAllOnes(getBitWidth()); } //===----------------------------------------------------------------------===// // FunctionType Implementation diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -687,7 +687,7 @@ if (IsDepBreaking) { // A mask of all zeroes means: explicit input operands are not // independent. - if (Mask.isNullValue()) { + if (Mask.isZero()) { if (!RD.isImplicitRead()) RS.setIndependentFromDef(); } else { diff --git a/llvm/lib/Support/APFixedPoint.cpp b/llvm/lib/Support/APFixedPoint.cpp --- a/llvm/lib/Support/APFixedPoint.cpp +++ b/llvm/lib/Support/APFixedPoint.cpp @@ -381,7 +381,7 @@ // Add 4 digits to hold the value after multiplying 10 (the radix) unsigned Width = Val.getBitWidth() + 4; APInt FractPart = Val.zextOrTrunc(Scale).zext(Width); - APInt FractPartMask = APInt::getAllOnesValue(Scale).zext(Width); + APInt FractPartMask = APInt::getAllOnes(Scale).zext(Width); APInt RadixInt = APInt(Width, 10); IntPart.toString(Str, /*Radix=*/10); diff --git a/llvm/lib/Support/APFloat.cpp b/llvm/lib/Support/APFloat.cpp --- a/llvm/lib/Support/APFloat.cpp +++ b/llvm/lib/Support/APFloat.cpp @@ -4866,7 +4866,7 @@ APFloat APFloat::getAllOnesValue(const fltSemantics &Semantics, unsigned BitWidth) { - return APFloat(Semantics, APInt::getAllOnesValue(BitWidth)); + return APFloat(Semantics, APInt::getAllOnes(BitWidth)); } void APFloat::print(raw_ostream &OS) const { diff --git a/llvm/lib/Support/APInt.cpp b/llvm/lib/Support/APInt.cpp --- a/llvm/lib/Support/APInt.cpp +++ b/llvm/lib/Support/APInt.cpp @@ -1121,7 +1121,7 @@ return U.VAL - 1; // Handle the zero case. - if (isNullValue()) + if (isZero()) return UINT32_MAX; // The non-zero case is handled by computing: @@ -2764,7 +2764,7 @@ << "x + " << C << ", rw:" << RangeWidth << '\n'); // Identify 0 as a (non)solution immediately. - if (C.sextOrTrunc(RangeWidth).isNullValue() ) { + if (C.sextOrTrunc(RangeWidth).isZero()) { LLVM_DEBUG(dbgs() << __func__ << ": zero solution\n"); return APInt(CoeffWidth, 0); } @@ -2826,7 +2826,7 @@ auto RoundUp = [] (const APInt &V, const APInt &A) -> APInt { assert(A.isStrictlyPositive()); APInt T = V.abs().urem(A); - if (T.isNullValue()) + if (T.isZero()) return V; return V.isNegative() ? V+T : V+(A-T); }; @@ -2910,7 +2910,7 @@ // can be 0, but cannot be negative. assert(X.isNonNegative() && "Solution should be non-negative"); - if (!InexactSQ && Rem.isNullValue()) { + if (!InexactSQ && Rem.isZero()) { LLVM_DEBUG(dbgs() << __func__ << ": solution (root): " << X << '\n'); return X; } @@ -2926,8 +2926,8 @@ APInt VX = (A*X + B)*X + C; APInt VY = VX + TwoA*X + A + B; - bool SignChange = VX.isNegative() != VY.isNegative() || - VX.isNullValue() != VY.isNullValue(); + bool SignChange = + VX.isNegative() != VY.isNegative() || VX.isZero() != VY.isZero(); // If the sign did not change between X and X+1, X is not a valid solution. // This could happen when the actual (exact) roots don't have an integer // between them, so they would both be contained between X and X+1. diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -13525,7 +13525,7 @@ unsigned ElemSizeInBits = VT.getScalarSizeInBits(); APInt CAsAPInt(ElemSizeInBits, C); - if (CAsAPInt != APInt::getAllOnesValue(ElemSizeInBits)) + if (CAsAPInt != APInt::getAllOnes(ElemSizeInBits)) return SDValue(); ExtendOpA = Xor.getOperand(0); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1710,7 +1710,7 @@ !cast(Idxen)->getSExtValue() && !cast(Addr64)->getSExtValue()) { uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | - APInt::getAllOnesValue(32).getZExtValue(); // Size + APInt::getAllOnes(32).getZExtValue(); // Size SDLoc DL(Addr); const SITargetLowering& Lowering = diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -12182,8 +12182,7 @@ // When looking for a 0 constant, N can be zext or sext. OtherOp = DAG.getConstant(1, dl, VT); else - OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, - VT); + OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT); return true; } } @@ -19325,8 +19324,8 @@ if (Op.getResNo() == 0 && !Op->hasAnyUseOfValue(1) && isa(Op->getOperand(2))) { unsigned ShAmt = Op->getConstantOperandVal(2); - if (ShAmt < 32 && OriginalDemandedBits.isSubsetOf( - APInt::getAllOnesValue(32) << (32 - ShAmt))) + if (ShAmt < 32 && OriginalDemandedBits.isSubsetOf(APInt::getAllOnes(32) + << (32 - ShAmt))) return TLO.CombineTo( Op, TLO.DAG.getNode( ISD::SHL, SDLoc(Op), MVT::i32, Op.getOperand(1), diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -1400,8 +1400,7 @@ // value is 0. OtherOp = DAG.getConstant(0, dl, VT); else - OtherOp = - DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl, VT); + OtherOp = DAG.getConstant(APInt::getAllOnes(VT.getSizeInBits()), dl, VT); return true; } } diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -1978,7 +1978,7 @@ M68k::CondCode CC = TranslateIntegerM68kCC(cast(Cond)->get()); EVT CarryVT = Carry.getValueType(); - APInt NegOne = APInt::getAllOnesValue(CarryVT.getScalarSizeInBits()); + APInt NegOne = APInt::getAllOnes(CarryVT.getScalarSizeInBits()); Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry, DAG.getConstant(NegOne, DL, CarryVT)); diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -15226,7 +15226,7 @@ int Bits = 4 /* 16 byte alignment */; if (DAG.MaskedValueIsZero(Add->getOperand(1), - APInt::getAllOnesValue(Bits /* alignment */) + APInt::getAllOnes(Bits /* alignment */) .zext(Add.getScalarValueSizeInBits()))) { SDNode *BasePtr = Add->getOperand(0).getNode(); for (SDNode::use_iterator UI = BasePtr->use_begin(), diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6539,7 +6539,7 @@ assert((VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()) && "Expected a 128/256/512-bit vector type"); - APInt Ones = APInt::getAllOnesValue(32); + APInt Ones = APInt::getAllOnes(32); unsigned NumElts = VT.getSizeInBits() / 32; SDValue Vec = DAG.getConstant(Ones, dl, MVT::getVectorVT(MVT::i32, NumElts)); return DAG.getBitcast(VT, Vec); @@ -6818,19 +6818,19 @@ // Handle UNDEFs. if (Op.isUndef()) { - APInt UndefSrcElts = APInt::getAllOnesValue(NumElts); + APInt UndefSrcElts = APInt::getAllOnes(NumElts); SmallVector SrcEltBits(NumElts, APInt(EltSizeInBits, 0)); return CastBitData(UndefSrcElts, SrcEltBits); } // Extract scalar constant bits. if (auto *Cst = dyn_cast(Op)) { - APInt UndefSrcElts = APInt::getNullValue(1); + APInt UndefSrcElts = APInt::getZero(1); SmallVector SrcEltBits(1, Cst->getAPIntValue()); return CastBitData(UndefSrcElts, SrcEltBits); } if (auto *Cst = dyn_cast(Op)) { - APInt UndefSrcElts = APInt::getNullValue(1); + APInt UndefSrcElts = APInt::getZero(1); APInt RawBits = Cst->getValueAPF().bitcastToAPInt(); SmallVector SrcEltBits(1, RawBits); return CastBitData(UndefSrcElts, SrcEltBits); @@ -7034,12 +7034,12 @@ AllowPartialUndefs)) return false; - UndefElts = APInt::getNullValue(NumElts); + UndefElts = APInt::getZero(NumElts); for (int i = 0; i != (int)NumElts; ++i) { int M = Mask[i]; if (M < 0) { UndefElts.setBit(i); - EltBits.push_back(APInt::getNullValue(EltSizeInBits)); + EltBits.push_back(APInt::getZero(EltSizeInBits)); } else if (M < (int)NumElts) { if (UndefElts0[M]) UndefElts.setBit(i); @@ -7136,8 +7136,8 @@ int NumEltsPerLane = NumElts / NumLanes; int NumInnerEltsPerLane = NumInnerElts / NumLanes; - DemandedLHS = APInt::getNullValue(NumInnerElts); - DemandedRHS = APInt::getNullValue(NumInnerElts); + DemandedLHS = APInt::getZero(NumInnerElts); + DemandedRHS = APInt::getZero(NumInnerElts); // Map DemandedElts to the packed operands. for (int Lane = 0; Lane != NumLanes; ++Lane) { @@ -7160,8 +7160,8 @@ int NumEltsPerLane = NumElts / NumLanes; int HalfEltsPerLane = NumEltsPerLane / 2; - DemandedLHS = APInt::getNullValue(NumElts); - DemandedRHS = APInt::getNullValue(NumElts); + DemandedLHS = APInt::getZero(NumElts); + DemandedRHS = APInt::getZero(NumElts); // Map DemandedElts to the horizontal operands. for (int Idx = 0; Idx != NumElts; ++Idx) { @@ -7508,7 +7508,7 @@ SDValue V1, SDValue V2, APInt &KnownUndef, APInt &KnownZero) { int Size = Mask.size(); - KnownUndef = KnownZero = APInt::getNullValue(Size); + KnownUndef = KnownZero = APInt::getZero(Size); V1 = peekThroughBitcasts(V1); V2 = peekThroughBitcasts(V2); @@ -7601,7 +7601,7 @@ int Size = Mask.size(); SDValue V1 = Ops[0]; SDValue V2 = IsUnary ? V1 : Ops[1]; - KnownUndef = KnownZero = APInt::getNullValue(Size); + KnownUndef = KnownZero = APInt::getZero(Size); V1 = peekThroughBitcasts(V1); V2 = peekThroughBitcasts(V2); @@ -7708,7 +7708,7 @@ APInt &KnownUndef, APInt &KnownZero) { unsigned NumElts = Mask.size(); - KnownUndef = KnownZero = APInt::getNullValue(NumElts); + KnownUndef = KnownZero = APInt::getZero(NumElts); for (unsigned i = 0; i != NumElts; ++i) { int M = Mask[i]; @@ -8204,7 +8204,7 @@ APInt KnownUndef, KnownZero; unsigned NumElts = Op.getValueType().getVectorNumElements(); - APInt DemandedElts = APInt::getAllOnesValue(NumElts); + APInt DemandedElts = APInt::getAllOnes(NumElts); return getTargetShuffleInputs(Op, DemandedElts, Inputs, Mask, KnownUndef, KnownZero, DAG, Depth, ResolveKnownElts); } @@ -8729,9 +8729,9 @@ unsigned NumElems = Elts.size(); int LastLoadedElt = -1; - APInt LoadMask = APInt::getNullValue(NumElems); - APInt ZeroMask = APInt::getNullValue(NumElems); - APInt UndefMask = APInt::getNullValue(NumElems); + APInt LoadMask = APInt::getZero(NumElems); + APInt ZeroMask = APInt::getZero(NumElems); + APInt UndefMask = APInt::getZero(NumElems); SmallVector Loads(NumElems, nullptr); SmallVector ByteOffsets(NumElems, 0); @@ -9993,7 +9993,7 @@ V1 = insertSubVector(DAG.getUNDEF(VT), V1, 0, DAG, SDLoc(BV), Width); unsigned NumElts = VT.getVectorNumElements(); - APInt DemandedElts = APInt::getAllOnesValue(NumElts); + APInt DemandedElts = APInt::getAllOnes(NumElts); for (unsigned i = 0; i != NumElts; ++i) if (BV->getOperand(i).isUndef()) DemandedElts.clearBit(i); @@ -10568,9 +10568,9 @@ return VectorConstant; unsigned EVTBits = EltVT.getSizeInBits(); - APInt UndefMask = APInt::getNullValue(NumElems); - APInt ZeroMask = APInt::getNullValue(NumElems); - APInt NonZeroMask = APInt::getNullValue(NumElems); + APInt UndefMask = APInt::getZero(NumElems); + APInt ZeroMask = APInt::getZero(NumElems); + APInt NonZeroMask = APInt::getZero(NumElems); bool IsAllConstants = true; SmallSet Values; unsigned NumConstants = NumElems; @@ -22668,7 +22668,7 @@ if (!SrcOpMap.empty() && VT != SrcOpMap.begin()->first.getValueType()) return false; unsigned NumElts = VT.getVectorNumElements(); - APInt EltCount = APInt::getNullValue(NumElts); + APInt EltCount = APInt::getZero(NumElts); M = SrcOpMap.insert(std::make_pair(Src, EltCount)).first; SrcOps.push_back(Src); } @@ -22772,7 +22772,7 @@ // Check whether we're masking/truncating an OR-reduction result, in which // case track the masked bits. - APInt Mask = APInt::getAllOnesValue(Op.getScalarValueSizeInBits()); + APInt Mask = APInt::getAllOnes(Op.getScalarValueSizeInBits()); switch (Op.getOpcode()) { case ISD::TRUNCATE: { SDValue Src = Op.getOperand(0); @@ -35455,8 +35455,8 @@ APInt DemandedLHS, DemandedRHS; getPackDemandedElts(VT, DemandedElts, DemandedLHS, DemandedRHS); - Known.One = APInt::getAllOnesValue(BitWidth * 2); - Known.Zero = APInt::getAllOnesValue(BitWidth * 2); + Known.One = APInt::getAllOnes(BitWidth * 2); + Known.Zero = APInt::getAllOnes(BitWidth * 2); KnownBits Known2; if (!!DemandedLHS) { @@ -36202,8 +36202,8 @@ unsigned NumV2Elts = V2.getValueType().getVectorNumElements(); unsigned Scale1 = NumV1Elts / NumMaskElts; unsigned Scale2 = NumV2Elts / NumMaskElts; - APInt DemandedZeroV1 = APInt::getNullValue(NumV1Elts); - APInt DemandedZeroV2 = APInt::getNullValue(NumV2Elts); + APInt DemandedZeroV1 = APInt::getZero(NumV1Elts); + APInt DemandedZeroV2 = APInt::getZero(NumV2Elts); for (unsigned i = 0; i != NumMaskElts; ++i) { int M = Mask[i]; if (M == SM_SentinelUndef) @@ -36973,8 +36973,8 @@ if (UnaryShuffle && MaskContainsZeros && AllowVariablePerLaneMask && isSequentialOrUndefOrZeroInRange(Mask, 0, NumMaskElts, 0) && DAG.getTargetLoweringInfo().isTypeLegal(MaskVT)) { - APInt Zero = APInt::getNullValue(MaskEltSizeInBits); - APInt AllOnes = APInt::getAllOnesValue(MaskEltSizeInBits); + APInt Zero = APInt::getZero(MaskEltSizeInBits); + APInt AllOnes = APInt::getAllOnes(MaskEltSizeInBits); APInt UndefElts(NumMaskElts, 0); SmallVector EltBits(NumMaskElts, Zero); for (unsigned i = 0; i != NumMaskElts; ++i) { @@ -37483,7 +37483,7 @@ APInt ZeroElts(NumMaskElts, 0); APInt ConstantElts(NumMaskElts, 0); SmallVector ConstantBitData(NumMaskElts, - APInt::getNullValue(MaskSizeInBits)); + APInt::getZero(MaskSizeInBits)); for (unsigned i = 0; i != NumMaskElts; ++i) { int M = Mask[i]; if (M == SM_SentinelUndef) { @@ -37610,7 +37610,7 @@ SmallVector OpMask; SmallVector OpInputs; APInt OpUndef, OpZero; - APInt OpDemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + APInt OpDemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); bool IsOpVariableMask = isTargetShuffleVariableMask(Op.getOpcode()); if (!getTargetShuffleInputs(Op, OpDemandedElts, OpInputs, OpMask, OpUndef, OpZero, DAG, Depth, false)) @@ -37653,7 +37653,7 @@ // up in an infinite loop. bool ResolveKnownZeros = true; if (!OpZero.isNullValue()) { - APInt UsedInputs = APInt::getNullValue(OpInputs.size()); + APInt UsedInputs = APInt::getZero(OpInputs.size()); for (int i = 0, e = OpMask.size(); i != e; ++i) { int M = OpMask[i]; if (OpUndef[i] || OpZero[i] || isUndefOrZero(M)) @@ -39253,7 +39253,7 @@ // Simplify source operands based on shuffle mask. // TODO - merge this into combineX86ShufflesRecursively. APInt KnownUndef, KnownZero; - APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); if (TLI.SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, DCI)) return SDValue(N, 0); @@ -39860,7 +39860,7 @@ continue; int Lo = Src * NumElts; - APInt SrcElts = APInt::getNullValue(NumElts); + APInt SrcElts = APInt::getZero(NumElts); for (int i = 0; i != NumElts; ++i) if (DemandedElts[i]) { int M = OpMask[i] - Lo; @@ -40382,7 +40382,7 @@ return getZeroVector(VT.getSimpleVT(), Subtarget, DAG, SDLoc(Op)); // Bitmask that indicates which ops have only been accessed 'inline'. - APInt IdentityOp = APInt::getAllOnesValue(NumOps); + APInt IdentityOp = APInt::getAllOnes(NumOps); for (int i = 0; i != NumElts; ++i) { int M = ShuffleMask[i]; if (!DemandedElts[i] || ShuffleUndef[i]) @@ -41233,7 +41233,7 @@ else if (BinOp == ISD::SMIN) Mask = DAG.getConstant(APInt::getSignedMinValue(MaskEltsBits), DL, SrcVT); else if (BinOp == ISD::UMAX) - Mask = DAG.getConstant(APInt::getAllOnesValue(MaskEltsBits), DL, SrcVT); + Mask = DAG.getConstant(APInt::getAllOnes(MaskEltsBits), DL, SrcVT); if (Mask) MinPos = DAG.getNode(ISD::XOR, DL, SrcVT, Mask, MinPos); @@ -41965,8 +41965,8 @@ if (IsPextr) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.SimplifyDemandedBits( - SDValue(N, 0), APInt::getAllOnesValue(VT.getSizeInBits()), DCI)) + if (TLI.SimplifyDemandedBits(SDValue(N, 0), + APInt::getAllOnes(VT.getSizeInBits()), DCI)) return SDValue(N, 0); // PEXTR*(PINSR*(v, s, c), c) -> s (with implicit zext handling). @@ -43518,7 +43518,7 @@ ShuffleInputs.size() == 1 && !isAnyZeroOrUndef(ShuffleMask) && ShuffleInputs[0].getValueSizeInBits() == VecVT.getSizeInBits()) { unsigned NumShuffleElts = ShuffleMask.size(); - APInt DemandedElts = APInt::getNullValue(NumShuffleElts); + APInt DemandedElts = APInt::getZero(NumShuffleElts); for (int M : ShuffleMask) { assert(0 <= M && M < (int)NumShuffleElts && "Bad unary shuffle index"); DemandedElts.setBit(M); @@ -44658,7 +44658,7 @@ unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; APInt Undefs(NumDstElts, 0); - SmallVector Bits(NumDstElts, APInt::getNullValue(DstBitsPerElt)); + SmallVector Bits(NumDstElts, APInt::getZero(DstBitsPerElt)); for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { for (unsigned Elt = 0; Elt != NumDstEltsPerLane; ++Elt) { unsigned SrcIdx = Lane * NumSrcEltsPerLane + Elt % NumSrcEltsPerLane; @@ -44688,9 +44688,9 @@ if (Val.isIntN(DstBitsPerElt)) Val = Val.trunc(DstBitsPerElt); else if (Val.isNegative()) - Val = APInt::getNullValue(DstBitsPerElt); + Val = APInt::getZero(DstBitsPerElt); else - Val = APInt::getAllOnesValue(DstBitsPerElt); + Val = APInt::getAllOnes(DstBitsPerElt); } Bits[Lane * NumDstEltsPerLane + Elt] = Val; } @@ -44848,7 +44848,7 @@ APInt KnownUndef, KnownZero; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef, KnownZero, DCI)) return SDValue(N, 0); @@ -44950,8 +44950,8 @@ } const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.SimplifyDemandedBits(SDValue(N, 0), - APInt::getAllOnesValue(NumBitsPerElt), DCI)) + if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumBitsPerElt), + DCI)) return SDValue(N, 0); return SDValue(); @@ -44970,7 +44970,7 @@ unsigned NumBitsPerElt = VT.getScalarSizeInBits(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (TLI.SimplifyDemandedBits(SDValue(N, 0), - APInt::getAllOnesValue(NumBitsPerElt), DCI)) + APInt::getAllOnes(NumBitsPerElt), DCI)) return SDValue(N, 0); } @@ -46171,7 +46171,7 @@ APInt SignedMax, SignedMin; if (MatchPackUS) { - SignedMax = APInt::getAllOnesValue(NumDstBits).zext(NumSrcBits); + SignedMax = APInt::getAllOnes(NumDstBits).zext(NumSrcBits); SignedMin = APInt(NumSrcBits, 0); } else { SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits); @@ -47747,7 +47747,7 @@ // SimplifyDemandedBits often relaxes sra to srl so we need to reverse it. if (In.getOpcode() == ISD::SRL && N->isOnlyUserOf(In.getNode())) if (const APInt *ShAmt = DAG.getValidShiftAmountConstant( - In, APInt::getAllOnesValue(VT.getVectorNumElements()))) { + In, APInt::getAllOnes(VT.getVectorNumElements()))) { if (*ShAmt == MinSignBits) { SDValue NewIn = DAG.getNode(ISD::SRA, DL, InVT, In->ops()); return truncateVectorWithPACK(X86ISD::PACKSS, VT, NewIn, DL, DAG, @@ -48003,7 +48003,7 @@ return DAG.getNode(X86ISD::VTRUNCUS, DL, VT, USatVal); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - APInt DemandedMask(APInt::getAllOnesValue(VT.getScalarSizeInBits())); + APInt DemandedMask(APInt::getAllOnes(VT.getScalarSizeInBits())); if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) return SDValue(N, 0); @@ -48387,7 +48387,7 @@ // Simplify the inputs. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - APInt DemandedMask(APInt::getAllOnesValue(NumBits)); + APInt DemandedMask(APInt::getAllOnes(NumBits)); if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) return SDValue(N, 0); @@ -48591,7 +48591,7 @@ const TargetLowering &TLI = DAG.getTargetLoweringInfo(); APInt KnownUndef, KnownZero; - APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef, KnownZero, DCI)) return SDValue(N, 0); @@ -49704,7 +49704,7 @@ // Simplify the inputs. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - APInt DemandedMask(APInt::getAllOnesValue(NumBits)); + APInt DemandedMask(APInt::getAllOnes(NumBits)); if (TLI.SimplifyDemandedBits(SDValue(N, 0), DemandedMask, DCI)) return SDValue(N, 0); @@ -51748,7 +51748,7 @@ // PMULDQ/PMULUDQ only uses lower 32 bits from each vector element. const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnesValue(64), DCI)) + if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(64), DCI)) return SDValue(N, 0); // If the input is an extend_invec and the SimplifyDemandedBits call didn't @@ -51862,7 +51862,7 @@ APInt KnownUndef, KnownZero; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - APInt DemandedElts = APInt::getAllOnesValue(VT.getVectorNumElements()); + APInt DemandedElts = APInt::getAllOnes(VT.getVectorNumElements()); if (TLI.SimplifyDemandedVectorElts(SDValue(N, 0), DemandedElts, KnownUndef, KnownZero, DCI)) return SDValue(N, 0); @@ -52074,8 +52074,7 @@ TargetLowering::DAGCombinerInfo &DCI) { unsigned NumBits = N->getSimpleValueType(0).getSizeInBits(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (TLI.SimplifyDemandedBits(SDValue(N, 0), - APInt::getAllOnesValue(NumBits), DCI)) + if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnes(NumBits), DCI)) return SDValue(N, 0); return SDValue(); diff --git a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp --- a/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp +++ b/llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp @@ -476,7 +476,7 @@ // PACKUS: Truncate signed value with unsigned saturation. // Source values less than zero are saturated to zero. // Source values greater than dst maxuint are saturated to maxuint. - MinValue = APInt::getNullValue(SrcScalarSizeInBits); + MinValue = APInt::getZero(SrcScalarSizeInBits); MaxValue = APInt::getLowBitsSet(SrcScalarSizeInBits, DstScalarSizeInBits); } diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -3740,7 +3740,7 @@ if ((IsLoad && !isLegalMaskedLoad(SrcVTy, Alignment)) || (IsStore && !isLegalMaskedStore(SrcVTy, Alignment))) { // Scalarization - APInt DemandedElts = APInt::getAllOnesValue(NumElem); + APInt DemandedElts = APInt::getAllOnes(NumElem); InstructionCost MaskSplitCost = getScalarizationOverhead(MaskTy, DemandedElts, false, true); InstructionCost ScalarCompareCost = getCmpSelInstrCost( @@ -4653,7 +4653,7 @@ bool VariableMask, Align Alignment, unsigned AddressSpace) { unsigned VF = cast(SrcVTy)->getNumElements(); - APInt DemandedElts = APInt::getAllOnesValue(VF); + APInt DemandedElts = APInt::getAllOnes(VF); TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; InstructionCost MaskUnpackCost = 0; diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp --- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp +++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp @@ -206,8 +206,8 @@ bool FoundAnd1; MaskOps(unsigned BitWidth, bool MatchAnds) - : Root(nullptr), Mask(APInt::getNullValue(BitWidth)), - MatchAndChain(MatchAnds), FoundAnd1(false) {} + : Root(nullptr), Mask(APInt::getZero(BitWidth)), MatchAndChain(MatchAnds), + FoundAnd1(false) {} }; /// This is a recursive helper for foldAnyOrAllBitsSet() that walks through a diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3456,13 +3456,13 @@ // canonicalize to a 'not' before the shift to help SCEV and codegen: // (X << C) ^ RHSC --> ~X << C if (match(Op0, m_OneUse(m_Shl(m_Value(X), m_APInt(C)))) && - *RHSC == APInt::getAllOnesValue(Ty->getScalarSizeInBits()).shl(*C)) { + *RHSC == APInt::getAllOnes(Ty->getScalarSizeInBits()).shl(*C)) { Value *NotX = Builder.CreateNot(X); return BinaryOperator::CreateShl(NotX, ConstantInt::get(Ty, *C)); } // (X >>u C) ^ RHSC --> ~X >>u C if (match(Op0, m_OneUse(m_LShr(m_Value(X), m_APInt(C)))) && - *RHSC == APInt::getAllOnesValue(Ty->getScalarSizeInBits()).lshr(*C)) { + *RHSC == APInt::getAllOnes(Ty->getScalarSizeInBits()).lshr(*C)) { Value *NotX = Builder.CreateNot(X); return BinaryOperator::CreateLShr(NotX, ConstantInt::get(Ty, *C)); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -953,7 +953,7 @@ if (auto *IIFVTy = dyn_cast(II->getType())) { auto VWidth = IIFVTy->getNumElements(); APInt UndefElts(VWidth, 0); - APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); if (Value *V = SimplifyDemandedVectorElts(II, AllOnesEltMask, UndefElts)) { if (V != II) return replaceInstUsesWith(*II, V); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -3746,7 +3746,7 @@ (WidestTy->getScalarSizeInBits() - 1) + (NarrowestTy->getScalarSizeInBits() - 1); APInt MaximalRepresentableShiftAmount = - APInt::getAllOnesValue(XShAmt->getType()->getScalarSizeInBits()); + APInt::getAllOnes(XShAmt->getType()->getScalarSizeInBits()); if (MaximalRepresentableShiftAmount.ult(MaximalPossibleTotalShiftAmount)) return nullptr; @@ -5042,7 +5042,7 @@ static APInt getDemandedBitsLHSMask(ICmpInst &I, unsigned BitWidth) { const APInt *RHS; if (!match(I.getOperand(1), m_APInt(RHS))) - return APInt::getAllOnesValue(BitWidth); + return APInt::getAllOnes(BitWidth); // If this is a normal comparison, it demands all bits. If it is a sign bit // comparison, it only demands the sign bit. @@ -5064,7 +5064,7 @@ return APInt::getBitsSetFrom(BitWidth, RHS->countTrailingZeros()); default: - return APInt::getAllOnesValue(BitWidth); + return APInt::getAllOnes(BitWidth); } } @@ -5228,8 +5228,7 @@ Op0Known, 0)) return &I; - if (SimplifyDemandedBits(&I, 1, APInt::getAllOnesValue(BitWidth), - Op1Known, 0)) + if (SimplifyDemandedBits(&I, 1, APInt::getAllOnes(BitWidth), Op1Known, 0)) return &I; // Given the known and unknown bits, compute a range that the LHS could be diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1265,9 +1265,9 @@ // We want to canonicalize it to 'ult', so we'll need to increment C0, // which again means it must not have any all-ones elements. if (!match(C0, - m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_NE, - APInt::getAllOnesValue( - C0->getType()->getScalarSizeInBits())))) + m_SpecificInt_ICMP( + ICmpInst::Predicate::ICMP_NE, + APInt::getAllOnes(C0->getType()->getScalarSizeInBits())))) return nullptr; // Can't do, have all-ones element[s]. C0 = InstCombiner::AddOne(C0); std::swap(X, Sel1); @@ -2441,7 +2441,7 @@ unsigned NumElts = VecTy->getNumElements(); APInt UndefElts(NumElts, 0); - APInt AllOnesEltMask(APInt::getAllOnesValue(NumElts)); + APInt AllOnesEltMask(APInt::getAllOnes(NumElts)); if (Value *V = SimplifyDemandedVectorElts(&Sel, AllOnesEltMask, UndefElts)) { if (V != &Sel) return replaceInstUsesWith(Sel, V); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineShifts.cpp @@ -41,7 +41,7 @@ (Sh0->getType()->getScalarSizeInBits() - 1) + (Sh1->getType()->getScalarSizeInBits() - 1); APInt MaximalRepresentableShiftAmount = - APInt::getAllOnesValue(ShAmt0->getType()->getScalarSizeInBits()); + APInt::getAllOnes(ShAmt0->getType()->getScalarSizeInBits()); return MaximalRepresentableShiftAmount.uge(MaximalPossibleTotalShiftAmount); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -55,7 +55,7 @@ bool InstCombinerImpl::SimplifyDemandedInstructionBits(Instruction &Inst) { unsigned BitWidth = Inst.getType()->getScalarSizeInBits(); KnownBits Known(BitWidth); - APInt DemandedMask(APInt::getAllOnesValue(BitWidth)); + APInt DemandedMask(APInt::getAllOnes(BitWidth)); Value *V = SimplifyDemandedUseBits(&Inst, DemandedMask, Known, 0, &Inst); @@ -743,7 +743,7 @@ } case Instruction::URem: { KnownBits Known2(BitWidth); - APInt AllOnes = APInt::getAllOnesValue(BitWidth); + APInt AllOnes = APInt::getAllOnes(BitWidth); if (SimplifyDemandedBits(I, 0, AllOnes, Known2, Depth + 1) || SimplifyDemandedBits(I, 1, AllOnes, Known2, Depth + 1)) return I; @@ -1044,8 +1044,8 @@ Known.Zero.setLowBits(ShlAmt - 1); Known.Zero &= DemandedMask; - APInt BitMask1(APInt::getAllOnesValue(BitWidth)); - APInt BitMask2(APInt::getAllOnesValue(BitWidth)); + APInt BitMask1(APInt::getAllOnes(BitWidth)); + APInt BitMask2(APInt::getAllOnes(BitWidth)); bool isLshr = (Shr->getOpcode() == Instruction::LShr); BitMask1 = isLshr ? (BitMask1.lshr(ShrAmt) << ShlAmt) : @@ -1111,7 +1111,7 @@ return nullptr; unsigned VWidth = cast(V->getType())->getNumElements(); - APInt EltMask(APInt::getAllOnesValue(VWidth)); + APInt EltMask(APInt::getAllOnes(VWidth)); assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); if (match(V, m_Undef())) { @@ -1538,8 +1538,8 @@ // Subtlety: If we load from a pointer, the pointer must be valid // regardless of whether the element is demanded. Doing otherwise risks // segfaults which didn't exist in the original program. - APInt DemandedPtrs(APInt::getAllOnesValue(VWidth)), - DemandedPassThrough(DemandedElts); + APInt DemandedPtrs(APInt::getAllOnes(VWidth)), + DemandedPassThrough(DemandedElts); if (auto *CV = dyn_cast(II->getOperand(2))) for (unsigned i = 0; i < VWidth; i++) { Constant *CElt = CV->getAggregateElement(i); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp --- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp @@ -282,7 +282,7 @@ unsigned VWidth = cast(V->getType())->getNumElements(); // Conservatively assume that all elements are needed. - APInt UsedElts(APInt::getAllOnesValue(VWidth)); + APInt UsedElts(APInt::getAllOnes(VWidth)); switch (UserInstr->getOpcode()) { case Instruction::ExtractElement: { @@ -330,11 +330,11 @@ if (Instruction *I = dyn_cast(U.getUser())) { UnionUsedElts |= findDemandedEltsBySingleUser(V, I); } else { - UnionUsedElts = APInt::getAllOnesValue(VWidth); + UnionUsedElts = APInt::getAllOnes(VWidth); break; } - if (UnionUsedElts.isAllOnesValue()) + if (UnionUsedElts.isAllOnes()) break; } @@ -396,7 +396,7 @@ // If the input vector has multiple uses, simplify it based on a union // of all elements used. APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec); - if (!DemandedElts.isAllOnesValue()) { + if (!DemandedElts.isAllOnes()) { APInt UndefElts(NumElts, 0); if (Value *V = SimplifyDemandedVectorElts( SrcVec, DemandedElts, UndefElts, 0 /* Depth */, @@ -1503,7 +1503,7 @@ if (auto VecTy = dyn_cast(VecOp->getType())) { unsigned VWidth = VecTy->getNumElements(); APInt UndefElts(VWidth, 0); - APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); if (Value *V = SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts)) { if (V != &IE) return replaceInstUsesWith(IE, V); @@ -2452,7 +2452,7 @@ return I; APInt UndefElts(VWidth, 0); - APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); if (Value *V = SimplifyDemandedVectorElts(&SVI, AllOnesEltMask, UndefElts)) { if (V != &SVI) return replaceInstUsesWith(SVI, V); diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -1906,7 +1906,7 @@ if (auto *GEPFVTy = dyn_cast(GEPType)) { auto VWidth = GEPFVTy->getNumElements(); APInt UndefElts(VWidth, 0); - APInt AllOnesEltMask(APInt::getAllOnesValue(VWidth)); + APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); if (Value *V = SimplifyDemandedVectorElts(&GEP, AllOnesEltMask, UndefElts)) { if (V != &GEP) diff --git a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp --- a/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp +++ b/llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp @@ -690,7 +690,7 @@ // sdiv/srem is UB if divisor is -1 and divident is INT_MIN, so unless we can // prove that such a combination is impossible, we need to bump the bitwidth. - if (CRs[1]->contains(APInt::getAllOnesValue(OrigWidth)) && + if (CRs[1]->contains(APInt::getAllOnes(OrigWidth)) && CRs[0]->contains( APInt::getSignedMinValue(MinSignedBits).sextOrSelf(OrigWidth))) ++MinSignedBits; diff --git a/llvm/lib/Transforms/Scalar/Float2Int.cpp b/llvm/lib/Transforms/Scalar/Float2Int.cpp --- a/llvm/lib/Transforms/Scalar/Float2Int.cpp +++ b/llvm/lib/Transforms/Scalar/Float2Int.cpp @@ -256,7 +256,7 @@ Op = [](ArrayRef Ops) { assert(Ops.size() == 1 && "FNeg is a unary operator!"); unsigned Size = Ops[0].getBitWidth(); - auto Zero = ConstantRange(APInt::getNullValue(Size)); + auto Zero = ConstantRange(APInt::getZero(Size)); return Zero.sub(Ops[0]); }; break; diff --git a/llvm/lib/Transforms/Scalar/Reassociate.cpp b/llvm/lib/Transforms/Scalar/Reassociate.cpp --- a/llvm/lib/Transforms/Scalar/Reassociate.cpp +++ b/llvm/lib/Transforms/Scalar/Reassociate.cpp @@ -140,7 +140,7 @@ // view the operand as "V | 0" SymbolicPart = V; - ConstPart = APInt::getNullValue(V->getType()->getScalarSizeInBits()); + ConstPart = APInt::getZero(V->getType()->getScalarSizeInBits()); isOr = true; } @@ -1361,7 +1361,7 @@ APInt C3((~C1) ^ C2); // Do not increase code size! - if (!C3.isNullValue() && !C3.isAllOnesValue()) { + if (!C3.isZero() && !C3.isAllOnes()) { int NewInstNum = ConstOpnd.getBoolValue() ? 1 : 2; if (NewInstNum > DeadInstNum) return false; @@ -1377,7 +1377,7 @@ APInt C3 = C1 ^ C2; // Do not increase code size - if (!C3.isNullValue() && !C3.isAllOnesValue()) { + if (!C3.isZero() && !C3.isAllOnes()) { int NewInstNum = ConstOpnd.getBoolValue() ? 1 : 2; if (NewInstNum > DeadInstNum) return false; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -3159,7 +3159,7 @@ // Now, is the bit permutation correct for a bswap or a bitreverse? We can // only byteswap values with an even number of bytes. - APInt DemandedMask = APInt::getAllOnesValue(DemandedBW); + APInt DemandedMask = APInt::getAllOnes(DemandedBW); bool OKForBSwap = MatchBSwaps && (DemandedBW % 16) == 0; bool OKForBitReverse = MatchBitReversals; for (unsigned BitIdx = 0; diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp --- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -2468,7 +2468,7 @@ Value *StartValue = expandCodeForImpl(Start, ARTy, Loc, false); ConstantInt *Zero = - ConstantInt::get(Loc->getContext(), APInt::getNullValue(DstBits)); + ConstantInt::get(Loc->getContext(), APInt::getZero(DstBits)); Builder.SetInsertPoint(Loc); // Compute |Step| diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -6898,7 +6898,7 @@ if (isScalarWithPredication(I) && !I->getType()->isVoidTy()) { ScalarCost += TTI.getScalarizationOverhead( cast(ToVectorTy(I->getType(), VF)), - APInt::getAllOnesValue(VF.getFixedValue()), true, false); + APInt::getAllOnes(VF.getFixedValue()), true, false); ScalarCost += VF.getFixedValue() * TTI.getCFInstrCost(Instruction::PHI, TTI::TCK_RecipThroughput); @@ -6917,7 +6917,7 @@ else if (needsExtract(J, VF)) { ScalarCost += TTI.getScalarizationOverhead( cast(ToVectorTy(J->getType(), VF)), - APInt::getAllOnesValue(VF.getFixedValue()), false, true); + APInt::getAllOnes(VF.getFixedValue()), false, true); } } @@ -7063,7 +7063,7 @@ auto *Vec_i1Ty = VectorType::get(IntegerType::getInt1Ty(ValTy->getContext()), VF); Cost += TTI.getScalarizationOverhead( - Vec_i1Ty, APInt::getAllOnesValue(VF.getKnownMinValue()), + Vec_i1Ty, APInt::getAllOnes(VF.getKnownMinValue()), /*Insert=*/false, /*Extract=*/true); Cost += TTI.getCFInstrCost(Instruction::Br, TTI::TCK_RecipThroughput); @@ -7405,8 +7405,8 @@ if (!RetTy->isVoidTy() && (!isa(I) || !TTI.supportsEfficientVectorElementLoadStore())) Cost += TTI.getScalarizationOverhead( - cast(RetTy), APInt::getAllOnesValue(VF.getKnownMinValue()), - true, false); + cast(RetTy), APInt::getAllOnes(VF.getKnownMinValue()), true, + false); // Some targets keep addresses scalar. if (isa(I) && !TTI.prefersVectorizedAddressing()) @@ -7657,8 +7657,7 @@ VectorType::get(IntegerType::getInt1Ty(RetTy->getContext()), VF); return ( TTI.getScalarizationOverhead( - Vec_i1Ty, APInt::getAllOnesValue(VF.getFixedValue()), false, - true) + + Vec_i1Ty, APInt::getAllOnes(VF.getFixedValue()), false, true) + (TTI.getCFInstrCost(Instruction::Br, CostKind) * VF.getFixedValue())); } else if (I->getParent() == TheLoop->getLoopLatch() || VF.isScalar()) // The back-edge branch will remain, as will all scalar branches. diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -3899,7 +3899,7 @@ unsigned const NumElts = SrcVecTy->getNumElements(); unsigned const NumScalars = VL.size(); - APInt DemandedElts = APInt::getNullValue(NumElts); + APInt DemandedElts = APInt::getZero(NumElts); // TODO: Add support for Instruction::InsertValue. unsigned Offset = UINT_MAX; bool IsIdentity = true; @@ -4525,7 +4525,7 @@ VF.push_back(FTy->getNumElements()); ShuffleMask.emplace_back(VF.back(), UndefMaskElem); FirstUsers.push_back(EU.User); - DemandedElts.push_back(APInt::getNullValue(VF.back())); + DemandedElts.push_back(APInt::getZero(VF.back())); VecId = FirstUsers.size() - 1; } else { VecId = std::distance(FirstUsers.begin(), It); @@ -4759,7 +4759,7 @@ BoUpSLP::getGatherCost(FixedVectorType *Ty, const DenseSet &ShuffledIndices) const { unsigned NumElts = Ty->getNumElements(); - APInt DemandedElts = APInt::getNullValue(NumElts); + APInt DemandedElts = APInt::getZero(NumElts); for (unsigned I = 0; I < NumElts; ++I) if (!ShuffledIndices.count(I)) DemandedElts.setBit(I); diff --git a/llvm/tools/llvm-stress/llvm-stress.cpp b/llvm/tools/llvm-stress/llvm-stress.cpp --- a/llvm/tools/llvm-stress/llvm-stress.cpp +++ b/llvm/tools/llvm-stress/llvm-stress.cpp @@ -452,10 +452,10 @@ switch (getRandom() % 7) { case 0: return PT->push_back(ConstantInt::get( - Ty, APInt::getAllOnesValue(Ty->getPrimitiveSizeInBits()))); + Ty, APInt::getAllOnes(Ty->getPrimitiveSizeInBits()))); case 1: - return PT->push_back(ConstantInt::get( - Ty, APInt::getNullValue(Ty->getPrimitiveSizeInBits()))); + return PT->push_back( + ConstantInt::get(Ty, APInt::getZero(Ty->getPrimitiveSizeInBits()))); case 2: case 3: case 4: diff --git a/llvm/unittests/ADT/APIntTest.cpp b/llvm/unittests/ADT/APIntTest.cpp --- a/llvm/unittests/ADT/APIntTest.cpp +++ b/llvm/unittests/ADT/APIntTest.cpp @@ -26,7 +26,7 @@ // Test that APInt shift left works when bitwidth > 64 and shiftamt == 0 TEST(APIntTest, ShiftLeftByZero) { - APInt One = APInt::getNullValue(65) + 1; + APInt One = APInt::getZero(65) + 1; APInt Shl = One.shl(0); EXPECT_TRUE(Shl[0]); EXPECT_FALSE(Shl[1]); @@ -102,7 +102,7 @@ } TEST(APIntTest, i128_PositiveCount) { - APInt u128max = APInt::getAllOnesValue(128); + APInt u128max = APInt::getAllOnes(128); EXPECT_EQ(128u, u128max.countLeadingOnes()); EXPECT_EQ(0u, u128max.countLeadingZeros()); EXPECT_EQ(128u, u128max.getActiveBits()); @@ -2323,7 +2323,7 @@ } TEST(APIntTest, clearLowBits) { - APInt i64hi32 = APInt::getAllOnesValue(64); + APInt i64hi32 = APInt::getAllOnes(64); i64hi32.clearLowBits(32); EXPECT_EQ(32u, i64hi32.countLeadingOnes()); EXPECT_EQ(0u, i64hi32.countLeadingZeros()); @@ -2332,7 +2332,7 @@ EXPECT_EQ(0u, i64hi32.countTrailingOnes()); EXPECT_EQ(32u, i64hi32.countPopulation()); - APInt i128hi64 = APInt::getAllOnesValue(128); + APInt i128hi64 = APInt::getAllOnes(128); i128hi64.clearLowBits(64); EXPECT_EQ(64u, i128hi64.countLeadingOnes()); EXPECT_EQ(0u, i128hi64.countLeadingZeros()); @@ -2341,7 +2341,7 @@ EXPECT_EQ(0u, i128hi64.countTrailingOnes()); EXPECT_EQ(64u, i128hi64.countPopulation()); - APInt i128hi24 = APInt::getAllOnesValue(128); + APInt i128hi24 = APInt::getAllOnes(128); i128hi24.clearLowBits(104); EXPECT_EQ(24u, i128hi24.countLeadingOnes()); EXPECT_EQ(0u, i128hi24.countLeadingZeros()); @@ -2350,7 +2350,7 @@ EXPECT_EQ(0u, i128hi24.countTrailingOnes()); EXPECT_EQ(24u, i128hi24.countPopulation()); - APInt i128hi104 = APInt::getAllOnesValue(128); + APInt i128hi104 = APInt::getAllOnes(128); i128hi104.clearLowBits(24); EXPECT_EQ(104u, i128hi104.countLeadingOnes()); EXPECT_EQ(0u, i128hi104.countLeadingZeros()); @@ -2359,7 +2359,7 @@ EXPECT_EQ(0u, i128hi104.countTrailingOnes()); EXPECT_EQ(104u, i128hi104.countPopulation()); - APInt i128hi0 = APInt::getAllOnesValue(128); + APInt i128hi0 = APInt::getAllOnes(128); i128hi0.clearLowBits(128); EXPECT_EQ(0u, i128hi0.countLeadingOnes()); EXPECT_EQ(128u, i128hi0.countLeadingZeros()); @@ -2368,7 +2368,7 @@ EXPECT_EQ(0u, i128hi0.countTrailingOnes()); EXPECT_EQ(0u, i128hi0.countPopulation()); - APInt i80hi1 = APInt::getAllOnesValue(80); + APInt i80hi1 = APInt::getAllOnes(80); i80hi1.clearLowBits(79); EXPECT_EQ(1u, i80hi1.countLeadingOnes()); EXPECT_EQ(0u, i80hi1.countLeadingZeros()); @@ -2377,7 +2377,7 @@ EXPECT_EQ(0u, i80hi1.countTrailingOnes()); EXPECT_EQ(1u, i80hi1.countPopulation()); - APInt i32hi16 = APInt::getAllOnesValue(32); + APInt i32hi16 = APInt::getAllOnes(32); i32hi16.clearLowBits(16); EXPECT_EQ(16u, i32hi16.countLeadingOnes()); EXPECT_EQ(0u, i32hi16.countLeadingZeros()); @@ -2484,7 +2484,7 @@ // Ensure we handle large shifts of multi-word. const APInt signmin32(APInt::getSignedMinValue(32)); - EXPECT_TRUE(signmin32.ashr(32).isAllOnesValue()); + EXPECT_TRUE(signmin32.ashr(32).isAllOnes()); // Ensure we handle large shifts of multi-word. const APInt umax32(APInt::getSignedMaxValue(32)); @@ -2492,7 +2492,7 @@ // Ensure we handle large shifts of multi-word. const APInt signmin128(APInt::getSignedMinValue(128)); - EXPECT_TRUE(signmin128.ashr(128).isAllOnesValue()); + EXPECT_TRUE(signmin128.ashr(128).isAllOnes()); // Ensure we handle large shifts of multi-word. const APInt umax128(APInt::getSignedMaxValue(128)); diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp --- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -1109,7 +1109,7 @@ KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg()); // We don't know what the result of the load is, so we don't know any ones. - EXPECT_TRUE(Res.One.isNullValue()); + EXPECT_TRUE(Res.One.isZero()); // We know that the value is in [0, 2). So, we don't know if the first bit // is 0 or not. However, we do know that every other bit must be 0. @@ -1601,11 +1601,11 @@ // We don't know what the result of the shift is, but we should not crash - EXPECT_TRUE(EqSizeRes.One.isNullValue()); - EXPECT_TRUE(EqSizeRes.Zero.isNullValue()); + EXPECT_TRUE(EqSizeRes.One.isZero()); + EXPECT_TRUE(EqSizeRes.Zero.isZero()); - EXPECT_TRUE(BiggerSizeRes.One.isNullValue()); - EXPECT_TRUE(BiggerSizeRes.Zero.isNullValue()); + EXPECT_TRUE(BiggerSizeRes.One.isZero()); + EXPECT_TRUE(BiggerSizeRes.Zero.isZero()); } TEST_F(AArch64GISelMITest, TestKnownBitsAssertZext) { diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp --- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp @@ -1016,7 +1016,7 @@ GISelKnownBits Info(*MF); KnownBits Res = Info.getKnownBits(And->getOperand(1).getReg()); - EXPECT_TRUE(Res.One.isNullValue()); + EXPECT_TRUE(Res.One.isZero()); APInt Mask(Res.getBitWidth(), 1); Mask.flipAllBits(); @@ -1454,11 +1454,11 @@ KnownBits EqSizeRes = Info.getKnownBits(EqSizedShl); KnownBits BiggerSizeRes = Info.getKnownBits(BiggerSizedShl); - EXPECT_TRUE(EqSizeRes.One.isNullValue()); - EXPECT_TRUE(EqSizeRes.Zero.isNullValue()); + EXPECT_TRUE(EqSizeRes.One.isZero()); + EXPECT_TRUE(EqSizeRes.Zero.isZero()); - EXPECT_TRUE(BiggerSizeRes.One.isNullValue()); - EXPECT_TRUE(BiggerSizeRes.Zero.isNullValue()); + EXPECT_TRUE(BiggerSizeRes.One.isZero()); + EXPECT_TRUE(BiggerSizeRes.Zero.isZero()); } TEST_F(AArch64GISelMITest, TestKnownBitsVectorAssertZext) { diff --git a/llvm/unittests/IR/ConstantRangeTest.cpp b/llvm/unittests/IR/ConstantRangeTest.cpp --- a/llvm/unittests/IR/ConstantRangeTest.cpp +++ b/llvm/unittests/IR/ConstantRangeTest.cpp @@ -1969,7 +1969,7 @@ EXPECT_MAY_OVERFLOW(Empty.unsignedAddMayOverflow(Some)); // Never overflow despite one full/wrap set. - ConstantRange Zero(APInt::getNullValue(16)); + ConstantRange Zero(APInt::getZero(16)); EXPECT_NEVER_OVERFLOWS(Full.unsignedAddMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Wrap.unsignedAddMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Zero.unsignedAddMayOverflow(Full)); @@ -2003,8 +2003,8 @@ EXPECT_MAY_OVERFLOW(Empty.unsignedSubMayOverflow(Some)); // Never overflow despite one full/wrap set. - ConstantRange Zero(APInt::getNullValue(16)); - ConstantRange Max(APInt::getAllOnesValue(16)); + ConstantRange Zero(APInt::getZero(16)); + ConstantRange Max(APInt::getAllOnes(16)); EXPECT_NEVER_OVERFLOWS(Full.unsignedSubMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Wrap.unsignedSubMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Max.unsignedSubMayOverflow(Full)); @@ -2038,7 +2038,7 @@ EXPECT_MAY_OVERFLOW(Empty.signedAddMayOverflow(Some)); // Never overflow despite one full/wrap set. - ConstantRange Zero(APInt::getNullValue(16)); + ConstantRange Zero(APInt::getZero(16)); EXPECT_NEVER_OVERFLOWS(Full.signedAddMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Wrap.signedAddMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Zero.signedAddMayOverflow(Full)); @@ -2090,7 +2090,7 @@ EXPECT_MAY_OVERFLOW(Empty.signedSubMayOverflow(Some)); // Never overflow despite one full/wrap set. - ConstantRange Zero(APInt::getNullValue(16)); + ConstantRange Zero(APInt::getZero(16)); EXPECT_NEVER_OVERFLOWS(Full.signedSubMayOverflow(Zero)); EXPECT_NEVER_OVERFLOWS(Wrap.signedSubMayOverflow(Zero)); @@ -2474,18 +2474,14 @@ PreferSmallest); TestUnaryOpExhaustive( [](const ConstantRange &CR) { - return CR.binaryXor( - ConstantRange(APInt::getAllOnesValue(CR.getBitWidth()))); + return CR.binaryXor(ConstantRange(APInt::getAllOnes(CR.getBitWidth()))); }, - [](const APInt &N) { return ~N; }, - PreferSmallest); + [](const APInt &N) { return ~N; }, PreferSmallest); TestUnaryOpExhaustive( [](const ConstantRange &CR) { - return ConstantRange(APInt::getAllOnesValue(CR.getBitWidth())) - .binaryXor(CR); + return ConstantRange(APInt::getAllOnes(CR.getBitWidth())).binaryXor(CR); }, - [](const APInt &N) { return ~N; }, - PreferSmallest); + [](const APInt &N) { return ~N; }, PreferSmallest); } } // anonymous namespace diff --git a/llvm/unittests/IR/PatternMatch.cpp b/llvm/unittests/IR/PatternMatch.cpp --- a/llvm/unittests/IR/PatternMatch.cpp +++ b/llvm/unittests/IR/PatternMatch.cpp @@ -1469,8 +1469,8 @@ TEST_F(PatternMatchTest, ConstantPredicateType) { // Scalar integer - APInt U32Max = APInt::getAllOnesValue(32); - APInt U32Zero = APInt::getNullValue(32); + APInt U32Max = APInt::getAllOnes(32); + APInt U32Zero = APInt::getZero(32); APInt U32DeadBeef(32, 0xDEADBEEF); Type *U32Ty = Type::getInt32Ty(Ctx); diff --git a/llvm/unittests/Support/KnownBitsTest.cpp b/llvm/unittests/Support/KnownBitsTest.cpp --- a/llvm/unittests/Support/KnownBitsTest.cpp +++ b/llvm/unittests/Support/KnownBitsTest.cpp @@ -464,8 +464,8 @@ unsigned Bits = 4; for (unsigned FromBits = 1; FromBits <= Bits; ++FromBits) { ForeachKnownBits(Bits, [&](const KnownBits &Known) { - APInt CommonOne = APInt::getAllOnesValue(Bits); - APInt CommonZero = APInt::getAllOnesValue(Bits); + APInt CommonOne = APInt::getAllOnes(Bits); + APInt CommonZero = APInt::getAllOnes(Bits); unsigned ExtBits = Bits - FromBits; ForeachNumInKnownBits(Known, [&](const APInt &N) { APInt Ext = N << ExtBits; diff --git a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp --- a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp +++ b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp @@ -254,7 +254,7 @@ // tosa::BitwiseNotOp if (isa(op) && elementTy.isa()) { auto allOnesAttr = rewriter.getIntegerAttr( - elementTy, APInt::getAllOnesValue(elementTy.getIntOrFloatBitWidth())); + elementTy, APInt::getAllOnes(elementTy.getIntOrFloatBitWidth())); auto allOnes = rewriter.create(loc, allOnesAttr); return rewriter.create(loc, resultTypes, args[0], allOnes); } @@ -739,10 +739,10 @@ elementTy, APInt::getSignedMinValue(elementTy.getIntOrFloatBitWidth())); if (isa(op) && elementTy.isInteger(1)) - return rewriter.getIntegerAttr(elementTy, APInt::getAllOnesValue(1)); + return rewriter.getIntegerAttr(elementTy, APInt::getAllOnes(1)); if (isa(op) && elementTy.isInteger(1)) - return rewriter.getIntegerAttr(elementTy, APInt::getNullValue(1)); + return rewriter.getIntegerAttr(elementTy, APInt::getZero(1)); if (isa(op) && elementTy.isa()) return rewriter.getFloatAttr( diff --git a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp --- a/mlir/lib/Dialect/StandardOps/IR/Ops.cpp +++ b/mlir/lib/Dialect/StandardOps/IR/Ops.cpp @@ -288,8 +288,7 @@ return rhs(); /// and(x, allOnes) -> x APInt intValue; - if (matchPattern(rhs(), m_ConstantInt(&intValue)) && - intValue.isAllOnesValue()) + if (matchPattern(rhs(), m_ConstantInt(&intValue)) && intValue.isAllOnes()) return lhs(); /// and(x,x) -> x if (lhs() == rhs()) @@ -1774,7 +1773,7 @@ return a; } unsigned bits = a.getBitWidth(); - APInt zero = APInt::getNullValue(bits); + APInt zero = APInt::getZero(bits); if (a.sge(zero) && b.sgt(zero)) { // Both positive (or a is zero), return a / b. return a.sdiv_ov(b, overflowOrDiv0); @@ -1824,7 +1823,7 @@ return a; } unsigned bits = a.getBitWidth(); - APInt zero = APInt::getNullValue(bits); + APInt zero = APInt::getZero(bits); if (a.sgt(zero) && b.sgt(zero)) { // Both positive, return ceil(a, b). return signedCeilNonnegInputs(a, b, overflowOrDiv0); diff --git a/mlir/lib/IR/BuiltinAttributes.cpp b/mlir/lib/IR/BuiltinAttributes.cpp --- a/mlir/lib/IR/BuiltinAttributes.cpp +++ b/mlir/lib/IR/BuiltinAttributes.cpp @@ -1380,7 +1380,7 @@ /// Get a zero APInt for the given sparse attribute. APInt SparseElementsAttr::getZeroAPInt() const { auto eltType = getType().getElementType().cast(); - return APInt::getNullValue(eltType.getWidth()); + return APInt::getZero(eltType.getWidth()); } /// Get a zero attribute for the given attribute type.