Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -261,11 +261,6 @@ def AArch64splice : SDNode<"AArch64ISD::SPLICE", SDT_AArch64Arith>; -def step_vector_oneuse : PatFrag<(ops node:$idx), - (step_vector node:$idx), [{ - return N->hasOneUse(); -}]>; - def reinterpret_cast : SDNode<"AArch64ISD::REINTERPRET_CAST", SDTUnaryOp>; def AArch64mul_p_oneuse : PatFrag<(ops node:$pred, node:$src1, node:$src2), @@ -1477,10 +1472,10 @@ defm INCP_ZP : sve_int_count_v<0b10000, "incp">; defm DECP_ZP : sve_int_count_v<0b10100, "decp">; - defm INDEX_RR : sve_int_index_rr<"index", step_vector, step_vector_oneuse, AArch64mul_p_oneuse>; - defm INDEX_IR : sve_int_index_ir<"index", step_vector, step_vector_oneuse, AArch64mul_p, AArch64mul_p_oneuse>; - defm INDEX_RI : sve_int_index_ri<"index", step_vector, step_vector_oneuse>; - defm INDEX_II : sve_int_index_ii<"index", step_vector, step_vector_oneuse>; + defm INDEX_RR : sve_int_index_rr<"index", AArch64mul_p_oneuse>; + defm INDEX_IR : sve_int_index_ir<"index", AArch64mul_p, AArch64mul_p_oneuse>; + defm INDEX_RI : sve_int_index_ri<"index">; + defm INDEX_II : sve_int_index_ii<"index">; // Unpredicated shifts defm ASR_ZZI : sve_int_bin_cons_shift_imm_right<0b00, "asr", AArch64asr_p>; Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -274,6 +274,12 @@ return N->hasOneUse(); }]>; +def step_vector_oneuse : PatFrag<(ops node:$idx), + (step_vector node:$idx), [{ + return N->hasOneUse(); +}]>; + + //===----------------------------------------------------------------------===// // SVE PTrue - These are used extensively throughout the pattern matching so // it's important we define them first. @@ -4986,7 +4992,7 @@ let Inst{4-0} = Zd; } -multiclass sve_int_index_ii { +multiclass sve_int_index_ii { def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_8b>; def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_16b>; def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>; @@ -5029,7 +5035,7 @@ let Inst{4-0} = Zd; } -multiclass sve_int_index_ir { +multiclass sve_int_index_ir { def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_8b>; def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_16b>; def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>; @@ -5096,7 +5102,7 @@ let Inst{4-0} = Zd; } -multiclass sve_int_index_ri { +multiclass sve_int_index_ri { def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_8b>; def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_16b>; def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>; @@ -5130,7 +5136,7 @@ let Inst{4-0} = Zd; } -multiclass sve_int_index_rr { +multiclass sve_int_index_rr { def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>; def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>; def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;