Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h =================================================================== --- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h +++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.h @@ -42,8 +42,8 @@ bool UpdateARM64SVERegistersInfos(uint64_t vg); void Finalize(const lldb_private::ArchSpec &arch); - void PreFinalize_x86_64(); - void PostFinalize_x86_64(); + void PreFinalize_x86(const lldb_private::ArchSpec &arch); + void PostFinalize_x86(); }; class GDBRemoteRegisterContext : public RegisterContext { Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp =================================================================== --- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp +++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext.cpp @@ -1107,8 +1107,9 @@ return; switch (arch.GetMachine()) { + case llvm::Triple::x86: case llvm::Triple::x86_64: - PreFinalize_x86_64(); + PreFinalize_x86(arch); break; default: @@ -1118,8 +1119,9 @@ DynamicRegisterInfo::Finalize(arch); switch (arch.GetMachine()) { + case llvm::Triple::x86: case llvm::Triple::x86_64: - PostFinalize_x86_64(); + PostFinalize_x86(); break; default: Index: lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext_x86.cpp =================================================================== --- lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext_x86.cpp +++ lldb/source/Plugins/Process/gdb-remote/GDBRemoteRegisterContext_x86.cpp @@ -102,7 +102,7 @@ {"ymm15", "xmm15", "ymm15h"}, }}; -void GDBRemoteDynamicRegisterInfo::PreFinalize_x86_64() { +void GDBRemoteDynamicRegisterInfo::PreFinalize_x86(const ArchSpec &arch) { uint32_t max_regnum = 0; uint32_t next_regindex = m_regs.size(); for (const RegisterInfo ® : m_regs) @@ -112,14 +112,34 @@ group.SetCString("partial registers"); for (PartialGPRRegSet &partial_regset : partial_gpr_regs) { - const RegisterInfo *reg64 = GetRegisterInfo(partial_regset.reg64); - if (!reg64 || reg64->byte_size != 8) + const RegisterInfo *base_reg; + uint32_t base_size; + int first_subreg; + + switch (arch.GetMachine()) { + case llvm::Triple::x86: + base_reg = GetRegisterInfo(partial_regset.r[0].name); + base_size = 4; + first_subreg = eRegKind16; + break; + + case llvm::Triple::x86_64: + base_reg = GetRegisterInfo(partial_regset.reg64); + base_size = 8; + first_subreg = eRegKind32; + break; + + default: + llvm_unreachable("unexpected arch"); + } + + if (!base_reg || base_reg->byte_size != base_size) continue; const RegisterInfo *reginfo[eRegKindCount]; uint32_t regno[eRegKindCount]; - for (int i = 0; i < eRegKindCount; i++) { + for (int i = first_subreg; i < eRegKindCount; i++) { if (!partial_regset.r[i].name) continue; @@ -130,16 +150,16 @@ regno[i] = ++max_regnum; } - for (int i = 0; i < eRegKindCount; i++) { + for (int i = first_subreg; i < eRegKindCount; i++) { if (!partial_regset.r[i].name) continue; partial_regset.r[i].value_regs[0] = - reg64->kinds[eRegisterKindProcessPlugin]; + base_reg->kinds[eRegisterKindProcessPlugin]; partial_regset.r[i].value_regs[1] = LLDB_INVALID_REGNUM; int k = 0; - for (int j = 0; j < eRegKindCount; j++) { + for (int j = first_subreg; j < eRegKindCount; j++) { if (i != j && partial_regset.r[j].name) partial_regset.r[i].invalidate_regs[k++] = regno[j]; } @@ -147,7 +167,7 @@ struct RegisterInfo new_reg { partial_regset.r[i].name, nullptr, partial_gpr_sizes[i], - LLDB_INVALID_INDEX32, reg64->encoding, reg64->format, + LLDB_INVALID_INDEX32, base_reg->encoding, base_reg->format, { LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, regno[i], @@ -193,10 +213,9 @@ for (YMMReg &ymmreg : ymm_regs) { const RegisterInfo *xmmreg = GetRegisterInfo(ymmreg.xmmreg); const RegisterInfo *ymmhreg = GetRegisterInfo(ymmreg.ymmhreg); - if (!xmmreg || !ymmhreg) + if (!xmmreg || !ymmhreg || xmmreg->byte_size != 16 || + ymmhreg->byte_size != 16) continue; - assert(xmmreg->byte_size == 16); - assert(ymmhreg->byte_size == 16); if (GetRegisterInfo(ymmreg.name)) continue; @@ -222,7 +241,7 @@ } } -void GDBRemoteDynamicRegisterInfo::PostFinalize_x86_64() { +void GDBRemoteDynamicRegisterInfo::PostFinalize_x86() { for (PartialGPRRegSet &partial_regset : partial_gpr_regs) { if (!partial_regset.r[eRegKind8h].name) continue; Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py =================================================================== --- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py +++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py @@ -385,11 +385,112 @@ # test generic aliases self.match("register read fp", ["ebp = 0x54535251"]) + self.match("register read sp", + ["esp = 0x44434241"]) self.match("register read pc", ["eip = 0x84838281"]) self.match("register read flags", ["eflags = 0x94939291"]) + # test pseudo-registers + self.match("register read cx", + ["cx = 0x1211"]) + self.match("register read ch", + ["ch = 0x12"]) + self.match("register read cl", + ["cl = 0x11"]) + self.match("register read mm0", + ["mm0 = 0x0807060504030201"]) + self.match("register read mm1", + ["mm1 = 0x1817161514131211"]) + + # both stX and xmmX should be displayed as vectors + self.match("register read st0", + ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) + self.match("register read st1", + ["st1 = {0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a}"]) + self.match("register read xmm0", + ["xmm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 " + "0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90}"]) + self.match("register read xmm1", + ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " + "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) + + # test recombining ymmX + self.match("register read ymm0h", + ["ymm0h = {0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 " + "0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) + self.match("register read ymm0", + ["ymm0 = {0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a " + "0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0xb1 0xb2 0xb3 0xb4 0xb5 " + "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) + self.match("register read ymm1h", + ["ymm1h = {0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 " + "0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0}"]) + self.match("register read ymm1", + ["ymm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a " + "0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xc1 0xc2 0xc3 0xc4 0xc5 " + "0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0}"]) + + # test writing into pseudo-registers + self.runCmd("register write cx 0xfbfa") + reg_data[1] = "fafb1314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ecx", + ["ecx = 0x1413fbfa"]) + + self.runCmd("register write ch 0xf9") + reg_data[1] = "faf91314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9fa"]) + self.match("register read ecx", + ["ecx = 0x1413f9fa"]) + + self.runCmd("register write cl 0xf8") + reg_data[1] = "f8f91314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9f8"]) + self.match("register read ecx", + ["ecx = 0x1413f9f8"]) + + self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") + reg_data[10] = "f8f9fafbfcfdfeff090a" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read st0", + ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) + + self.runCmd("register write xmm0 \"{0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 " + "0xf8 0xf7 0xf6 0xf5 0xf4 0xf3 0xf2 0xf1 0xf0}\"") + reg_data[18] = "fffefdfcfbfaf9f8f7f6f5f4f3f2f1f0" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ymm0", + ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " + "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xb1 0xb2 0xb3 0xb4 0xb5 " + "0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0}"]) + + self.runCmd("register write ymm0h \"{0xef 0xee 0xed 0xec 0xeb 0xea 0xe9 " + "0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}\"") + reg_data[27] = "efeeedecebeae9e8e7e6e5e4e3e2e1e0" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ymm0", + ["ymm0 = {0xff 0xfe 0xfd 0xfc 0xfb 0xfa 0xf9 0xf8 0xf7 0xf6 " + "0xf5 0xf4 0xf3 0xf2 0xf1 0xf0 0xef 0xee 0xed 0xec 0xeb " + "0xea 0xe9 0xe8 0xe7 0xe6 0xe5 0xe4 0xe3 0xe2 0xe1 0xe0}"]) + + self.runCmd("register write ymm0 \"{0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 " + "0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 " + "0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec " + "0xed 0xee 0xef}\"") + reg_data[18] = "d0d1d2d3d4d5d6d7d8d9dadbdcdddedf" + reg_data[27] = "e0e1e2e3e4e5e6e7e8e9eaebecedeeef" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ymm0", + ["ymm0 = {0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 " + "0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 " + "0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef}"]) + @skipIfXmlSupportMissing @skipIfRemote @skipIfLLVMTargetMissing("AArch64")