diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -1526,7 +1526,8 @@ STI); OutStreamer->emitInstruction( MCInstBuilder(X86::JMP_1) - .addExpr(MCSymbolRefExpr::create(ReportError, OutContext)), + .addExpr(MCSymbolRefExpr::create(ReportError, MCSymbolRefExpr::VK_PLT, + OutContext)), STI); } diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll --- a/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll +++ b/llvm/test/CodeGen/X86/asan-check-memaccess-add.ll @@ -166,7 +166,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store1 +; CHECK-NEXT: jmp __asan_report_store1@PLT ; CHECK: .type __asan_check_store2_rn[[RN2]],@function ; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]] @@ -188,7 +188,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store2 +; CHECK-NEXT: jmp __asan_report_store2@PLT ; CHECK: .type __asan_check_store4_rn[[RN4]],@function ; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]] @@ -210,7 +210,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store4 +; CHECK-NEXT: jmp __asan_report_store4@PLT ; CHECK: .type __asan_check_store8_rn[[RN8]],@function ; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]] @@ -224,7 +224,7 @@ ; CHECK-NEXT: retq ; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store8 +; CHECK-NEXT: jmp __asan_report_store8PLT ; CHECK: .type __asan_check_store16_rn[[RN16]],@function ; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]] @@ -238,6 +238,6 @@ ; CHECK-NEXT: retq ; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store16 +; CHECK-NEXT: jmp __asan_report_store16@PLT declare void @llvm.asan.check.memaccess(i8*, i32 immarg) diff --git a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll --- a/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll +++ b/llvm/test/CodeGen/X86/asan-check-memaccess-or.ll @@ -172,7 +172,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store1 +; CHECK-NEXT: jmp __asan_report_store1@PLT ; CHECK: .type __asan_check_store2_rn[[RN2]],@function ; CHECK-NEXT: .weak __asan_check_store2_rn[[RN2]] @@ -195,7 +195,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store2 +; CHECK-NEXT: jmp __asan_report_store2@PLT ; CHECK: .type __asan_check_store4_rn[[RN4]],@function ; CHECK-NEXT: .weak __asan_check_store4_rn[[RN4]] @@ -218,7 +218,7 @@ ; CHECK-NEXT: popq %rcx ; CHECK-NEXT: jl [[RET]] ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store4 +; CHECK-NEXT: jmp __asan_report_store4@PLT ; CHECK: .type __asan_check_store8_rn[[RN8]],@function ; CHECK-NEXT: .weak __asan_check_store8_rn[[RN8]] @@ -233,7 +233,7 @@ ; CHECK-NEXT: retq ; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store8 +; CHECK-NEXT: jmp __asan_report_store8@PLT ; CHECK: .type __asan_check_store16_rn[[RN16]],@function ; CHECK-NEXT: .weak __asan_check_store16_rn[[RN16]] @@ -248,6 +248,6 @@ ; CHECK-NEXT: retq ; CHECK-NEXT: [[FAIL]]: ; CHECK-NEXT: movq [[REG:.*]], %rdi -; CHECK-NEXT: jmp __asan_report_store16 +; CHECK-NEXT: jmp __asan_report_store16@PLT declare void @llvm.asan.check.memaccess(i8*, i32 immarg)