diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -13871,6 +13871,8 @@
     N = N.getOperand(0);
   if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR)
     return false;
+  if (N.getOperand(0).getValueType().isScalableVector())
+    return false;
   return cast<ConstantSDNode>(N.getOperand(1))->getAPIntValue() ==
          N.getOperand(0).getValueType().getVectorNumElements() / 2;
 }
diff --git a/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll b/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-no-typesize-warnings.ll
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+define i64 @sve_no_typesize_warning() #0 {
+; CHECK-LABEL: sve_no_typesize_warning:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ld1r { v0.4h }, [x8]
+; CHECK-NEXT:    uabdl v1.4s, v0.4h, v0.4h
+; CHECK-NEXT:    uabal v1.4s, v0.4h, v0.4h
+; CHECK-NEXT:    ushll v0.2d, v1.2s, #0
+; CHECK-NEXT:    uaddw2 v0.2d, v0.2d, v1.4s
+; CHECK-NEXT:    addp d0, v0.2d
+; CHECK-NEXT:    fmov x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %wide.masked.gather = call <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*> undef, i32 2, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i16> undef)
+  %wide.load25 = load <4 x i32>, <4 x i32>* undef, align 4
+  %i = zext <4 x i16> %wide.masked.gather to <4 x i32>
+  %i2 = sub nsw <4 x i32> %i, %i
+  %i3 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %i2, i1 true)
+  %i5 = add nuw nsw <4 x i32> %i3, %i3
+  %i6 = zext <4 x i32> %i5 to <4 x i64>
+  %i7 = add <4 x i64> <i64 undef, i64 0, i64 0, i64 0>, %i6
+  %i8 = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %i7)
+  ret i64 %i8
+}
+
+declare <4 x i16> @llvm.masked.gather.v4i16.v4p0i16(<4 x i16*>, i32 immarg, <4 x i1>, <4 x i16>)
+declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1 immarg)
+declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>)
+
+attributes #0 = { "target-features"="+sve" }