Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -22860,6 +22860,20 @@ } } + // Fold select_CC setgt X, -1, C, ~C -> xor (ashr X, BW-1), C + // Fold select_CC setlt X, 0, C, ~C -> xor (ashr X, BW-1), ~C + if (!NotExtCompare && N1C && N2C && N3C && + N2C->getAPIntValue() == ~N3C->getAPIntValue() && + ((N1C->isAllOnesValue() && CC == ISD::SETGT) || + (N1C->isNullValue() && CC == ISD::SETLT)) && + !TLI.shouldAvoidTransformToShift(VT, CmpOpVT.getScalarSizeInBits() - 1)) { + SDValue ASR = DAG.getNode( + ISD::SRA, DL, CmpOpVT, N0, + DAG.getConstant(CmpOpVT.getScalarSizeInBits() - 1, DL, CmpOpVT)); + return DAG.getNode(ISD::XOR, DL, VT, DAG.getSExtOrTrunc(ASR, DL, VT), + DAG.getSExtOrTrunc(CC == ISD::SETLT ? N3 : N2, DL, VT)); + } + return SDValue(); } Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -3902,6 +3902,15 @@ return DAG.getSetCC(dl, VT, N0.getOperand(0), N1, Cond); } + // Fold set_cc seteq (ashr X, BW-1), -1 -> set_cc setlt X, 0 + if (Cond == ISD::SETEQ && N0.getOpcode() == ISD::SRA && + isa(N0.getOperand(1)) && + N0.getConstantOperandAPInt(1) == OpVT.getScalarSizeInBits() - 1 && + N1C && N1C->isAllOnesValue()) { + return DAG.getSetCC(dl, VT, N0.getOperand(0), + DAG.getConstant(0, dl, OpVT), ISD::SETLT); + } + if (SDValue V = optimizeSetCCOfSignedTruncationCheck(VT, N0, N1, Cond, DCI, dl)) return V; Index: llvm/test/CodeGen/AArch64/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/AArch64/select-constant-xor.ll +++ llvm/test/CodeGen/AArch64/select-constant-xor.ll @@ -16,9 +16,8 @@ define i64 @selecti64i64(i64 %a) { ; CHECK-LABEL: selecti64i64: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp x0, #0 -; CHECK-NEXT: mov w8, #2147483647 -; CHECK-NEXT: cinv x0, x8, lt +; CHECK-NEXT: asr x8, x0, #63 +; CHECK-NEXT: eor x0, x8, #0x7fffffff ; CHECK-NEXT: ret %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -28,9 +27,8 @@ define i32 @selecti64i32(i64 %a) { ; CHECK-LABEL: selecti64i32: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp x0, #0 -; CHECK-NEXT: mov w8, #2147483647 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: asr x8, x0, #63 +; CHECK-NEXT: eor w0, w8, #0x7fffffff ; CHECK-NEXT: ret %c = icmp sgt i64 %a, -1 %s = select i1 %c, i32 2147483647, i32 -2147483648 @@ -40,9 +38,9 @@ define i64 @selecti32i64(i32 %a) { ; CHECK-LABEL: selecti32i64: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #2147483647 -; CHECK-NEXT: cinv x0, x8, lt +; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-NEXT: sbfx x8, x0, #31, #1 +; CHECK-NEXT: eor x0, x8, #0x7fffffff ; CHECK-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -66,9 +64,8 @@ define i32 @selecti32i32(i32 %a) { ; CHECK-LABEL: selecti32i32: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: mov w8, #84 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: eor w0, w8, w0, asr #31 ; CHECK-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -78,9 +75,8 @@ define i8 @selecti32i8(i32 %a) { ; CHECK-LABEL: selecti32i8: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 ; CHECK-NEXT: mov w8, #84 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: eor w0, w8, w0, asr #31 ; CHECK-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i8 84, i8 -85 @@ -91,9 +87,8 @@ ; CHECK-LABEL: selecti8i32: ; CHECK: // %bb.0: ; CHECK-NEXT: sxtb w8, w0 -; CHECK-NEXT: cmp w8, #0 -; CHECK-NEXT: mov w8, #84 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: mov w9, #84 +; CHECK-NEXT: eor w0, w9, w8, asr #7 ; CHECK-NEXT: ret %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -124,9 +119,8 @@ define i32 @selecti32i32_1(i32 %a) { ; CHECK-LABEL: selecti32i32_1: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #1 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: eor w0, w8, #0x1 ; CHECK-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 1, i32 -2 @@ -136,9 +130,8 @@ define i32 @selecti32i32_sge(i32 %a) { ; CHECK-LABEL: selecti32i32_sge: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #12 -; CHECK-NEXT: cinv w0, w8, lt +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: eor w0, w8, #0xc ; CHECK-NEXT: ret %c = icmp sge i32 %a, 0 %s = select i1 %c, i32 12, i32 -13 @@ -148,9 +141,8 @@ define i32 @selecti32i32_slt(i32 %a) { ; CHECK-LABEL: selecti32i32_slt: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #-13 -; CHECK-NEXT: cinv w0, w8, ge +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: eor w0, w8, #0xc ; CHECK-NEXT: ret %c = icmp slt i32 %a, 0 %s = select i1 %c, i32 -13, i32 12 @@ -160,9 +152,8 @@ define i32 @selecti32i32_sle(i32 %a) { ; CHECK-LABEL: selecti32i32_sle: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #-13 -; CHECK-NEXT: cinv w0, w8, ge +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: eor w0, w8, #0xc ; CHECK-NEXT: ret %c = icmp sle i32 %a, -1 %s = select i1 %c, i32 -13, i32 12 @@ -172,9 +163,8 @@ define i32 @selecti32i32_sgt(i32 %a) { ; CHECK-LABEL: selecti32i32_sgt: ; CHECK: // %bb.0: -; CHECK-NEXT: cmp w0, #0 -; CHECK-NEXT: mov w8, #-13 -; CHECK-NEXT: cinv w0, w8, ge +; CHECK-NEXT: asr w8, w0, #31 +; CHECK-NEXT: eor w0, w8, #0xc ; CHECK-NEXT: ret %c = icmp sle i32 %a, -1 %s = select i1 %c, i32 -13, i32 12 Index: llvm/test/CodeGen/AMDGPU/fp_to_sint.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/fp_to_sint.ll +++ llvm/test/CodeGen/AMDGPU/fp_to_sint.ll @@ -237,7 +237,7 @@ ; ; EG-LABEL: fp_to_sint_i64: ; EG: ; %bb.0: ; %entry -; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD @@ -277,11 +277,10 @@ ; EG-NEXT: SUB_INT T2.W, PS, T1.W, ; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W, ; EG-NEXT: SUB_INT T2.W, PV.W, PS, -; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x, -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W, +; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X, +; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0, ; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W, -; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W, +; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) entry: @@ -361,7 +360,7 @@ ; ; EG-LABEL: fp_to_sint_v2i64: ; EG: ; %bb.0: -; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD @@ -429,19 +428,17 @@ ; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W, ; EG-NEXT: SUB_INT T1.Y, PV.W, PS, -; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x, +; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y, ; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W, -; EG-NEXT: -1(nan), 0(0.000000e+00) ; EG-NEXT: SUB_INT T0.Z, PV.W, PS, -; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x, -; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z, +; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W, +; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0, +; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0, ; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W, -; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W, +; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0, ; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W, -; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W, +; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0, ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) %conv = fptosi <2 x float> %x to <2 x i64> @@ -567,7 +564,7 @@ ; EG-LABEL: fp_to_sint_v4i64: ; EG: ; %bb.0: ; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[] -; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1 ; EG-NEXT: CF_END @@ -653,12 +650,11 @@ ; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W, ; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44) ; EG-NEXT: SUB_INT T5.X, PV.W, PS, -; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x, +; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y, ; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0, -; EG-NEXT: OR_INT T1.W, PV.X, literal.y, -; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z, -; EG-NEXT: -1(nan), 8388608(1.175494e-38) -; EG-NEXT: -150(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT T1.W, PV.X, literal.x, +; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y, +; EG-NEXT: 8388608(1.175494e-38), -150(nan) ; EG-NEXT: ADD_INT T4.X, T3.X, literal.x, ; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X, ; EG-NEXT: AND_INT T2.Z, PS, literal.z, @@ -673,15 +669,15 @@ ; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x, ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) ; EG-NEXT: ADD_INT T6.X, T1.X, literal.x, -; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0, +; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0, +; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0, ; EG-NEXT: -150(nan), 0(0.000000e+00) ; EG-NEXT: ALU clause starting at 108: -; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0, ; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y, ; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x, ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) ; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W, -; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z, +; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z, ; EG-NEXT: AND_INT T2.Z, T6.X, literal.x, ; EG-NEXT: NOT_INT T1.W, T6.X, ; EG-NEXT: LSHR * T3.W, T0.W, 1, @@ -708,29 +704,26 @@ ; EG-NEXT: XOR_INT T1.X, PV.W, PS, ; EG-NEXT: XOR_INT T5.Y, PV.Z, PS, ; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y, -; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x, -; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x, -; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z, +; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122 +; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0, +; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X, +; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0, ; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122 ; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W, -; EG-NEXT: -1(nan), 0(0.000000e+00) ; EG-NEXT: SUB_INT T3.X, PV.W, PS, -; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x, -; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212 -; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, -; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W, -; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X, +; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y, +; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0, +; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122 +; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0, +; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0, +; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0, ; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y, ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W, +; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0, ; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212 -; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W, +; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: LSHR * T0.X, PV.W, literal.x, Index: llvm/test/CodeGen/AMDGPU/fp_to_uint.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/fp_to_uint.ll +++ llvm/test/CodeGen/AMDGPU/fp_to_uint.ll @@ -184,7 +184,7 @@ ; ; EG-LABEL: fp_to_uint_f32_to_i64: ; EG: ; %bb.0: -; EG-NEXT: ALU 41, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 40, @4, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD @@ -224,11 +224,10 @@ ; EG-NEXT: SUB_INT T2.W, PS, T1.W, ; EG-NEXT: SUBB_UINT * T3.W, PV.W, T1.W, ; EG-NEXT: SUB_INT T2.W, PV.W, PS, -; EG-NEXT: SETGT_INT * T3.W, T0.X, literal.x, -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T0.Y, PS, 0.0, PV.W, +; EG-NEXT: SETGT_INT * T3.W, 0.0, T0.X, +; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0, ; EG-NEXT: SUB_INT * T0.W, T0.W, T1.W, -; EG-NEXT: CNDE_INT T0.X, T3.W, 0.0, PV.W, +; EG-NEXT: CNDE_INT T0.X, T3.W, PV.W, 0.0, ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) %conv = fptoui float %x to i64 @@ -287,7 +286,7 @@ ; ; EG-LABEL: fp_to_uint_v2f32_to_v2i64: ; EG: ; %bb.0: -; EG-NEXT: ALU 77, @4, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1 ; EG-NEXT: CF_END ; EG-NEXT: PAD @@ -355,19 +354,17 @@ ; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W, ; EG-NEXT: SUB_INT T1.Y, PV.W, PS, -; EG-NEXT: SETGT_INT T1.Z, T3.Y, literal.x, +; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y, ; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W, -; EG-NEXT: -1(nan), 0(0.000000e+00) ; EG-NEXT: SUB_INT T0.Z, PV.W, PS, -; EG-NEXT: SETGT_INT T0.W, T1.W, literal.x, -; EG-NEXT: CNDE_INT * T1.W, PV.Z, 0.0, PV.Y, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T1.Y, PV.W, 0.0, PV.Z, +; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W, +; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0, +; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0, ; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W, -; EG-NEXT: CNDE_INT T1.Z, T1.Z, 0.0, PV.W, +; EG-NEXT: CNDE_INT T1.Z, T1.Z, PV.W, 0.0, ; EG-NEXT: SUB_INT * T2.W, T0.Y, T3.W, -; EG-NEXT: CNDE_INT T1.X, T0.W, 0.0, PV.W, +; EG-NEXT: CNDE_INT T1.X, T0.W, PV.W, 0.0, ; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) %conv = fptoui <2 x float> %x to <2 x i64> @@ -453,7 +450,7 @@ ; EG-LABEL: fp_to_uint_v4f32_to_v4i64: ; EG: ; %bb.0: ; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[] -; EG-NEXT: ALU 58, @108, KC0[CB0:0-32], KC1[] +; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[] ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1 ; EG-NEXT: CF_END @@ -539,12 +536,11 @@ ; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W, ; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44) ; EG-NEXT: SUB_INT T5.X, PV.W, PS, -; EG-NEXT: SETGT_INT T0.Y, T0.Y, literal.x, +; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y, ; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0, -; EG-NEXT: OR_INT T1.W, PV.X, literal.y, -; EG-NEXT: ADD_INT * T3.W, T3.X, literal.z, -; EG-NEXT: -1(nan), 8388608(1.175494e-38) -; EG-NEXT: -150(nan), 0(0.000000e+00) +; EG-NEXT: OR_INT T1.W, PV.X, literal.x, +; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y, +; EG-NEXT: 8388608(1.175494e-38), -150(nan) ; EG-NEXT: ADD_INT T4.X, T3.X, literal.x, ; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X, ; EG-NEXT: AND_INT T2.Z, PS, literal.z, @@ -559,15 +555,15 @@ ; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x, ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00) ; EG-NEXT: ADD_INT T6.X, T1.X, literal.x, -; EG-NEXT: CNDE_INT * T3.Y, PS, PV.W, 0.0, +; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0, +; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0, ; EG-NEXT: -150(nan), 0(0.000000e+00) ; EG-NEXT: ALU clause starting at 108: -; EG-NEXT: CNDE_INT T3.Z, T2.Z, T4.Y, 0.0, ; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y, ; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x, ; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00) ; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W, -; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, PV.Z, +; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z, ; EG-NEXT: AND_INT T2.Z, T6.X, literal.x, ; EG-NEXT: NOT_INT T1.W, T6.X, ; EG-NEXT: LSHR * T3.W, T0.W, 1, @@ -594,29 +590,26 @@ ; EG-NEXT: XOR_INT T1.X, PV.W, PS, ; EG-NEXT: XOR_INT T5.Y, PV.Z, PS, ; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y, -; EG-NEXT: SETGT_INT T1.W, T4.X, literal.x, -; EG-NEXT: CNDE_INT * T6.W, T0.Y, 0.0, T5.X, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: SETGT_INT T0.X, T0.X, literal.x, -; EG-NEXT: CNDE_INT T6.Y, PV.W, 0.0, PV.Z, +; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122 +; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0, +; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X, +; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0, ; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122 ; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W, ; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W, -; EG-NEXT: -1(nan), 0(0.000000e+00) ; EG-NEXT: SUB_INT T3.X, PV.W, PS, -; EG-NEXT: SETGT_INT T1.Y, T4.Y, literal.x, -; EG-NEXT: CNDE_INT T6.Z, T0.Y, 0.0, PV.Z, BS:VEC_120/SCL_212 -; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, -; EG-NEXT: CNDE_INT * T4.W, PV.X, 0.0, T2.X, BS:VEC_021/SCL_122 -; EG-NEXT: -1(nan), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T6.X, T1.W, 0.0, PV.W, -; EG-NEXT: CNDE_INT T4.Y, PV.Y, 0.0, PV.X, +; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y, +; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0, +; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122 +; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0, +; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0, +; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0, ; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y, ; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x, ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00) -; EG-NEXT: CNDE_INT T4.Z, T0.X, 0.0, PV.W, +; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0, ; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212 -; EG-NEXT: CNDE_INT T4.X, T1.Y, 0.0, PV.W, +; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0, ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x, ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00) ; EG-NEXT: LSHR * T0.X, PV.W, literal.x, Index: llvm/test/CodeGen/AMDGPU/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/select-constant-xor.ll +++ llvm/test/CodeGen/AMDGPU/select-constant-xor.ll @@ -20,10 +20,8 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1] -; CHECK-NEXT: v_bfrev_b32_e32 v2, -2 -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo -; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo +; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1 +; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -35,9 +33,8 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_cmp_lt_i64_e32 vcc_lo, -1, v[0:1] -; CHECK-NEXT: v_bfrev_b32_e32 v2, -2 -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v2, vcc_lo +; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v1 +; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i64 %a, -1 %s = select i1 %c, i32 2147483647, i32 -2147483648 @@ -49,10 +46,9 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_bfrev_b32_e32 v1, -2 -; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0x80000000, v1, vcc_lo -; CHECK-NEXT: v_cndmask_b32_e64 v1, -1, 0, vcc_lo +; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; CHECK-NEXT: v_xor_b32_e32 v0, 0x7fffffff, v1 +; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v1 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -80,9 +76,8 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_mov_b32_e32 v1, 0x54 -; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo +; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0 +; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -94,9 +89,8 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_mov_b32_e32 v1, 0x54 -; CHECK-NEXT: v_cmp_lt_i32_e32 vcc_lo, -1, v0 -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v1, vcc_lo +; CHECK-NEXT: v_ashrrev_i32_e32 v0, 31, v0 +; CHECK-NEXT: v_xor_b32_e32 v0, 0x54, v0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i32 %a, -1 %s = select i1 %c, i8 84, i8 -85 @@ -108,10 +102,10 @@ ; CHECK: ; %bb.0: ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt_vscnt null, 0x0 -; CHECK-NEXT: v_mov_b32_e32 v1, -1 -; CHECK-NEXT: v_mov_b32_e32 v2, 0x54 -; CHECK-NEXT: v_cmp_gt_i16_sdwa vcc_lo, sext(v0), v1 src0_sel:BYTE_0 src1_sel:DWORD -; CHECK-NEXT: v_cndmask_b32_e32 v0, 0xffffffab, v2, vcc_lo +; CHECK-NEXT: v_bfe_i32 v0, v0, 0, 8 +; CHECK-NEXT: v_mov_b32_e32 v1, 0x54 +; CHECK-NEXT: v_ashrrev_i16 v0, 7, v0 +; CHECK-NEXT: v_xor_b32_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 ; CHECK-NEXT: s_setpc_b64 s[30:31] %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 Index: llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll =================================================================== --- llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll +++ llvm/test/CodeGen/AMDGPU/selectcc-icmp-select-float.ll @@ -8,7 +8,7 @@ ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[] ; CHECK-NEXT: TEX 0 @6 -; CHECK-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[] +; CHECK-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[] ; CHECK-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1 ; CHECK-NEXT: CF_END ; CHECK-NEXT: PAD @@ -17,9 +17,8 @@ ; CHECK-NEXT: ALU clause starting at 8: ; CHECK-NEXT: MOV * T0.X, KC0[2].Z, ; CHECK-NEXT: ALU clause starting at 9: -; CHECK-NEXT: SETGT_INT * T0.W, T0.X, literal.x, -; CHECK-NEXT: -1(nan), 0(0.000000e+00) -; CHECK-NEXT: CNDE_INT T0.X, PV.W, 0.0, literal.x, +; CHECK-NEXT: SETGT_INT * T0.W, 0.0, T0.X, +; CHECK-NEXT: CNDE_INT T0.X, PV.W, literal.x, 0.0, ; CHECK-NEXT: LSHR * T1.X, KC0[2].Y, literal.y, ; CHECK-NEXT: 1065353216(1.000000e+00), 2(2.802597e-45) entry: Index: llvm/test/CodeGen/ARM/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/ARM/select-constant-xor.ll +++ llvm/test/CodeGen/ARM/select-constant-xor.ll @@ -42,54 +42,34 @@ define i64 @selecti64i64(i64 %a) { ; CHECK7A-LABEL: selecti64i64: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: cmn r1, #1 -; CHECK7A-NEXT: mov r0, #-2147483648 -; CHECK7A-NEXT: mvn r1, #0 -; CHECK7A-NEXT: mvngt r0, #-2147483648 -; CHECK7A-NEXT: movwgt r1, #0 +; CHECK7A-NEXT: mvn r0, #-2147483648 +; CHECK7A-NEXT: eor r0, r0, r1, asr #31 +; CHECK7A-NEXT: asr r1, r1, #31 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti64i64: ; CHECK6M: @ %bb.0: -; CHECK6M-NEXT: cmp r1, #0 -; CHECK6M-NEXT: bge .LBB1_2 -; CHECK6M-NEXT: @ %bb.1: -; CHECK6M-NEXT: movs r0, #1 -; CHECK6M-NEXT: lsls r0, r0, #31 -; CHECK6M-NEXT: b .LBB1_3 -; CHECK6M-NEXT: .LBB1_2: +; CHECK6M-NEXT: asrs r1, r1, #31 ; CHECK6M-NEXT: ldr r0, .LCPI1_0 -; CHECK6M-NEXT: .LBB1_3: -; CHECK6M-NEXT: movs r2, #0 -; CHECK6M-NEXT: cmp r1, #0 -; CHECK6M-NEXT: bge .LBB1_5 -; CHECK6M-NEXT: @ %bb.4: -; CHECK6M-NEXT: mvns r2, r2 -; CHECK6M-NEXT: .LBB1_5: -; CHECK6M-NEXT: mov r1, r2 +; CHECK6M-NEXT: eors r0, r1 ; CHECK6M-NEXT: bx lr ; CHECK6M-NEXT: .p2align 2 -; CHECK6M-NEXT: @ %bb.6: +; CHECK6M-NEXT: @ %bb.1: ; CHECK6M-NEXT: .LCPI1_0: ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff ; ; CHECK7M-LABEL: selecti64i64: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: cmp.w r1, #-1 -; CHECK7M-NEXT: mov.w r0, #-2147483648 -; CHECK7M-NEXT: mov.w r1, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: mvngt r0, #-2147483648 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: movgt r1, #0 +; CHECK7M-NEXT: mvn r0, #-2147483648 +; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK7M-NEXT: asrs r1, r1, #31 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti64i64: ; CHECK81M: @ %bb.0: -; CHECK81M-NEXT: cmp.w r1, #-1 ; CHECK81M-NEXT: mvn r0, #-2147483648 -; CHECK81M-NEXT: cinv r0, r0, le -; CHECK81M-NEXT: csetm r1, le +; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31 +; CHECK81M-NEXT: asrs r1, r1, #31 ; CHECK81M-NEXT: bx lr %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -99,9 +79,8 @@ define i32 @selecti64i32(i64 %a) { ; CHECK7A-LABEL: selecti64i32: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: mov r0, #-2147483648 -; CHECK7A-NEXT: cmn r1, #1 -; CHECK7A-NEXT: mvngt r0, #-2147483648 +; CHECK7A-NEXT: mvn r0, #-2147483648 +; CHECK7A-NEXT: eor r0, r0, r1, asr #31 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti64i32: @@ -120,17 +99,14 @@ ; ; CHECK7M-LABEL: selecti64i32: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: mov.w r0, #-2147483648 -; CHECK7M-NEXT: cmp.w r1, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: mvngt r0, #-2147483648 +; CHECK7M-NEXT: mvn r0, #-2147483648 +; CHECK7M-NEXT: eor.w r0, r0, r1, asr #31 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti64i32: ; CHECK81M: @ %bb.0: ; CHECK81M-NEXT: mvn r0, #-2147483648 -; CHECK81M-NEXT: cmp.w r1, #-1 -; CHECK81M-NEXT: cinv r0, r0, le +; CHECK81M-NEXT: eor.w r0, r0, r1, asr #31 ; CHECK81M-NEXT: bx lr %c = icmp sgt i64 %a, -1 %s = select i1 %c, i32 2147483647, i32 -2147483648 @@ -140,56 +116,37 @@ define i64 @selecti32i64(i32 %a) { ; CHECK7A-LABEL: selecti32i64: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: mov r2, #-2147483648 -; CHECK7A-NEXT: cmn r0, #1 -; CHECK7A-NEXT: mvn r1, #0 -; CHECK7A-NEXT: mvngt r2, #-2147483648 -; CHECK7A-NEXT: movwgt r1, #0 +; CHECK7A-NEXT: mvn r1, #-2147483648 +; CHECK7A-NEXT: eor r2, r1, r0, asr #31 +; CHECK7A-NEXT: asr r1, r0, #31 ; CHECK7A-NEXT: mov r0, r2 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti32i64: ; CHECK6M: @ %bb.0: -; CHECK6M-NEXT: mov r2, r0 -; CHECK6M-NEXT: cmp r0, #0 -; CHECK6M-NEXT: bge .LBB3_2 -; CHECK6M-NEXT: @ %bb.1: -; CHECK6M-NEXT: movs r0, #1 -; CHECK6M-NEXT: lsls r0, r0, #31 -; CHECK6M-NEXT: b .LBB3_3 -; CHECK6M-NEXT: .LBB3_2: +; CHECK6M-NEXT: asrs r1, r0, #31 ; CHECK6M-NEXT: ldr r0, .LCPI3_0 -; CHECK6M-NEXT: .LBB3_3: -; CHECK6M-NEXT: movs r1, #0 -; CHECK6M-NEXT: cmp r2, #0 -; CHECK6M-NEXT: bge .LBB3_5 -; CHECK6M-NEXT: @ %bb.4: -; CHECK6M-NEXT: mvns r1, r1 -; CHECK6M-NEXT: .LBB3_5: +; CHECK6M-NEXT: eors r0, r1 ; CHECK6M-NEXT: bx lr ; CHECK6M-NEXT: .p2align 2 -; CHECK6M-NEXT: @ %bb.6: +; CHECK6M-NEXT: @ %bb.1: ; CHECK6M-NEXT: .LCPI3_0: ; CHECK6M-NEXT: .long 2147483647 @ 0x7fffffff ; ; CHECK7M-LABEL: selecti32i64: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: mov.w r2, #-2147483648 -; CHECK7M-NEXT: cmp.w r0, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: mvngt r2, #-2147483648 -; CHECK7M-NEXT: mov.w r1, #-1 +; CHECK7M-NEXT: mvn r1, #-2147483648 +; CHECK7M-NEXT: eor.w r2, r1, r0, asr #31 +; CHECK7M-NEXT: asrs r1, r0, #31 ; CHECK7M-NEXT: mov r0, r2 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: movgt r1, #0 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti32i64: ; CHECK81M: @ %bb.0: ; CHECK81M-NEXT: mvn r1, #-2147483648 -; CHECK81M-NEXT: cmp.w r0, #-1 -; CHECK81M-NEXT: cinv r0, r1, le -; CHECK81M-NEXT: csetm r1, le +; CHECK81M-NEXT: eor.w r2, r1, r0, asr #31 +; CHECK81M-NEXT: asrs r1, r0, #31 +; CHECK81M-NEXT: mov r0, r2 ; CHECK81M-NEXT: bx lr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -232,37 +189,27 @@ define i32 @selecti32i32(i32 %a) { ; CHECK7A-LABEL: selecti32i32: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: mvn r1, #84 -; CHECK7A-NEXT: cmn r0, #1 -; CHECK7A-NEXT: movwgt r1, #84 -; CHECK7A-NEXT: mov r0, r1 +; CHECK7A-NEXT: mov r1, #84 +; CHECK7A-NEXT: eor r0, r1, r0, asr #31 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti32i32: ; CHECK6M: @ %bb.0: -; CHECK6M-NEXT: mov r1, r0 +; CHECK6M-NEXT: asrs r1, r0, #31 ; CHECK6M-NEXT: movs r0, #84 -; CHECK6M-NEXT: cmp r1, #0 -; CHECK6M-NEXT: bge .LBB5_2 -; CHECK6M-NEXT: @ %bb.1: -; CHECK6M-NEXT: mvns r0, r0 -; CHECK6M-NEXT: .LBB5_2: +; CHECK6M-NEXT: eors r0, r1 ; CHECK6M-NEXT: bx lr ; ; CHECK7M-LABEL: selecti32i32: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: mvn r1, #84 -; CHECK7M-NEXT: cmp.w r0, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: movgt r1, #84 -; CHECK7M-NEXT: mov r0, r1 +; CHECK7M-NEXT: movs r1, #84 +; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti32i32: ; CHECK81M: @ %bb.0: ; CHECK81M-NEXT: movs r1, #84 -; CHECK81M-NEXT: cmp.w r0, #-1 -; CHECK81M-NEXT: cinv r0, r1, le +; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31 ; CHECK81M-NEXT: bx lr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -272,37 +219,27 @@ define i8 @selecti32i8(i32 %a) { ; CHECK7A-LABEL: selecti32i8: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: mvn r1, #84 -; CHECK7A-NEXT: cmn r0, #1 -; CHECK7A-NEXT: movwgt r1, #84 -; CHECK7A-NEXT: mov r0, r1 +; CHECK7A-NEXT: mov r1, #84 +; CHECK7A-NEXT: eor r0, r1, r0, asr #31 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti32i8: ; CHECK6M: @ %bb.0: -; CHECK6M-NEXT: mov r1, r0 +; CHECK6M-NEXT: asrs r1, r0, #31 ; CHECK6M-NEXT: movs r0, #84 -; CHECK6M-NEXT: cmp r1, #0 -; CHECK6M-NEXT: bge .LBB6_2 -; CHECK6M-NEXT: @ %bb.1: -; CHECK6M-NEXT: mvns r0, r0 -; CHECK6M-NEXT: .LBB6_2: +; CHECK6M-NEXT: eors r0, r1 ; CHECK6M-NEXT: bx lr ; ; CHECK7M-LABEL: selecti32i8: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: mvn r1, #84 -; CHECK7M-NEXT: cmp.w r0, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: movgt r1, #84 -; CHECK7M-NEXT: mov r0, r1 +; CHECK7M-NEXT: movs r1, #84 +; CHECK7M-NEXT: eor.w r0, r1, r0, asr #31 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti32i8: ; CHECK81M: @ %bb.0: ; CHECK81M-NEXT: movs r1, #84 -; CHECK81M-NEXT: cmp.w r0, #-1 -; CHECK81M-NEXT: cinv r0, r1, le +; CHECK81M-NEXT: eor.w r0, r1, r0, asr #31 ; CHECK81M-NEXT: bx lr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i8 84, i8 -85 @@ -312,38 +249,31 @@ define i32 @selecti8i32(i8 %a) { ; CHECK7A-LABEL: selecti8i32: ; CHECK7A: @ %bb.0: -; CHECK7A-NEXT: sxtb r1, r0 -; CHECK7A-NEXT: mvn r0, #84 -; CHECK7A-NEXT: cmn r1, #1 -; CHECK7A-NEXT: movwgt r0, #84 +; CHECK7A-NEXT: sxtb r0, r0 +; CHECK7A-NEXT: mov r1, #84 +; CHECK7A-NEXT: eor r0, r1, r0, asr #7 ; CHECK7A-NEXT: bx lr ; ; CHECK6M-LABEL: selecti8i32: ; CHECK6M: @ %bb.0: -; CHECK6M-NEXT: sxtb r1, r0 +; CHECK6M-NEXT: sxtb r0, r0 +; CHECK6M-NEXT: asrs r1, r0, #7 ; CHECK6M-NEXT: movs r0, #84 -; CHECK6M-NEXT: cmp r1, #0 -; CHECK6M-NEXT: bge .LBB7_2 -; CHECK6M-NEXT: @ %bb.1: -; CHECK6M-NEXT: mvns r0, r0 -; CHECK6M-NEXT: .LBB7_2: +; CHECK6M-NEXT: eors r0, r1 ; CHECK6M-NEXT: bx lr ; ; CHECK7M-LABEL: selecti8i32: ; CHECK7M: @ %bb.0: -; CHECK7M-NEXT: sxtb r1, r0 -; CHECK7M-NEXT: mvn r0, #84 -; CHECK7M-NEXT: cmp.w r1, #-1 -; CHECK7M-NEXT: it gt -; CHECK7M-NEXT: movgt r0, #84 +; CHECK7M-NEXT: sxtb r0, r0 +; CHECK7M-NEXT: movs r1, #84 +; CHECK7M-NEXT: eor.w r0, r1, r0, asr #7 ; CHECK7M-NEXT: bx lr ; ; CHECK81M-LABEL: selecti8i32: ; CHECK81M: @ %bb.0: ; CHECK81M-NEXT: sxtb r0, r0 ; CHECK81M-NEXT: movs r1, #84 -; CHECK81M-NEXT: cmp.w r0, #-1 -; CHECK81M-NEXT: cinv r0, r1, le +; CHECK81M-NEXT: eor.w r0, r1, r0, asr #7 ; CHECK81M-NEXT: bx lr %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 Index: llvm/test/CodeGen/PowerPC/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/PowerPC/select-constant-xor.ll +++ llvm/test/CodeGen/PowerPC/select-constant-xor.ll @@ -17,11 +17,9 @@ define i64 @selecti64i64(i64 %a) { ; CHECK-LABEL: selecti64i64: ; CHECK: # %bb.0: -; CHECK-NEXT: lis 4, 32767 -; CHECK-NEXT: cmpdi 3, -1 -; CHECK-NEXT: ori 3, 4, 65535 -; CHECK-NEXT: lis 4, -32768 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: sradi 3, 3, 63 +; CHECK-NEXT: xori 3, 3, 65535 +; CHECK-NEXT: xoris 3, 3, 32767 ; CHECK-NEXT: blr %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -31,11 +29,9 @@ define i32 @selecti64i32(i64 %a) { ; CHECK-LABEL: selecti64i32: ; CHECK: # %bb.0: -; CHECK-NEXT: lis 4, 32767 -; CHECK-NEXT: cmpdi 3, -1 -; CHECK-NEXT: ori 3, 4, 65535 -; CHECK-NEXT: lis 4, -32768 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: sradi 3, 3, 63 +; CHECK-NEXT: xori 3, 3, 65535 +; CHECK-NEXT: xoris 3, 3, 32767 ; CHECK-NEXT: blr %c = icmp sgt i64 %a, -1 %s = select i1 %c, i32 2147483647, i32 -2147483648 @@ -45,11 +41,10 @@ define i64 @selecti32i64(i32 %a) { ; CHECK-LABEL: selecti32i64: ; CHECK: # %bb.0: -; CHECK-NEXT: lis 4, 32767 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: ori 3, 4, 65535 -; CHECK-NEXT: lis 4, -32768 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: srawi 3, 3, 31 +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: xori 3, 3, 65535 +; CHECK-NEXT: xoris 3, 3, 32767 ; CHECK-NEXT: blr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -73,10 +68,9 @@ define i32 @selecti32i32(i32 %a) { ; CHECK-LABEL: selecti32i32: ; CHECK: # %bb.0: -; CHECK-NEXT: li 4, -85 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: li 3, 84 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: srawi 3, 3, 31 +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: xori 3, 3, 84 ; CHECK-NEXT: blr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -86,10 +80,9 @@ define i8 @selecti32i8(i32 %a) { ; CHECK-LABEL: selecti32i8: ; CHECK: # %bb.0: -; CHECK-NEXT: li 4, -85 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: li 3, 84 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: srawi 3, 3, 31 +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: xori 3, 3, 84 ; CHECK-NEXT: blr %c = icmp sgt i32 %a, -1 %s = select i1 %c, i8 84, i8 -85 @@ -100,10 +93,9 @@ ; CHECK-LABEL: selecti8i32: ; CHECK: # %bb.0: ; CHECK-NEXT: extsb 3, 3 -; CHECK-NEXT: li 4, -85 -; CHECK-NEXT: cmpwi 3, -1 -; CHECK-NEXT: li 3, 84 -; CHECK-NEXT: iselgt 3, 3, 4 +; CHECK-NEXT: srawi 3, 3, 7 +; CHECK-NEXT: extsw 3, 3 +; CHECK-NEXT: xori 3, 3, 84 ; CHECK-NEXT: blr %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 Index: llvm/test/CodeGen/PowerPC/smulfixsat.ll =================================================================== --- llvm/test/CodeGen/PowerPC/smulfixsat.ll +++ llvm/test/CodeGen/PowerPC/smulfixsat.ll @@ -6,20 +6,15 @@ define i32 @func1(i32 %x, i32 %y) nounwind { ; CHECK-LABEL: func1: ; CHECK: # %bb.0: -; CHECK-NEXT: lis 5, 32767 -; CHECK-NEXT: mulhw. 6, 3, 4 -; CHECK-NEXT: lis 7, -32768 +; CHECK-NEXT: mulhw 5, 3, 4 ; CHECK-NEXT: mullw 3, 3, 4 -; CHECK-NEXT: ori 4, 5, 65535 -; CHECK-NEXT: srawi 5, 3, 31 -; CHECK-NEXT: cmplw 1, 6, 5 -; CHECK-NEXT: bc 12, 0, .LBB0_1 -; CHECK-NEXT: b .LBB0_2 -; CHECK-NEXT: .LBB0_1: -; CHECK-NEXT: addi 4, 7, 0 -; CHECK-NEXT: .LBB0_2: -; CHECK-NEXT: bclr 12, 6, 0 -; CHECK-NEXT: # %bb.3: +; CHECK-NEXT: srawi 4, 3, 31 +; CHECK-NEXT: cmplw 5, 4 +; CHECK-NEXT: srawi 4, 5, 31 +; CHECK-NEXT: xori 4, 4, 65535 +; CHECK-NEXT: xoris 4, 4, 32767 +; CHECK-NEXT: bclr 12, 2, 0 +; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: ori 3, 4, 0 ; CHECK-NEXT: blr %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0) Index: llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll =================================================================== --- llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll +++ llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll @@ -72,8 +72,7 @@ ; LE-NEXT: blr ; ; CHECK-P10-LE-LABEL: testCompare1: -; CHECK-P10-LE: .localentry testCompare1, 1 -; CHECK-P10-LE-NEXT: # %bb.0: # %entry +; CHECK-P10-LE: # %bb.0: # %entry ; CHECK-P10-LE-NEXT: plbz r4, testCompare1@PCREL(0), 1 ; CHECK-P10-LE-NEXT: lbz r3, 0(r3) ; CHECK-P10-LE-NEXT: clrlwi r3, r3, 31 @@ -124,8 +123,7 @@ ; CHECK-P10-CMP-LE-NEXT: blr ; ; CHECK-P10-CMP-BE-LABEL: testCompare1: -; CHECK-P10-CMP-BE: .localentry testCompare1, 1 -; CHECK-P10-CMP-BE-NEXT: # %bb.0: # %entry +; CHECK-P10-CMP-BE: # %bb.0: # %entry ; CHECK-P10-CMP-BE-NEXT: plbz r4, testCompare1@PCREL(0), 1 ; CHECK-P10-CMP-BE-NEXT: lbz r3, 0(r3) ; CHECK-P10-CMP-BE-NEXT: clrlwi r3, r3, 31 Index: llvm/test/CodeGen/RISCV/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/RISCV/select-constant-xor.ll +++ llvm/test/CodeGen/RISCV/select-constant-xor.ll @@ -27,24 +27,18 @@ define i64 @selecti64i64(i64 %a) { ; CHECK32-LABEL: selecti64i64: ; CHECK32: # %bb.0: +; CHECK32-NEXT: srai a1, a1, 31 ; CHECK32-NEXT: lui a0, 524288 -; CHECK32-NEXT: bgez a1, .LBB1_2 -; CHECK32-NEXT: # %bb.1: -; CHECK32-NEXT: addi a1, zero, -1 -; CHECK32-NEXT: ret -; CHECK32-NEXT: .LBB1_2: -; CHECK32-NEXT: mv a1, zero ; CHECK32-NEXT: addi a0, a0, -1 +; CHECK32-NEXT: xor a0, a1, a0 ; CHECK32-NEXT: ret ; ; CHECK64-LABEL: selecti64i64: ; CHECK64: # %bb.0: -; CHECK64-NEXT: mv a1, a0 -; CHECK64-NEXT: lui a0, 524288 -; CHECK64-NEXT: bltz a1, .LBB1_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addiw a0, a0, -1 -; CHECK64-NEXT: .LBB1_2: +; CHECK64-NEXT: srai a0, a0, 63 +; CHECK64-NEXT: lui a1, 524288 +; CHECK64-NEXT: addiw a1, a1, -1 +; CHECK64-NEXT: xor a0, a0, a1 ; CHECK64-NEXT: ret %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -62,12 +56,10 @@ ; ; CHECK64-LABEL: selecti64i32: ; CHECK64: # %bb.0: -; CHECK64-NEXT: mv a1, a0 -; CHECK64-NEXT: lui a0, 524288 -; CHECK64-NEXT: bltz a1, .LBB2_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addiw a0, a0, -1 -; CHECK64-NEXT: .LBB2_2: +; CHECK64-NEXT: srai a0, a0, 63 +; CHECK64-NEXT: lui a1, 524288 +; CHECK64-NEXT: addiw a1, a1, -1 +; CHECK64-NEXT: xor a0, a0, a1 ; CHECK64-NEXT: ret %c = icmp sgt i64 %a, -1 %s = select i1 %c, i32 2147483647, i32 -2147483648 @@ -77,25 +69,18 @@ define i64 @selecti32i64(i32 %a) { ; CHECK32-LABEL: selecti32i64: ; CHECK32: # %bb.0: -; CHECK32-NEXT: mv a1, a0 +; CHECK32-NEXT: srai a1, a0, 31 ; CHECK32-NEXT: lui a0, 524288 -; CHECK32-NEXT: bgez a1, .LBB3_2 -; CHECK32-NEXT: # %bb.1: -; CHECK32-NEXT: addi a1, zero, -1 -; CHECK32-NEXT: ret -; CHECK32-NEXT: .LBB3_2: -; CHECK32-NEXT: mv a1, zero ; CHECK32-NEXT: addi a0, a0, -1 +; CHECK32-NEXT: xor a0, a1, a0 ; CHECK32-NEXT: ret ; ; CHECK64-LABEL: selecti32i64: ; CHECK64: # %bb.0: -; CHECK64-NEXT: sext.w a1, a0 -; CHECK64-NEXT: lui a0, 524288 -; CHECK64-NEXT: bltz a1, .LBB3_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addiw a0, a0, -1 -; CHECK64-NEXT: .LBB3_2: +; CHECK64-NEXT: sraiw a0, a0, 31 +; CHECK64-NEXT: lui a1, 524288 +; CHECK64-NEXT: addiw a1, a1, -1 +; CHECK64-NEXT: xor a0, a0, a1 ; CHECK64-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -125,22 +110,14 @@ define i32 @selecti32i32(i32 %a) { ; CHECK32-LABEL: selecti32i32: ; CHECK32: # %bb.0: -; CHECK32-NEXT: mv a1, a0 -; CHECK32-NEXT: addi a0, zero, 84 -; CHECK32-NEXT: bgez a1, .LBB5_2 -; CHECK32-NEXT: # %bb.1: -; CHECK32-NEXT: addi a0, zero, -85 -; CHECK32-NEXT: .LBB5_2: +; CHECK32-NEXT: srai a0, a0, 31 +; CHECK32-NEXT: xori a0, a0, 84 ; CHECK32-NEXT: ret ; ; CHECK64-LABEL: selecti32i32: ; CHECK64: # %bb.0: -; CHECK64-NEXT: sext.w a1, a0 -; CHECK64-NEXT: addi a0, zero, 84 -; CHECK64-NEXT: bgez a1, .LBB5_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addi a0, zero, -85 -; CHECK64-NEXT: .LBB5_2: +; CHECK64-NEXT: sraiw a0, a0, 31 +; CHECK64-NEXT: xori a0, a0, 84 ; CHECK64-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -150,22 +127,14 @@ define i8 @selecti32i8(i32 %a) { ; CHECK32-LABEL: selecti32i8: ; CHECK32: # %bb.0: -; CHECK32-NEXT: mv a1, a0 -; CHECK32-NEXT: addi a0, zero, 84 -; CHECK32-NEXT: bgez a1, .LBB6_2 -; CHECK32-NEXT: # %bb.1: -; CHECK32-NEXT: addi a0, zero, -85 -; CHECK32-NEXT: .LBB6_2: +; CHECK32-NEXT: srai a0, a0, 31 +; CHECK32-NEXT: xori a0, a0, 84 ; CHECK32-NEXT: ret ; ; CHECK64-LABEL: selecti32i8: ; CHECK64: # %bb.0: -; CHECK64-NEXT: sext.w a1, a0 -; CHECK64-NEXT: addi a0, zero, 84 -; CHECK64-NEXT: bgez a1, .LBB6_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addi a0, zero, -85 -; CHECK64-NEXT: .LBB6_2: +; CHECK64-NEXT: sraiw a0, a0, 31 +; CHECK64-NEXT: xori a0, a0, 84 ; CHECK64-NEXT: ret %c = icmp sgt i32 %a, -1 %s = select i1 %c, i8 84, i8 -85 @@ -176,23 +145,15 @@ ; CHECK32-LABEL: selecti8i32: ; CHECK32: # %bb.0: ; CHECK32-NEXT: slli a0, a0, 24 -; CHECK32-NEXT: srai a1, a0, 24 -; CHECK32-NEXT: addi a0, zero, 84 -; CHECK32-NEXT: bgez a1, .LBB7_2 -; CHECK32-NEXT: # %bb.1: -; CHECK32-NEXT: addi a0, zero, -85 -; CHECK32-NEXT: .LBB7_2: +; CHECK32-NEXT: srai a0, a0, 31 +; CHECK32-NEXT: xori a0, a0, 84 ; CHECK32-NEXT: ret ; ; CHECK64-LABEL: selecti8i32: ; CHECK64: # %bb.0: ; CHECK64-NEXT: slli a0, a0, 56 -; CHECK64-NEXT: srai a1, a0, 56 -; CHECK64-NEXT: addi a0, zero, 84 -; CHECK64-NEXT: bgez a1, .LBB7_2 -; CHECK64-NEXT: # %bb.1: -; CHECK64-NEXT: addi a0, zero, -85 -; CHECK64-NEXT: .LBB7_2: +; CHECK64-NEXT: srai a0, a0, 63 +; CHECK64-NEXT: xori a0, a0, 84 ; CHECK64-NEXT: ret %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 Index: llvm/test/CodeGen/X86/pr16031.ll =================================================================== --- llvm/test/CodeGen/X86/pr16031.ll +++ llvm/test/CodeGen/X86/pr16031.ll @@ -7,15 +7,14 @@ ; CHECK-NEXT: pushl %esi ; CHECK-NEXT: testb $1, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl $-12, %eax -; CHECK-NEXT: movl $-1, %edx -; CHECK-NEXT: cmovel %edx, %eax -; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: movl $-1, %ecx +; CHECK-NEXT: cmovel %ecx, %eax +; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: movl %eax, %esi ; CHECK-NEXT: addl $-1, %esi -; CHECK-NEXT: movl $-1, %esi -; CHECK-NEXT: adcl $-1, %esi -; CHECK-NEXT: cmovsl %ecx, %eax -; CHECK-NEXT: cmovsl %ecx, %edx +; CHECK-NEXT: adcl $-1, %ecx +; CHECK-NEXT: cmovsl %edx, %eax +; CHECK-NEXT: xorl %edx, %edx ; CHECK-NEXT: popl %esi ; CHECK-NEXT: retl entry: Index: llvm/test/CodeGen/X86/select-constant-xor.ll =================================================================== --- llvm/test/CodeGen/X86/select-constant-xor.ll +++ llvm/test/CodeGen/X86/select-constant-xor.ll @@ -18,10 +18,9 @@ define i64 @selecti64i64(i64 %a) { ; CHECK-LABEL: selecti64i64: ; CHECK: # %bb.0: -; CHECK-NEXT: testq %rdi, %rdi -; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF -; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000 -; CHECK-NEXT: cmovnsq %rcx, %rax +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: sarq $63, %rax +; CHECK-NEXT: xorq $2147483647, %rax # imm = 0x7FFFFFFF ; CHECK-NEXT: retq %c = icmp sgt i64 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -45,10 +44,9 @@ define i64 @selecti32i64(i32 %a) { ; CHECK-LABEL: selecti32i64: ; CHECK: # %bb.0: -; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF -; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000 -; CHECK-NEXT: cmovnsq %rcx, %rax +; CHECK-NEXT: sarl $31, %edi +; CHECK-NEXT: movslq %edi, %rax +; CHECK-NEXT: xorq $2147483647, %rax # imm = 0x7FFFFFFF ; CHECK-NEXT: retq %c = icmp sgt i32 %a, -1 %s = select i1 %c, i64 2147483647, i64 -2147483648 @@ -74,10 +72,9 @@ define i32 @selecti32i32(i32 %a) { ; CHECK-LABEL: selecti32i32: ; CHECK: # %bb.0: -; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: movl $84, %ecx -; CHECK-NEXT: movl $-85, %eax -; CHECK-NEXT: cmovnsl %ecx, %eax +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: sarl $31, %eax +; CHECK-NEXT: xorl $84, %eax ; CHECK-NEXT: retq %c = icmp sgt i32 %a, -1 %s = select i1 %c, i32 84, i32 -85 @@ -87,10 +84,9 @@ define i8 @selecti32i8(i32 %a) { ; CHECK-LABEL: selecti32i8: ; CHECK: # %bb.0: -; CHECK-NEXT: testl %edi, %edi -; CHECK-NEXT: movl $84, %ecx -; CHECK-NEXT: movl $171, %eax -; CHECK-NEXT: cmovnsl %ecx, %eax +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: sarl $31, %eax +; CHECK-NEXT: xorb $84, %al ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: retq %c = icmp sgt i32 %a, -1 @@ -101,10 +97,9 @@ define i32 @selecti8i32(i8 %a) { ; CHECK-LABEL: selecti8i32: ; CHECK: # %bb.0: -; CHECK-NEXT: testb %dil, %dil -; CHECK-NEXT: movl $84, %ecx -; CHECK-NEXT: movl $-85, %eax -; CHECK-NEXT: cmovnsl %ecx, %eax +; CHECK-NEXT: sarb $7, %dil +; CHECK-NEXT: movsbl %dil, %eax +; CHECK-NEXT: xorl $84, %eax ; CHECK-NEXT: retq %c = icmp sgt i8 %a, -1 %s = select i1 %c, i32 84, i32 -85 Index: llvm/test/CodeGen/X86/smul_fix_sat.ll =================================================================== --- llvm/test/CodeGen/X86/smul_fix_sat.ll +++ llvm/test/CodeGen/X86/smul_fix_sat.ll @@ -387,15 +387,14 @@ ; X86-NEXT: calll __mulodi4 ; X86-NEXT: addl $20, %esp ; X86-NEXT: .cfi_adjust_cfa_offset -20 -; X86-NEXT: xorl %ecx, %ecx -; X86-NEXT: testl %edx, %edx -; X86-NEXT: setns %cl -; X86-NEXT: addl $2147483647, %ecx # imm = 0x7FFFFFFF ; X86-NEXT: movl %edx, %esi ; X86-NEXT: sarl $31, %esi +; X86-NEXT: movl %esi, %ecx +; X86-NEXT: xorl $-2147483648, %ecx # imm = 0x80000000 ; X86-NEXT: cmpl $0, (%esp) ; X86-NEXT: cmovnel %esi, %eax -; X86-NEXT: cmovnel %ecx, %edx +; X86-NEXT: cmovel %edx, %ecx +; X86-NEXT: movl %ecx, %edx ; X86-NEXT: addl $4, %esp ; X86-NEXT: .cfi_def_cfa_offset 12 ; X86-NEXT: popl %esi Index: llvm/test/CodeGen/X86/sshl_sat.ll =================================================================== --- llvm/test/CodeGen/X86/sshl_sat.ll +++ llvm/test/CodeGen/X86/sshl_sat.ll @@ -229,39 +229,38 @@ ; X86-NEXT: pushl %ebx ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi +; X86-NEXT: pushl %eax ; X86-NEXT: movb {{[0-9]+}}(%esp), %cl +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebx -; X86-NEXT: movl %eax, %ebp -; X86-NEXT: shll %cl, %ebp -; X86-NEXT: shldl %cl, %eax, %ebx -; X86-NEXT: xorl %edx, %edx +; X86-NEXT: movl %edx, %ebx +; X86-NEXT: shll %cl, %ebx +; X86-NEXT: movl %eax, %esi +; X86-NEXT: shldl %cl, %edx, %esi +; X86-NEXT: xorl %edi, %edi ; X86-NEXT: testb $32, %cl -; X86-NEXT: cmovnel %ebp, %ebx -; X86-NEXT: cmovnel %edx, %ebp -; X86-NEXT: movl %ebx, %edx -; X86-NEXT: sarl %cl, %edx -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: sarl $31, %edi +; X86-NEXT: cmovnel %ebx, %esi +; X86-NEXT: cmovel %ebx, %edi +; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: movl %esi, %ebx +; X86-NEXT: sarl %cl, %ebx +; X86-NEXT: movl %esi, %ebp +; X86-NEXT: sarl $31, %ebp ; X86-NEXT: testb $32, %cl -; X86-NEXT: cmovel %edx, %edi -; X86-NEXT: movl %ebp, %esi -; X86-NEXT: shrdl %cl, %ebx, %esi +; X86-NEXT: cmovel %ebx, %ebp +; X86-NEXT: shrdl %cl, %esi, %edi ; X86-NEXT: testb $32, %cl -; X86-NEXT: cmovnel %edx, %esi -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: xorl %ecx, %edi -; X86-NEXT: xorl %eax, %esi -; X86-NEXT: xorl %edx, %edx -; X86-NEXT: testl %ecx, %ecx -; X86-NEXT: movl $-1, %eax -; X86-NEXT: movl $0, %ecx -; X86-NEXT: cmovsl %ecx, %eax -; X86-NEXT: sets %dl -; X86-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF -; X86-NEXT: orl %edi, %esi -; X86-NEXT: cmovel %ebp, %eax -; X86-NEXT: cmovel %ebx, %edx +; X86-NEXT: cmovnel %ebx, %edi +; X86-NEXT: xorl %eax, %ebp +; X86-NEXT: xorl {{[0-9]+}}(%esp), %edi +; X86-NEXT: sarl $31, %eax +; X86-NEXT: movl %eax, %edx +; X86-NEXT: xorl $2147483647, %edx # imm = 0x7FFFFFFF +; X86-NEXT: orl %ebp, %edi +; X86-NEXT: notl %eax +; X86-NEXT: cmovel (%esp), %eax # 4-byte Folded Reload +; X86-NEXT: cmovel %esi, %edx +; X86-NEXT: addl $4, %esp ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi ; X86-NEXT: popl %ebx