diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -10867,10 +10867,9 @@
           BTB->DefaultProb -= DefaultProb / 2;
         }
 
-        if (FallthroughUnreachable) {
-          // Skip the range check if the fallthrough block is unreachable.
+        // Skip the range check if the fallthrough block is unreachable.
+        if (FallthroughUnreachable)
           BTB->OmitRangeCheck = true;
-        }
 
         // If we're in the right place, emit the bit test header right now.
         if (CurMBB == SwitchMBB) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1861,9 +1861,9 @@
       // test, and delete the last bit test.
 
       MachineBasicBlock *NextMBB;
-      if (BTB.ContiguousRange && j + 2 == ej) {
-        // Second-to-last bit-test with contiguous range: fall through to the
-        // target of the final bit test.
+      if ((BTB.ContiguousRange || BTB.OmitRangeCheck) && j + 2 == ej) {
+        // Second-to-last bit-test with contiguous range or omitted range
+        // check: fall through to the target of the final bit test.
         NextMBB = BTB.Cases[j + 1].TargetBB;
       } else if (j + 1 == ej) {
         // For the last bit test, fall through to Default.
@@ -1880,7 +1880,7 @@
       SDB->clear();
       CodeGenAndEmitDAG();
 
-      if (BTB.ContiguousRange && j + 2 == ej) {
+      if ((BTB.ContiguousRange || BTB.OmitRangeCheck) && j + 2 == ej) {
         // Since we're not going to use the final bit test, remove it.
         BTB.Cases.pop_back();
         break;
diff --git a/llvm/test/CodeGen/X86/SwitchLowering.ll b/llvm/test/CodeGen/X86/SwitchLowering.ll
--- a/llvm/test/CodeGen/X86/SwitchLowering.ll
+++ b/llvm/test/CodeGen/X86/SwitchLowering.ll
@@ -62,10 +62,10 @@
 
 declare void @foo(i8)
 
+; PR50080
+; The important part of this test is that we emit only 1 bit test rather than
+; 2 since the default BB of the switch is unreachable.
 define i32 @baz(i32 %0) {
-; FIXME: Get rid of this conditional jump and bit test in .LBB1_1.
-; FIXME: .LBB1_4 should not have .LBB1_1 as a predacessor, or be past the end
-; FIXME: of the function.
 ; CHECK-LABEL: baz:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xorl %eax, %eax
@@ -73,16 +73,11 @@
 ; CHECK-NEXT:    movl $13056, %edx # imm = 0x3300
 ; CHECK-NEXT:    btl %ecx, %edx
 ; CHECK-NEXT:    jae .LBB1_1
-; CHECK-NEXT:  # %bb.3: # %return
+; CHECK-NEXT:  # %bb.2: # %return
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:  .LBB1_1:
-; CHECK-NEXT:    movl $48, %eax
-; CHECK-NEXT:    btl %ecx, %eax
-; CHECK-NEXT:    jae .LBB1_4
-; CHECK-NEXT:  # %bb.2: # %sw.epilog8
+; CHECK-NEXT:  .LBB1_1: # %sw.epilog8
 ; CHECK-NEXT:    movl $1, %eax
 ; CHECK-NEXT:    retl
-; CHECK-NEXT:  .LBB1_4: # %if.then.unreachabledefault
   switch i32 %0, label %if.then.unreachabledefault [
     i32 4, label %sw.epilog8
     i32 5, label %sw.epilog8
diff --git a/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll b/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
--- a/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
+++ b/llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
@@ -7,8 +7,6 @@
 
 ; PR50080
 define i32 @baz(i32 %0) {
-; FIXME: Get rid of this conditional jump and bit test in bb.5.
-; FIXME: bb.2 should not have bb.5 as a predacessor.
 ; CHECK-SISEL: bb.0 (%ir-block.1):
 ; CHECK-SISEL:   successors: %bb.4(0x80000000); %bb.4(100.00%)
 ; CHECK-SISEL:   liveins: $edi
@@ -17,27 +15,21 @@
 ; CHECK-SISEL:   %3:gr32 = COPY %1:gr32
 ; CHECK-SISEL: bb.4 (%ir-block.1):
 ; CHECK-SISEL: ; predecessors: %bb.0
-; CHECK-SISEL:   successors: %bb.3(0x55555555), %bb.5(0x2aaaaaab); %bb.3(66.67%), %bb.5(33.33%)
+; CHECK-SISEL:   successors: %bb.3(0x55555555), %bb.1(0x2aaaaaab); %bb.3(66.67%), %bb.1(33.33%)
 ; CHECK-SISEL:   %4:gr32 = MOV32ri 13056
 ; CHECK-SISEL:   BT32rr killed %4:gr32, %3:gr32, implicit-def $eflags
 ; CHECK-SISEL:   JCC_1 %bb.3, 2, implicit $eflags
+; CHECK-SISEL:   JMP_1 %bb.1
 ; CHECK-SISEL: bb.5 (%ir-block.1):
-; CHECK-SISEL: ; predecessors: %bb.4
-; CHECK-SISEL:   successors: %bb.1(0x80000000), %bb.2(0x00000000); %bb.1(100.00%), %bb.2(0.00%)
-; CHECK-SISEL:   %5:gr32 = MOV32ri 48
-; CHECK-SISEL:   BT32rr killed %5:gr32, %3:gr32, implicit-def $eflags
-; CHECK-SISEL:   JCC_1 %bb.1, 2, implicit $eflags
-; CHECK-SISEL:   JMP_1 %bb.2
 ; CHECK-SISEL: bb.1.sw.epilog8:
-; CHECK-SISEL: ; predecessors: %bb.5
+; CHECK-SISEL: ; predecessors: %bb.4
 ; CHECK-SISEL:   successors: %bb.3(0x80000000); %bb.3(100.00%)
-; CHECK-SISEL:   %6:gr32 = MOV32ri 1
+; CHECK-SISEL:   %5:gr32 = MOV32ri 1
 ; CHECK-SISEL:   JMP_1 %bb.3
 ; CHECK-SISEL: bb.2.if.then.unreachabledefault:
-; CHECK-SISEL: ; predecessors: %bb.5
 ; CHECK-SISEL: bb.3.return:
 ; CHECK-SISEL: ; predecessors: %bb.4, %bb.1
-; CHECK-SISEL:   %0:gr32 = PHI %2:gr32, %bb.4, %6:gr32, %bb.1
+; CHECK-SISEL:   %0:gr32 = PHI %2:gr32, %bb.4, %5:gr32, %bb.1
 ; CHECK-SISEL:   $eax = COPY %0:gr32
 ; CHECK-SISEL:   RET 0, $eax