Index: llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll =================================================================== --- llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll +++ llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll @@ -378,6 +378,58 @@ ret void } +define void @masked_gather() { +; CHECK-LABEL: 'masked_gather' +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %NXV4F64 = call @llvm.masked.gather.nxv4f64.nxv4p0f64( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %NXV2F64 = call @llvm.masked.gather.nxv2f64.nxv2p0f64( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %NXV8F32 = call @llvm.masked.gather.nxv8f32.nxv8p0f32( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %NXV4F32 = call @llvm.masked.gather.nxv4f32.nxv4p0f32( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %NXV2F32 = call @llvm.masked.gather.nxv2f32.nxv2p0f32( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: %NXV16I16 = call @llvm.masked.gather.nxv16i16.nxv16p0i16( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %NXV8I16 = call @llvm.masked.gather.nxv8i16.nxv8p0i16( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %NXV4I16 = call @llvm.masked.gather.nxv4i16.nxv4p0i16( undef, i32 1, undef, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + %NXV4F64 = call @llvm.masked.gather.nxv4f64( undef, i32 1, undef, undef) + %NXV2F64 = call @llvm.masked.gather.nxv2f64( undef, i32 1, undef, undef) + + %NXV8F32 = call @llvm.masked.gather.nxv8f32( undef, i32 1, undef, undef) + %NXV4F32 = call @llvm.masked.gather.nxv4f32( undef, i32 1, undef, undef) + %NXV2F32 = call @llvm.masked.gather.nxv2f32( undef, i32 1, undef, undef) + + %NXV16I16 = call @llvm.masked.gather.nxv16i16( undef, i32 1, undef, undef) + %NXV8I16 = call @llvm.masked.gather.nxv8i16( undef, i32 1, undef, undef) + %NXV4I16 = call @llvm.masked.gather.nxv4i16( undef, i32 1, undef, undef) + + ret void +} + +define void @masked_scatter() { +; CHECK-LABEL: 'masked_scatter' +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.nxv4f64.nxv4p0f64( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.nxv2f64.nxv2p0f64( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: call void @llvm.masked.scatter.nxv8f32.nxv8p0f32( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.nxv4f32.nxv4p0f32( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: call void @llvm.masked.scatter.nxv2f32.nxv2p0f32( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 256 for instruction: call void @llvm.masked.scatter.nxv16i16.nxv16p0i16( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: call void @llvm.masked.scatter.nxv8i16.nxv8p0i16( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: call void @llvm.masked.scatter.nxv4i16.nxv4p0i16( undef, undef, i32 1, undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void +; + call void @llvm.masked.scatter.nxv4f64( undef, undef, i32 1, undef) + call void @llvm.masked.scatter.nxv2f64( undef, undef, i32 1, undef) + + call void @llvm.masked.scatter.nxv8f32( undef, undef, i32 1, undef) + call void @llvm.masked.scatter.nxv4f32( undef, undef, i32 1, undef) + call void @llvm.masked.scatter.nxv2f32( undef, undef, i32 1, undef) + + call void @llvm.masked.scatter.nxv16i16( undef, undef, i32 1, undef) + call void @llvm.masked.scatter.nxv8i16( undef, undef, i32 1, undef) + call void @llvm.masked.scatter.nxv4i16( undef, undef, i32 1, undef) + + ret void +} + declare @llvm.experimental.vector.splice.nxv2i1(, , i32) declare @llvm.experimental.vector.splice.nxv4i1(, , i32) declare @llvm.experimental.vector.splice.nxv8i1(, , i32) @@ -407,5 +459,21 @@ declare @llvm.experimental.vector.splice.nxv16f32(, , i32) declare @llvm.experimental.vector.splice.nxv2f64(, , i32) declare @llvm.experimental.vector.splice.nxv4f64(, , i32) +declare @llvm.masked.gather.nxv4f64(, i32, , ) +declare @llvm.masked.gather.nxv2f64(, i32, , ) +declare @llvm.masked.gather.nxv8f32(, i32, , ) +declare @llvm.masked.gather.nxv4f32(, i32, , ) +declare @llvm.masked.gather.nxv2f32(, i32, , ) +declare @llvm.masked.gather.nxv16i16(, i32, , ) +declare @llvm.masked.gather.nxv8i16(, i32, , ) +declare @llvm.masked.gather.nxv4i16(, i32, , ) +declare void @llvm.masked.scatter.nxv4f64(, , i32, ) +declare void @llvm.masked.scatter.nxv2f64(, , i32, ) +declare void @llvm.masked.scatter.nxv8f32(, , i32, ) +declare void @llvm.masked.scatter.nxv4f32(, , i32, ) +declare void @llvm.masked.scatter.nxv2f32(, , i32, ) +declare void @llvm.masked.scatter.nxv16i16(, , i32, ) +declare void @llvm.masked.scatter.nxv8i16(, , i32, ) +declare void @llvm.masked.scatter.nxv4i16(, , i32, ) attributes #0 = { "target-features"="+sve,+bf16" }