Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -546,6 +546,12 @@ /// should be stack expanded. bool isShuffleMaskLegal(ArrayRef M, EVT VT) const override; + /// Return true if lowering to a jump table is suitable for a set of case + /// clusters which may contain NumCases cases, Range range of values. + virtual bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases, + uint64_t Range, ProfileSummaryInfo *PSI, + BlockFrequencyInfo *BFI) const; + /// Return the ISD::SETCC ValueType. EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const override; Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -10744,6 +10744,17 @@ isConcatMask(M, VT, VT.getSizeInBits() == 128)); } +bool AArch64TargetLowering::isSuitableForJumpTable( + const SwitchInst *SI, uint64_t NumCases, uint64_t Range, + ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) const { + // On TargetLowering::isSuitableForJumpTable, the minimum size is not checked. + // Check the minimum NumCases. The number 16 has been decided by benchmark + // scores. + if (NumCases <= 16) + return false; + return TargetLowering::isSuitableForJumpTable(SI, NumCases, Range, PSI, BFI); +} + /// getVShiftImm - Check if this is a valid build_vector for the immediate /// operand of a vector shift operation, where all the elements of the /// build_vector must have the same constant integer value. Index: llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll =================================================================== --- llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll +++ llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll @@ -31,6 +31,7 @@ ; CHECK: bb.4.case200: ; CHECK: successors: %bb.5(0x80000000) ; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[C2]] + ; CHECK: G_BR %bb.5 ; CHECK: bb.5.return: ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[ADD]](s32), %bb.2, [[ADD1]](s32), %bb.3, [[ADD2]](s32), %bb.4 ; CHECK: $w0 = COPY [[PHI]](s32) @@ -163,32 +164,54 @@ define i32 @jt_test(i32 %x) { ; CHECK-LABEL: name: jt_test ; CHECK: bb.1.entry: - ; CHECK: successors: %bb.4(0x40000000), %bb.5(0x40000000) + ; CHECK: successors: %bb.3(0x40000000), %bb.5(0x40000000) ; CHECK: liveins: $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 71 - ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 - ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 - ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 - ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C4]] - ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SUB]](s32) - ; CHECK: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[C]](s32) - ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ugt), [[ZEXT]](s64), [[ZEXT1]] - ; CHECK: G_BRCOND [[ICMP]](s1), %bb.4 + ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 + ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 34 + ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 40 + ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 56 + ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 75 + ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 + ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 42 + ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C]] + ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 + ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB]](s32), [[C8]] + ; CHECK: G_BRCOND [[ICMP]](s1), %bb.3 + ; CHECK: G_BR %bb.5 ; CHECK: bb.5.entry: - ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab) - ; CHECK: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0 - ; CHECK: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[ZEXT]](s64) + ; CHECK: successors: %bb.2(0x40000000), %bb.6(0x40000000) + ; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C1]] + ; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ule), [[SUB1]](s32), [[C9]] + ; CHECK: G_BRCOND [[ICMP1]](s1), %bb.2 + ; CHECK: G_BR %bb.6 + ; CHECK: bb.6.entry: + ; CHECK: successors: %bb.2(0x40000000), %bb.7(0x40000000) + ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C2]] + ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 + ; CHECK: G_BR %bb.7 + ; CHECK: bb.7.entry: + ; CHECK: successors: %bb.2(0x40000000), %bb.8(0x40000000) + ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C3]] + ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 + ; CHECK: G_BR %bb.8 + ; CHECK: bb.8.entry: + ; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000) + ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C4]] + ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.2 + ; CHECK: G_BR %bb.4 ; CHECK: bb.2.sw.bb: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C2]] + ; CHECK: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[C6]] ; CHECK: G_BR %bb.4 ; CHECK: bb.3.sw.bb1: ; CHECK: successors: %bb.4(0x80000000) - ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C1]] + ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C5]] + ; CHECK: G_BR %bb.4 ; CHECK: bb.4.return: - ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C3]](s32), %bb.1, [[C3]](s32), %bb.5 + ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C7]](s32), %bb.8 ; CHECK: $w0 = COPY [[PHI]](s32) ; CHECK: RET_ReallyLR implicit $w0 entry: @@ -776,6 +799,7 @@ ; CHECK: G_BR %bb.56 ; CHECK: bb.55.bb56: ; CHECK: successors: %bb.56(0x80000000) + ; CHECK: G_BR %bb.56 ; CHECK: bb.56.bb57: ; CHECK: successors: %bb.59(0x80000000) ; CHECK: [[PHI:%[0-9]+]]:_(s64) = G_PHI [[C56]](s64), %bb.1, [[C57]](s64), %bb.2, [[C58]](s64), %bb.3, [[C59]](s64), %bb.4, [[C60]](s64), %bb.5, [[C61]](s64), %bb.6, [[C62]](s64), %bb.7, [[C63]](s64), %bb.8, [[C64]](s64), %bb.9, [[C65]](s64), %bb.10, [[C66]](s64), %bb.11, [[C67]](s64), %bb.12, [[C68]](s64), %bb.13, [[C69]](s64), %bb.14, [[C70]](s64), %bb.15, [[C71]](s64), %bb.16, [[C72]](s64), %bb.17, [[C73]](s64), %bb.18, [[C74]](s64), %bb.19, [[C75]](s64), %bb.20, [[C76]](s64), %bb.21, [[C77]](s64), %bb.22, [[C78]](s64), %bb.23, [[C79]](s64), %bb.24, [[C80]](s64), %bb.25, [[C81]](s64), %bb.26, [[C82]](s64), %bb.27, [[C83]](s64), %bb.28, [[C84]](s64), %bb.29, [[C85]](s64), %bb.30, [[C86]](s64), %bb.31, [[C87]](s64), %bb.32, [[C88]](s64), %bb.33, [[C89]](s64), %bb.34, [[C90]](s64), %bb.35, [[C91]](s64), %bb.36, [[C92]](s64), %bb.37, [[C93]](s64), %bb.38, [[C94]](s64), %bb.39, [[C95]](s64), %bb.40, [[C96]](s64), %bb.41, [[C97]](s64), %bb.42, [[C98]](s64), %bb.43, [[C99]](s64), %bb.44, [[C100]](s64), %bb.45, [[C101]](s64), %bb.46, [[C102]](s64), %bb.47, [[C103]](s64), %bb.48, [[C104]](s64), %bb.49, [[C105]](s64), %bb.50, [[C106]](s64), %bb.51, [[C107]](s64), %bb.52, [[C108]](s64), %bb.53, [[C109]](s64), %bb.54, [[C110]](s64), %bb.55 @@ -815,6 +839,7 @@ ; CHECK: BL @wibble, csr_aarch64_aapcs_thisreturn, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1 ; CHECK: [[COPY6:%[0-9]+]]:_(p0) = COPY [[COPY]](p0) ; CHECK: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp + ; CHECK: G_BR %bb.59 ; CHECK: bb.59.bb68: ; CHECK: RET_ReallyLR ; CHECK: bb.60.bb69: @@ -1205,6 +1230,7 @@ ; CHECK: G_BR %bb.16 ; CHECK: bb.15.sw.bb12.i: ; CHECK: successors: %bb.16(0x80000000) + ; CHECK: G_BR %bb.16 ; CHECK: bb.16.land.rhs.lr.ph: ; CHECK: successors: %bb.17(0x40000000), %bb.18(0x40000000) ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[C13]](s32), %bb.24, [[C14]](s32), %bb.9, [[C15]](s32), %bb.10, [[C16]](s32), %bb.11, [[C17]](s32), %bb.12, [[C18]](s32), %bb.13, [[C19]](s32), %bb.14, [[C20]](s32), %bb.15 @@ -1322,6 +1348,7 @@ ; CHECK: bb.3.sw.bb1: ; CHECK: successors: %bb.4(0x80000000) ; CHECK: [[MUL:%[0-9]+]]:_(s32) = nsw G_MUL [[COPY]], [[C2]] + ; CHECK: G_BR %bb.4 ; CHECK: bb.4.return: ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[MUL]](s32), %bb.3, [[ADD]](s32), %bb.2, [[C4]](s32), %bb.5 ; CHECK: $w0 = COPY [[PHI]](s32) @@ -1358,6 +1385,7 @@ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; CHECK: G_BR %bb.2 ; CHECK: bb.2.bb1: ; CHECK: successors: %bb.2(0x40000000), %bb.6(0x40000000) ; CHECK: [[PHI:%[0-9]+]]:_(s32) = G_PHI [[DEF]](s32), %bb.1, [[C3]](s32), %bb.3, [[C4]](s32), %bb.4, [[C5]](s32), %bb.2 Index: llvm/test/CodeGen/AArch64/arm64-jumptable.ll =================================================================== --- llvm/test/CodeGen/AArch64/arm64-jumptable.ll +++ llvm/test/CodeGen/AArch64/arm64-jumptable.ll @@ -26,9 +26,9 @@ } ; CHECK-LABEL: sum: -; CHECK: adrp {{x[0-9]+}}, LJTI0_0@PAGE -; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF +; CHECK-NOT: adrp {{x[0-9]+}}, LJTI0_0@PAGE +; CHECK-NOT: add {{x[0-9]+}}, {{x[0-9]+}}, LJTI0_0@PAGEOFF ; CHECK-LINUX-LABEL: sum: -; CHECK-LINUX: adrp {{x[0-9]+}}, .LJTI0_0 -; CHECK-LINUX: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0 +; CHECK-LINUX-NOT: adrp {{x[0-9]+}}, .LJTI0_0 +; CHECK-LINUX-NOT: add {{x[0-9]+}}, {{x[0-9]+}}, :lo12:.LJTI0_0 Index: llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll =================================================================== --- llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll +++ llvm/test/CodeGen/AArch64/bti-branch-relaxation.ll @@ -9,8 +9,7 @@ %and = and i32 %call, 2 %cmp = icmp eq i32 %and, 0 br i1 %cmp, label %if.then, label %if.else -; CHECK: tbz -; CHECK-NEXT: b +; CHECK: bti if.then: ; preds = %entry switch i64 %v, label %sw.epilog [ i64 0, label %sw.bb Index: llvm/test/CodeGen/AArch64/jump-table-32.ll =================================================================== --- llvm/test/CodeGen/AArch64/jump-table-32.ll +++ llvm/test/CodeGen/AArch64/jump-table-32.ll @@ -9,13 +9,6 @@ i32 2, label %lbl3 i32 4, label %lbl4 ] -; CHECK: adrp [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE -; CHECK: mov w[[INDEX:[0-9]+]], w0 -; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF -; CHECK: adr [[BASE_BLOCK:x[0-9]+]], LBB0_2 -; CHECK: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], x[[INDEX]]] -; CHECK: add [[DEST:x[0-9]+]], [[BASE_BLOCK]], x[[OFFSET]], lsl #2 -; CHECK: br [[DEST]] def: ret i32 0 @@ -34,9 +27,4 @@ } -; CHECK: LJTI0_0: -; CHECK-NEXT: .byte -; CHECK-NEXT: .byte -; CHECK-NEXT: .byte -; CHECK-NEXT: .byte -; CHECK-NEXT: .byte +; CHECK-NOT LJTI0_0: Index: llvm/test/CodeGen/AArch64/jump-table-exynos.ll =================================================================== --- llvm/test/CodeGen/AArch64/jump-table-exynos.ll +++ llvm/test/CodeGen/AArch64/jump-table-exynos.ll @@ -10,18 +10,8 @@ i32 2, label %lbl3 i32 4, label %lbl4 ] -; CHECK-LABEL: test_jumptable: -; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0 -; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0 -; CHECK: [[PCREL_LBL:.Ltmp.*]]: -; CHECK-NEXT: adr [[PCBASE:x[0-9]+]], [[PCREL_LBL]] -; CHECK: ldrsw x[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #2] -; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]] -; CHECK: br [[DEST]] - -; CHECK: .LJTI0_0: -; CHECK-NEXT: .word .LBB{{.*}}-[[PCREL_LBL]] +; CHECK-NOT: .LJTI0_0: def: ret i32 0 @@ -47,15 +37,8 @@ i32 2, label %lbl3 i32 4, label %lbl4 ] -; CHECK-LABEL: test_jumptable_minsize: -; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI1_0 -; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI1_0 -; CHECK: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}] -; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK: br [[DEST]] - +; CHECK-NOT: .LJTI0_1: def: ret i32 0 Index: llvm/test/CodeGen/AArch64/jump-table.ll =================================================================== --- llvm/test/CodeGen/AArch64/jump-table.ll +++ llvm/test/CodeGen/AArch64/jump-table.ll @@ -4,7 +4,6 @@ ; RUN: llc -no-integrated-as -code-model=tiny -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -aarch64-enable-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-TINY %s define i32 @test_jumptable(i32 %in) { -; CHECK: test_jumptable switch i32 %in, label %def [ i32 0, label %lbl1 @@ -12,45 +11,6 @@ i32 2, label %lbl3 i32 4, label %lbl4 ] -; CHECK-LABEL: test_jumptable: -; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0 -; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0 -; CHECK: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}] -; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK: br [[DEST]] - -; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g0_nc:.LJTI0_0 -; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0 -; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0 -; CHECK-LARGE: movk x[[JTADDR]], #:abs_g3:.LJTI0_0 -; CHECK-LARGE: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK-LARGE: ldrb w[[OFFSET:[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}] -; CHECK-LARGE: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK-LARGE: br [[DEST]] - -; CHECK-PIC-LABEL: test_jumptable: -; CHECK-PIC: adrp [[JTPAGE:x[0-9]+]], .LJTI0_0 -; CHECK-PIC: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI0_0 -; CHECK-PIC: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK-PIC: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}] -; CHECK-PIC: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK-PIC: br [[DEST]] - -; CHECK-IOS: adrp [[JTPAGE:x[0-9]+]], LJTI0_0@PAGE -; CHECK-IOS: add x[[JT:[0-9]+]], [[JTPAGE]], LJTI0_0@PAGEOFF -; CHECK-IOS: adr [[PCBASE:x[0-9]+]], [[JTBASE:LBB[0-9]+_[0-9]+]] -; CHECK-IOS: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}] -; CHECK-IOS: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK-IOS: br [[DEST]] - -; CHECK-TINY-LABEL: test_jumptable: -; CHECK-TINY: adr x[[JT:[0-9]+]], .LJTI0_0 -; CHECK-TINY: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK-TINY: ldrb w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}] -; CHECK-TINY: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK-TINY: br [[DEST]] - def: ret i32 0 @@ -69,14 +29,7 @@ } -; CHECK: .rodata - -; CHECK: .LJTI0_0: -; CHECK-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2 -; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 +; CHECK-NOT: .LJTI0_0: define i32 @test_jumptable16(i32 %in) { @@ -86,13 +39,6 @@ i32 2, label %lbl3 i32 4, label %lbl4 ] -; CHECK-LABEL: test_jumptable16: -; CHECK: adrp [[JTPAGE:x[0-9]+]], .LJTI1_0 -; CHECK: add x[[JT:[0-9]+]], [[JTPAGE]], {{#?}}:lo12:.LJTI1_0 -; CHECK: adr [[PCBASE:x[0-9]+]], [[JTBASE:.LBB[0-9]+_[0-9]+]] -; CHECK: ldrh w[[OFFSET:[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #1] -; CHECK: add [[DEST:x[0-9]+]], [[PCBASE]], x[[OFFSET]], lsl #2 -; CHECK: br [[DEST]] def: ret i32 0 @@ -112,41 +58,22 @@ } -; CHECK: .rodata -; CHECK: .p2align 1 -; CHECK: .LJTI1_0: -; CHECK-NEXT: .hword ([[JTBASE]]-[[JTBASE]])>>2 -; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-NEXT: .hword (.LBB{{.*}}-[[JTBASE]])>>2 +; CHECK-NOT: .LJTI1_0: + +; CHECK-LARGE-NOT: .LJTI1_0: + +; CHECK-TINY-NOT: .LJTI1_0: -; CHECK-PIC-NOT: .data_region ; CHECK-PIC-NOT: .LJTI0_0 -; CHECK-PIC: .LJTI0_0: -; CHECK-PIC-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2 -; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-PIC-NEXT: .byte (.LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-PIC-NOT: .end_data_region - -; CHECK-IOS: .section __TEXT,__const -; CHECK-IOS-NOT: .data_region -; CHECK-IOS: LJTI0_0: -; CHECK-IOS-NEXT: .byte ([[JTBASE]]-[[JTBASE]])>>2 -; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-IOS-NEXT: .byte (LBB{{.*}}-[[JTBASE]])>>2 -; CHECK-IOS-NOT: .end_data_region + +; CHECK-IOS-NOT: LJTI0_0: ; Compressing just the first table has the opportunity to truncate the vector of ; sizes. Make sure it doesn't. define i32 @test_twotables(i32 %in1, i32 %in2) { -; CHECK-LABEL: test_twotables: -; CHECK: .LJTI2_0 -; CHECK: .LJTI2_1 + +; CHECK-NOT: .LJTI2_0 +; CHECK-NOT: .LJTI2_1 switch i32 %in1, label %def [ i32 0, label %lbl1 Index: llvm/test/CodeGen/AArch64/max-jump-table.ll =================================================================== --- llvm/test/CodeGen/AArch64/max-jump-table.ll +++ llvm/test/CodeGen/AArch64/max-jump-table.ll @@ -28,21 +28,9 @@ i32 17, label %bb17 ] ; CHECK-LABEL: function jt1: -; CHECK-NEXT: Jump Tables: +; CHECK0-NEXT: Jump Tables: ; CHECK0-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17 ; CHECK0-NOT: %jump-table.1: -; CHECK4-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 -; CHECK4-NEXT: %jump-table.1: %bb.6 %bb.7 %bb.8 %bb.9 -; CHECK4-NEXT: %jump-table.2: %bb.10 %bb.11 %bb.12 %bb.13 -; CHECK4-NEXT: %jump-table.3: %bb.14 %bb.15 %bb.16 %bb.17 -; CHECK4-NOT: %jump-table.4: -; CHECK8-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 -; CHECK8-NEXT: %jump-table.1: %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17 -; CHECK8-NOT: %jump-table.2: -; CHECK16-NEXT: %jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17 -; CHECK16-NOT: %jump-table.1: -; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.5 %bb.6 %bb.7 %bb.8 %bb.9 %bb.10 %bb.11 %bb.12 %bb.13 %bb.14 %bb.15 %bb.16 %bb.17 -; CHECKM3-NOT: %jump-table.1: bb1: tail call void @ext(i32 1, i32 0) br label %return bb2: tail call void @ext(i32 2, i32 2) br label %return @@ -77,17 +65,7 @@ i32 15, label %bb6 ] ; CHECK-LABEL: function jt2: -; CHECK-NEXT: Jump Tables: -; CHECK0-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}} -; CHECK0-NOT: %jump-table.1: -; CHECK4-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4{{$}} -; CHECK4-NOT: %jump-table.1: -; CHECK8-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4{{$}} -; CHECK8-NOT: %jump-table.1: -; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}} -; CHECK16-NOT: %jump-table.1: -; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.7 %bb.5 %bb.6{{$}} -; CHECKM3-NOT: %jump-table.1: +; CHECK-NOT: Jump Tables: ; CHECK-DAG: End machine code for function jt2. bb1: tail call void @ext(i32 6, i32 1) br label %return @@ -119,20 +97,7 @@ i32 23, label %bb12 ] ; CHECK-LABEL: function jt3: -; CHECK-NEXT: Jump Tables: -; CHECK0-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12 -; CHECK0-NOT: %jump-table.1: -; CHECK4-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 -; CHECK4-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 -; CHECK4-NOT: %jump-table.2: -; CHECK8-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 -; CHECK8-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 -; CHECK8-NOT: %jump-table.2: -; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 -; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12 -; CHECK16-NOT: %jump-table.2: -; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 -; CHECKM3-NOT: %jump-table.1: +; CHECK-NOT: Jump Tables: ; CHECK-DAG: End machine code for function jt3. bb1: tail call void @ext(i32 1, i32 12) br label %return @@ -171,20 +136,7 @@ i32 23, label %bb12 ] ; CHECK-LABEL: function jt4: -; CHECK-NEXT: Jump Tables: -; CHECK0-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12 -; CHECK0-NOT: %jump-table.1: -; CHECK4-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 -; CHECK4-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 -; CHECK4-NOT: %jump-table.2: -; CHECK8-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 -; CHECK8-NEXT: %jump-table.1: %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 -; CHECK8-NOT: %jump-table.2: -; CHECK16-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 -; CHECK16-NEXT: %jump-table.1: %bb.8 %bb.13 %bb.9 %bb.10 %bb.13 %bb.11 %bb.12 -; CHECK16-NOT: %jump-table.2: -; CHECKM3-NEXT: %jump-table.0: %bb.1 %bb.2 %bb.3 %bb.4 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.13 %bb.5 %bb.6 %bb.7 %bb.8 %bb.13 %bb.9 %bb.10 -; CHECKM3-NOT: %jump-table.1: +; CHECK-NOT: Jump Tables: ; CHECK-DAG: End machine code for function jt4. bb1: tail call void @ext(i32 1, i32 12) br label %return Index: llvm/test/CodeGen/AArch64/min-jump-table.ll =================================================================== --- llvm/test/CodeGen/AArch64/min-jump-table.ll +++ llvm/test/CodeGen/AArch64/min-jump-table.ll @@ -13,7 +13,7 @@ ] ; CHECK-LABEL: function jt2: ; CHECK0-NEXT: Jump Tables: -; CHECK2-NEXT: Jump Tables: +; CHECK2-NOT: {{^}}Jump Tables: ; CHECK4-NOT: {{^}}Jump Tables: ; CHECK8-NOT: {{^}}Jump Tables: @@ -33,8 +33,8 @@ ] ; CHECK-LABEL: function jt4: ; CHECK0-NEXT: Jump Tables: -; CHECK2-NEXT: Jump Tables: -; CHECK4-NEXT: Jump Tables: +; CHECK2-NOT: {{^}}Jump Tables: +; CHECK4-NOT: {{^}}Jump Tables: ; CHECK8-NOT: {{^}}Jump Tables: bb1: tail call void @ext(i32 1, i32 0) br label %return @@ -58,7 +58,10 @@ i32 9, label %bb8 ] ; CHECK-LABEL: function jt8: -; CHECK-NEXT: Jump Tables: +; CHECK0-NEXT: Jump Tables: +; CHECK2-NOT: {{^}}Jump Tables: +; CHECK4-NOT: {{^}}Jump Tables: +; CHECK8-NOT: {{^}}Jump Tables: bb1: tail call void @ext(i32 1, i32 0) br label %return bb2: tail call void @ext(i32 2, i32 2) br label %return Index: llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll =================================================================== --- llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll +++ llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll @@ -58,7 +58,6 @@ ; CHECK-NEXT: nop ;; Other basic blocks have BTI, but they don't affect our decision to not create .Lpatch0 ; CHECK: .LBB{{.+}} // %sw.bb1 -; CHECK-NEXT: hint #36 ; CHECK: .section __patchable_function_entries,"awo",@progbits,f1i{{$}} ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .xword .Lpatch1 Index: llvm/test/CodeGen/AArch64/switch-unreachable-default.ll =================================================================== --- llvm/test/CodeGen/AArch64/switch-unreachable-default.ll +++ llvm/test/CodeGen/AArch64/switch-unreachable-default.ll @@ -20,9 +20,9 @@ ; CHECK-NOT: sub ; CHECK-NOT: cmp ; CHECK-NOT: b.hi -; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] -; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #2 -; CHECK: br {{x[0-9]+}} +; CHECK-NOT: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{x[0-9]+}}] +; CHECK-NOT: add {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #2 +; CHECK-NOT: br {{x[0-9]+}} default: unreachable Index: llvm/test/CodeGen/AArch64/win64-jumptable.ll =================================================================== --- llvm/test/CodeGen/AArch64/win64-jumptable.ll +++ llvm/test/CodeGen/AArch64/win64-jumptable.ll @@ -38,12 +38,12 @@ ; CHECK: .seh_proc f ; CHECK: b g ; CHECK-NEXT: .seh_endfunclet -; CHECK-NEXT: .p2align 2 -; CHECK-NEXT: .LJTI0_0: -; CHECK: .word .LBB0_2-.Ltmp0 -; CHECK: .word .LBB0_3-.Ltmp0 -; CHECK: .word .LBB0_4-.Ltmp0 -; CHECK: .word .LBB0_5-.Ltmp0 +; CHECK-NOT: .p2align 2 +; CHECK-NOT: .LJTI0_0: +; CHECK-NOT: .word .LBB0_2-.Ltmp0 +; CHECK-NOT: .word .LBB0_3-.Ltmp0 +; CHECK-NOT: .word .LBB0_4-.Ltmp0 +; CHECK-NOT: .word .LBB0_5-.Ltmp0 ; CHECK: .seh_endproc ; Check that we can emit an object file with correct unwind info.