diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -36,8 +36,10 @@
 #define GET_SUBTARGETINFO_CTOR
 #include "PPCGenSubtargetInfo.inc"
 
-static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
-cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
+static cl::opt<bool>
+    UseSubRegLiveness("ppc-track-subreg-liveness",
+                      cl::desc("Enable subregister liveness tracking for PPC"),
+                      cl::init(true), cl::Hidden);
 
 static cl::opt<bool>
     EnableMachinePipeliner("ppc-enable-pipeliner",
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
@@ -269,9 +269,9 @@
 ; SPE-NEXT:    efdcmplt cr1, r5, r7
 ; SPE-NEXT:    efdcmpeq cr5, r7, r7
 ; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
+; SPE-NEXT:    crand 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
@@ -305,9 +305,9 @@
 ; SPE-NEXT:    efdcmpgt cr1, r5, r7
 ; SPE-NEXT:    efdcmpeq cr5, r7, r7
 ; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr6+gt, 4*cr5+gt
-; SPE-NEXT:    crand 4*cr5+lt, 4*cr7+lt, 4*cr5+lt
+; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
+; SPE-NEXT:    crand 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
+; SPE-NEXT:    crand 4*cr5+lt, 4*cr5+lt, 4*cr5+gt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
@@ -379,9 +379,9 @@
 ; SPE-NEXT:    efdcmpeq cr5, r5, r5
 ; SPE-NEXT:    efdcmpeq cr6, r5, r5
 ; SPE-NEXT:    efdcmpgt cr7, r5, r6
-; SPE-NEXT:    crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
+; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
+; SPE-NEXT:    crnor 4*cr5+gt, 4*cr5+gt, 4*cr6+gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; SPE-NEXT:    cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
@@ -419,9 +419,9 @@
 ; SPE-NEXT:    efdcmpeq cr5, r5, r5
 ; SPE-NEXT:    efdcmpeq cr6, r5, r5
 ; SPE-NEXT:    efdcmplt cr7, r5, r6
-; SPE-NEXT:    crnor 4*cr1+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr1+lt
+; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
+; SPE-NEXT:    crnor 4*cr5+gt, 4*cr5+gt, 4*cr6+gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; SPE-NEXT:    cror 4*cr5+lt, 4*cr7+gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
@@ -475,9 +475,9 @@
 ; SPE-NEXT:    efdcmpeq cr1, r6, r6
 ; SPE-NEXT:    efdcmpeq cr5, r5, r5
 ; SPE-NEXT:    efdcmpeq cr6, r5, r5
-; SPE-NEXT:    crnor 4*cr7+lt, gt, 4*cr1+gt
-; SPE-NEXT:    crnor 4*cr5+lt, 4*cr5+gt, 4*cr6+gt
-; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+lt, 4*cr7+lt
+; SPE-NEXT:    crnor 4*cr5+lt, gt, 4*cr1+gt
+; SPE-NEXT:    crnor 4*cr5+gt, 4*cr5+gt, 4*cr6+gt
+; SPE-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; SPE-NEXT:    bclr 12, 4*cr5+lt, 0
 ; SPE-NEXT:  # %bb.1:
 ; SPE-NEXT:    ori r3, r4, 0
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
--- a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -136,8 +136,8 @@
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv v3, g@PCREL+32(0), 1
 ; LE-PAIRED-NEXT:    plxv v2, g@PCREL+48(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+80(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+64(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testLdStPair:
@@ -197,8 +197,8 @@
 ; LE-PAIRED:       # %bb.0: # %entry
 ; LE-PAIRED-NEXT:    plxv v3, g@PCREL+11(0), 1
 ; LE-PAIRED-NEXT:    plxv v2, g@PCREL+27(0), 1
-; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+19(0), 1
 ; LE-PAIRED-NEXT:    pstxv v2, g@PCREL+35(0), 1
+; LE-PAIRED-NEXT:    pstxv v3, g@PCREL+19(0), 1
 ; LE-PAIRED-NEXT:    blr
 ;
 ; BE-PAIRED-LABEL: testUnalignedLdStPair:
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
--- a/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-acc-spill.ll
@@ -19,15 +19,9 @@
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stdu r1, -176(r1)
-; CHECK-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-NEXT:    # kill: def $v4 killed $v4 killed $vsrp18 def $vsrp18
-; CHECK-NEXT:    # kill: def $v3 killed $v3 killed $vsrp17 def $vsrp17
-; CHECK-NEXT:    # kill: def $v2 killed $v2 killed $vsrp17 def $vsrp17
 ; CHECK-NEXT:    xxlor vs0, v2, v2
 ; CHECK-NEXT:    xxlor vs1, v3, v3
-; CHECK-NEXT:    stxvp vsp34, 128(r1) # 32-byte Folded Spill
 ; CHECK-NEXT:    ld r30, 272(r1)
-; CHECK-NEXT:    stxvp vsp36, 96(r1) # 32-byte Folded Spill
 ; CHECK-NEXT:    xxlor vs2, v4, v4
 ; CHECK-NEXT:    xxlor vs3, v5, v5
 ; CHECK-NEXT:    xxmtacc acc0
@@ -35,6 +29,8 @@
 ; CHECK-NEXT:    xxmfacc acc0
 ; CHECK-NEXT:    stxvp vsp0, 64(r1)
 ; CHECK-NEXT:    stxvp vsp2, 32(r1)
+; CHECK-NEXT:    stxvp vsp34, 128(r1) # 32-byte Folded Spill
+; CHECK-NEXT:    stxvp vsp36, 96(r1) # 32-byte Folded Spill
 ; CHECK-NEXT:    bl foo@notoc
 ; CHECK-NEXT:    lxvp vsp0, 64(r1)
 ; CHECK-NEXT:    lxvp vsp2, 32(r1)
@@ -61,23 +57,19 @@
 ; CHECK-BE-NEXT:    .cfi_def_cfa_offset 256
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
-; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    # kill: def $v5 killed $v5 killed $vsrp18 def $vsrp18
-; CHECK-BE-NEXT:    # kill: def $v4 killed $v4 killed $vsrp18 def $vsrp18
-; CHECK-BE-NEXT:    # kill: def $v3 killed $v3 killed $vsrp17 def $vsrp17
-; CHECK-BE-NEXT:    # kill: def $v2 killed $v2 killed $vsrp17 def $vsrp17
 ; CHECK-BE-NEXT:    xxlor vs0, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs1, v3, v3
-; CHECK-BE-NEXT:    stxvp vsp34, 208(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT:    std r30, 240(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    ld r30, 368(r1)
 ; CHECK-BE-NEXT:    xxlor vs2, v4, v4
 ; CHECK-BE-NEXT:    xxlor vs3, v5, v5
-; CHECK-BE-NEXT:    stxvp vsp36, 176(r1) # 32-byte Folded Spill
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    xvf16ger2pp acc0, v2, v4
 ; CHECK-BE-NEXT:    xxmfacc acc0
 ; CHECK-BE-NEXT:    stxvp vsp0, 112(r1)
 ; CHECK-BE-NEXT:    stxvp vsp2, 144(r1)
+; CHECK-BE-NEXT:    stxvp vsp34, 208(r1) # 32-byte Folded Spill
+; CHECK-BE-NEXT:    stxvp vsp36, 176(r1) # 32-byte Folded Spill
 ; CHECK-BE-NEXT:    bl foo
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    lxvp vsp0, 112(r1)
diff --git a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
--- a/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/mma-intrinsics.ll
@@ -11,11 +11,10 @@
 define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_acc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
@@ -24,11 +23,10 @@
 ;
 ; CHECK-BE-LABEL: ass_acc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
@@ -45,11 +43,10 @@
 define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmtacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
@@ -59,11 +56,10 @@
 ;
 ; CHECK-BE-LABEL: int_xxmtacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    xxmtacc acc0
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
@@ -84,11 +80,10 @@
 define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: int_xxmfacc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
-; CHECK-NEXT:    xxlor vs0, v2, v2
-; CHECK-NEXT:    xxlor vs1, v3, v3
+; CHECK-NEXT:    xxlor vs3, v2, v2
 ; CHECK-NEXT:    xxlor vs2, v2, v2
-; CHECK-NEXT:    xxlor vs3, v3, v3
+; CHECK-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-NEXT:    stxv vs0, 48(r3)
 ; CHECK-NEXT:    stxv vs1, 32(r3)
 ; CHECK-NEXT:    stxv vs2, 16(r3)
@@ -97,11 +92,10 @@
 ;
 ; CHECK-BE-LABEL: int_xxmfacc:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
-; CHECK-BE-NEXT:    xxlor vs0, v2, v2
-; CHECK-BE-NEXT:    xxlor vs1, v3, v3
+; CHECK-BE-NEXT:    xxlor vs3, v2, v2
 ; CHECK-BE-NEXT:    xxlor vs2, v2, v2
-; CHECK-BE-NEXT:    xxlor vs3, v3, v3
+; CHECK-BE-NEXT:    xxlor vs0, vs2, vs2
+; CHECK-BE-NEXT:    xxlor vs1, vs3, vs3
 ; CHECK-BE-NEXT:    stxv vs1, 16(r3)
 ; CHECK-BE-NEXT:    stxv vs0, 0(r3)
 ; CHECK-BE-NEXT:    stxv vs3, 48(r3)
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
--- a/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-creq.ll
@@ -29,161 +29,120 @@
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:    ld r4, 0(0)
 ; CHECK-NEXT:    ld r5, 56(0)
-; CHECK-NEXT:    cmpdi cr1, r3, 0
-; CHECK-NEXT:    cmpdi cr4, r4, 0
-; CHECK-NEXT:    cmpdi cr6, r5, 0
-; CHECK-NEXT:    cmpldi r3, 0
-; CHECK-NEXT:    beq cr0, .LBB0_3
+; CHECK-NEXT:    cmpdi r3, 0
+; CHECK-NEXT:    cmpdi cr1, r4, 0
+; CHECK-NEXT:    cmpdi cr5, r5, 0
+; CHECK-NEXT:    cmpldi cr6, r3, 0
+; CHECK-NEXT:    beq cr6, .LBB0_3
 ; CHECK-NEXT:  # %bb.1: # %bb10
 ; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    bc 12, 4*cr4+eq, .LBB0_4
+; CHECK-NEXT:    bc 12, 4*cr1+eq, .LBB0_4
 ; CHECK-NEXT:  .LBB0_2: # %bb14
 ; CHECK-NEXT:    lwz r5, 0(r3)
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    # implicit-def: $r3
-; CHECK-NEXT:    bc 4, 4*cr4+eq, .LBB0_2
+; CHECK-NEXT:    bc 4, 4*cr1+eq, .LBB0_2
 ; CHECK-NEXT:  .LBB0_4:
 ; CHECK-NEXT:    # implicit-def: $r5
 ; CHECK-NEXT:  .LBB0_5: # %bb16
-; CHECK-NEXT:    mfocrf r4, 64
-; CHECK-NEXT:    crnot 4*cr2+un, 4*cr1+eq
-; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr6+eq
-; CHECK-NEXT:    rotlwi r4, r4, 4
-; CHECK-NEXT:    stw r4, -4(r1)
-; CHECK-NEXT:    bc 12, 4*cr6+eq, .LBB0_7
+; CHECK-NEXT:    crnot 4*cr1+lt, eq
+; CHECK-NEXT:    crnot 4*cr5+un, 4*cr5+eq
+; CHECK-NEXT:    bc 12, 4*cr5+eq, .LBB0_7
 ; CHECK-NEXT:  # %bb.6: # %bb18
 ; CHECK-NEXT:    lwz r4, 0(r3)
 ; CHECK-NEXT:    b .LBB0_8
 ; CHECK-NEXT:  .LBB0_7:
 ; CHECK-NEXT:    # implicit-def: $r4
 ; CHECK-NEXT:  .LBB0_8: # %bb20
-; CHECK-NEXT:    cmpwi r3, -1
+; CHECK-NEXT:    cmpwi cr2, r3, -1
 ; CHECK-NEXT:    cmpwi cr3, r4, -1
 ; CHECK-NEXT:    cmpwi cr7, r3, 0
-; CHECK-NEXT:    cmpwi cr1, r4, 0
+; CHECK-NEXT:    cmpwi cr6, r4, 0
 ; CHECK-NEXT:    # implicit-def: $x3
-; CHECK-NEXT:    crand 4*cr5+eq, gt, 4*cr2+un
-; CHECK-NEXT:    crand 4*cr5+gt, 4*cr3+gt, 4*cr5+lt
-; CHECK-NEXT:    setnbc r4, 4*cr5+eq
-; CHECK-NEXT:    stw r4, -20(r1)
-; CHECK-NEXT:    bc 4, 4*cr5+eq, .LBB0_10
+; CHECK-NEXT:    crand 4*cr5+gt, 4*cr2+gt, 4*cr1+lt
+; CHECK-NEXT:    crand 4*cr5+lt, 4*cr3+gt, 4*cr5+un
+; CHECK-NEXT:    bc 4, 4*cr5+gt, .LBB0_10
 ; CHECK-NEXT:  # %bb.9: # %bb34
 ; CHECK-NEXT:    ld r3, 0(r3)
 ; CHECK-NEXT:  .LBB0_10: # %bb36
-; CHECK-NEXT:    mfocrf r4, 2
-; CHECK-NEXT:    cmpwi cr3, r5, 0
-; CHECK-NEXT:    rotlwi r4, r4, 24
-; CHECK-NEXT:    stw r4, -12(r1)
+; CHECK-NEXT:    cmpwi cr2, r5, 0
 ; CHECK-NEXT:    # implicit-def: $x4
-; CHECK-NEXT:    bc 4, 4*cr5+gt, .LBB0_12
+; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb38
 ; CHECK-NEXT:    ld r4, 0(r3)
 ; CHECK-NEXT:  .LBB0_12: # %bb40
-; CHECK-NEXT:    mcrf cr6, cr4
-; CHECK-NEXT:    crnot 4*cr4+eq, 4*cr4+eq
-; CHECK-NEXT:    crand 4*cr4+lt, 4*cr7+lt, 4*cr2+un
+; CHECK-NEXT:    crnot 4*cr6+un, 4*cr1+eq
+; CHECK-NEXT:    crand 4*cr6+gt, 4*cr7+lt, 4*cr1+lt
 ; CHECK-NEXT:    # implicit-def: $x6
-; CHECK-NEXT:    crand 4*cr4+gt, 4*cr1+lt, 4*cr5+lt
-; CHECK-NEXT:    bc 4, 4*cr4+gt, .LBB0_14
+; CHECK-NEXT:    crand 4*cr6+lt, 4*cr6+lt, 4*cr5+un
+; CHECK-NEXT:    bc 4, 4*cr6+lt, .LBB0_14
 ; CHECK-NEXT:  # %bb.13: # %bb48
 ; CHECK-NEXT:    ld r6, 0(r3)
 ; CHECK-NEXT:  .LBB0_14: # %bb50
-; CHECK-NEXT:    cmpwi r5, -1
-; CHECK-NEXT:    crand 4*cr4+un, 4*cr3+lt, 4*cr4+eq
+; CHECK-NEXT:    cmpwi cr3, r5, -1
+; CHECK-NEXT:    crand 4*cr7+lt, 4*cr2+lt, 4*cr6+un
 ; CHECK-NEXT:    # implicit-def: $r5
-; CHECK-NEXT:    bc 4, 4*cr4+lt, .LBB0_16
+; CHECK-NEXT:    bc 4, 4*cr6+gt, .LBB0_16
 ; CHECK-NEXT:  # %bb.15: # %bb52
 ; CHECK-NEXT:    lwz r5, 0(r3)
 ; CHECK-NEXT:  .LBB0_16: # %bb54
-; CHECK-NEXT:    setnbc r7, 4*cr5+gt
-; CHECK-NEXT:    stw r7, -16(r1)
-; CHECK-NEXT:    mfocrf r7, 2
-; CHECK-NEXT:    rotlwi r7, r7, 24
-; CHECK-NEXT:    stw r7, -8(r1)
+; CHECK-NEXT:    mfocrf r7, 128
+; CHECK-NEXT:    stw r7, -4(r1)
 ; CHECK-NEXT:    # implicit-def: $r7
-; CHECK-NEXT:    bc 4, 4*cr4+un, .LBB0_18
+; CHECK-NEXT:    bc 4, 4*cr7+lt, .LBB0_18
 ; CHECK-NEXT:  # %bb.17: # %bb56
 ; CHECK-NEXT:    lwz r7, 0(r3)
 ; CHECK-NEXT:  .LBB0_18: # %bb58
-; CHECK-NEXT:    crand 4*cr5+gt, 4*cr7+eq, 4*cr2+un
-; CHECK-NEXT:    mcrf cr2, cr1
-; CHECK-NEXT:    cmpwi cr1, r5, 1
-; CHECK-NEXT:    crand lt, gt, 4*cr4+eq
-; CHECK-NEXT:    # implicit-def: $x5
-; CHECK-NEXT:    setnbc r8, 4*cr5+gt
-; CHECK-NEXT:    crand 4*cr5+lt, 4*cr2+eq, 4*cr5+lt
-; CHECK-NEXT:    crand 4*cr4+eq, 4*cr3+eq, 4*cr4+eq
-; CHECK-NEXT:    crand gt, 4*cr1+lt, 4*cr4+lt
-; CHECK-NEXT:    stw r8, -24(r1)
-; CHECK-NEXT:    setnbc r8, 4*cr5+lt
-; CHECK-NEXT:    cmpwi cr5, r7, 1
-; CHECK-NEXT:    stw r8, -28(r1)
 ; CHECK-NEXT:    lwz r6, 92(r6)
-; CHECK-NEXT:    crand eq, 4*cr5+lt, 4*cr4+un
-; CHECK-NEXT:    cmpwi cr6, r6, 1
-; CHECK-NEXT:    crand un, 4*cr6+lt, 4*cr4+gt
-; CHECK-NEXT:    bc 4, gt, .LBB0_20
+; CHECK-NEXT:    crand 4*cr7+un, 4*cr3+gt, 4*cr6+un
+; CHECK-NEXT:    cmpwi cr3, r5, 1
+; CHECK-NEXT:    cmpwi cr4, r7, 1
+; CHECK-NEXT:    # implicit-def: $x5
+; CHECK-NEXT:    cmpwi r6, 1
+; CHECK-NEXT:    crand 4*cr7+gt, 4*cr7+eq, 4*cr1+lt
+; CHECK-NEXT:    crand 4*cr6+un, 4*cr2+eq, 4*cr6+un
+; CHECK-NEXT:    crand 4*cr5+un, 4*cr6+eq, 4*cr5+un
+; CHECK-NEXT:    crand 4*cr6+gt, 4*cr3+lt, 4*cr6+gt
+; CHECK-NEXT:    crand 4*cr7+lt, 4*cr4+lt, 4*cr7+lt
+; CHECK-NEXT:    crand 4*cr6+lt, lt, 4*cr6+lt
+; CHECK-NEXT:    bc 4, 4*cr6+gt, .LBB0_20
 ; CHECK-NEXT:  # %bb.19: # %bb68
 ; CHECK-NEXT:    ld r5, 0(r3)
 ; CHECK-NEXT:  .LBB0_20: # %bb70
-; CHECK-NEXT:    lwz r7, -20(r1)
-; CHECK-NEXT:    # implicit-def: $cr5lt
-; CHECK-NEXT:    mfocrf r6, 4
-; CHECK-NEXT:    xxlxor f2, f2, f2
-; CHECK-NEXT:    rlwimi r6, r7, 12, 20, 20
-; CHECK-NEXT:    mtocrf 4, r6
+; CHECK-NEXT:    crandc 4*cr5+gt, 4*cr5+gt, 4*cr7+eq
 ; CHECK-NEXT:    ld r6, 0(r3)
-; CHECK-NEXT:    crandc 4*cr5+gt, lt, 4*cr3+eq
-; CHECK-NEXT:    lwz r8, -16(r1)
-; CHECK-NEXT:    # implicit-def: $cr5eq
-; CHECK-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr7+eq
-; CHECK-NEXT:    mfocrf r7, 4
-; CHECK-NEXT:    rlwimi r7, r8, 10, 22, 22
-; CHECK-NEXT:    mtocrf 4, r7
-; CHECK-NEXT:    lwz r7, -24(r1)
-; CHECK-NEXT:    # implicit-def: $cr5un
-; CHECK-NEXT:    lwz r9, -28(r1)
-; CHECK-NEXT:    crandc 4*cr5+eq, 4*cr5+eq, 4*cr2+eq
-; CHECK-NEXT:    isel r3, r3, r5, 4*cr5+lt
-; CHECK-NEXT:    crnor 4*cr5+lt, gt, 4*cr5+lt
-; CHECK-NEXT:    crnor 4*cr5+gt, eq, 4*cr5+gt
-; CHECK-NEXT:    crnor 4*cr5+eq, un, 4*cr5+eq
-; CHECK-NEXT:    mfocrf r5, 4
-; CHECK-NEXT:    rlwimi r5, r7, 9, 23, 23
-; CHECK-NEXT:    setbc r7, 4*cr4+eq
-; CHECK-NEXT:    mtocrf 4, r5
-; CHECK-NEXT:    setbc r5, 4*cr5+un
-; CHECK-NEXT:    # implicit-def: $cr5un
-; CHECK-NEXT:    mfocrf r8, 4
-; CHECK-NEXT:    add r5, r7, r5
-; CHECK-NEXT:    rlwimi r8, r9, 9, 23, 23
-; CHECK-NEXT:    lwz r9, -4(r1)
-; CHECK-NEXT:    mtocrf 4, r8
-; CHECK-NEXT:    mtocrf 128, r9
-; CHECK-NEXT:    lwz r9, -8(r1)
-; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+lt
+; CHECK-NEXT:    crandc 4*cr7+eq, 4*cr7+un, 4*cr2+eq
+; CHECK-NEXT:    setbc r7, 4*cr6+un
 ; CHECK-NEXT:    setbc r8, 4*cr5+un
-; CHECK-NEXT:    isel r6, 0, r6, 4*cr5+gt
-; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+eq
-; CHECK-NEXT:    add r5, r8, r5
-; CHECK-NEXT:    iseleq r3, 0, r3
-; CHECK-NEXT:    mtfprd f0, r5
-; CHECK-NEXT:    mtocrf 128, r9
-; CHECK-NEXT:    lwz r9, -12(r1)
+; CHECK-NEXT:    lwz r9, -4(r1)
+; CHECK-NEXT:    xxlxor f2, f2, f2
+; CHECK-NEXT:    crandc 4*cr5+lt, 4*cr5+lt, 4*cr6+eq
 ; CHECK-NEXT:    lwz r12, 8(r1)
-; CHECK-NEXT:    xscvsxddp f0, f0
-; CHECK-NEXT:    iseleq r6, 0, r6
+; CHECK-NEXT:    isel r3, r3, r5, 4*cr5+gt
+; CHECK-NEXT:    setbc r5, 4*cr7+gt
+; CHECK-NEXT:    crnor 4*cr5+gt, 4*cr6+gt, 4*cr5+gt
+; CHECK-NEXT:    add r5, r7, r5
+; CHECK-NEXT:    crnor 4*cr6+gt, 4*cr7+lt, 4*cr7+eq
+; CHECK-NEXT:    crnor 4*cr5+lt, 4*cr6+lt, 4*cr5+lt
+; CHECK-NEXT:    add r5, r8, r5
+; CHECK-NEXT:    isel r3, 0, r3, 4*cr5+gt
+; CHECK-NEXT:    isel r6, 0, r6, 4*cr6+gt
 ; CHECK-NEXT:    mtocrf 128, r9
+; CHECK-NEXT:    mtfprd f0, r5
+; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+lt
+; CHECK-NEXT:    iseleq r3, 0, r3
+; CHECK-NEXT:    isel r6, 0, r6, 4*cr1+eq
+; CHECK-NEXT:    isel r4, 0, r4, 4*cr5+eq
 ; CHECK-NEXT:    add r3, r6, r3
 ; CHECK-NEXT:    mtocrf 32, r12
 ; CHECK-NEXT:    mtocrf 16, r12
+; CHECK-NEXT:    xscvsxddp f0, f0
 ; CHECK-NEXT:    mtocrf 8, r12
-; CHECK-NEXT:    iseleq r4, 0, r4
 ; CHECK-NEXT:    add r3, r4, r3
-; CHECK-NEXT:    xsmuldp f0, f0, f2
 ; CHECK-NEXT:    mtfprd f1, r3
 ; CHECK-NEXT:    xscvsxddp f1, f1
+; CHECK-NEXT:    xsmuldp f0, f0, f2
 ; CHECK-NEXT:    xsadddp f1, f0, f1
 ; CHECK-NEXT:    blr
 bb:
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll
@@ -17,8 +17,7 @@
 
 define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_GT:
-; CHECK:         .localentry P10_Spill_CR_GT, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    std r0, 16(r1)
@@ -187,7 +186,7 @@
 ; CHECK-NEXT:    mtocrf 8, r12
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_32: # %bb29
-; CHECK-NEXT:    mcrf cr0, cr4
+; CHECK-NEXT:    crmove eq, 4*cr4+eq
 ; CHECK-NEXT:    cmpwi cr3, r5, 366
 ; CHECK-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-NEXT:    li r29, 0
@@ -380,7 +379,7 @@
 ; CHECK-BE-NEXT:    mtocrf 8, r12
 ; CHECK-BE-NEXT:    blr
 ; CHECK-BE-NEXT:  .LBB0_32: # %bb29
-; CHECK-BE-NEXT:    mcrf cr0, cr4
+; CHECK-BE-NEXT:    crmove eq, 4*cr4+eq
 ; CHECK-BE-NEXT:    cmpwi cr3, r5, 366
 ; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-BE-NEXT:    li r29, 0
diff --git a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
--- a/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll
@@ -25,31 +25,28 @@
 
 define dso_local void @P10_Spill_CR_LT() local_unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_LT:
-; CHECK:         .localentry P10_Spill_CR_LT, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stw r12, 8(r1)
-; CHECK-NEXT:    stdu r1, -80(r1)
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    .cfi_offset cr2, 8
 ; CHECK-NEXT:    .cfi_offset cr3, 8
 ; CHECK-NEXT:    .cfi_offset cr4, 8
-; CHECK-NEXT:    std r30, 64(r1) # 8-byte Folded Spill
+; CHECK-NEXT:    std r30, 32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    bl call_2@notoc
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
 ; CHECK-NEXT:  # %bb.1: # %bb
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-NEXT:  # %bb.2: # %bb4
 ; CHECK-NEXT:    cmpdi cr3, r3, 0
-; CHECK-NEXT:    # implicit-def: $r30
-; CHECK-NEXT:    crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-NEXT:    setnbc r3, 4*cr5+lt
-; CHECK-NEXT:    stw r3, 60(r1)
 ; CHECK-NEXT:    lwz r3, 0(r3)
+; CHECK-NEXT:    # implicit-def: $r30
+; CHECK-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
 ; CHECK-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_3: # %bb12
@@ -77,12 +74,7 @@
 ; CHECK-NEXT:  .LBB0_8: # %bb22
 ; CHECK-NEXT:  .LBB0_9: # %bb35
 ; CHECK-NEXT:  .LBB0_10: # %bb27
-; CHECK-NEXT:    lwz r4, 60(r1)
-; CHECK-NEXT:    # implicit-def: $cr5lt
-; CHECK-NEXT:    mfocrf r3, 4
-; CHECK-NEXT:    rlwimi r3, r4, 12, 20, 20
-; CHECK-NEXT:    mtocrf 4, r3
-; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
 ; CHECK-NEXT:  # %bb.11: # %bb28
 ; CHECK-NEXT:  .LBB0_12: # %bb29
 ; CHECK-NEXT:  .LBB0_13: # %bb3
@@ -94,16 +86,16 @@
 ; CHECK-BE-NEXT:    mfcr r12
 ; CHECK-BE-NEXT:    std r0, 16(r1)
 ; CHECK-BE-NEXT:    stw r12, 8(r1)
-; CHECK-BE-NEXT:    stdu r1, -160(r1)
-; CHECK-BE-NEXT:    .cfi_def_cfa_offset 160
+; CHECK-BE-NEXT:    stdu r1, -144(r1)
+; CHECK-BE-NEXT:    .cfi_def_cfa_offset 144
 ; CHECK-BE-NEXT:    .cfi_offset lr, 16
 ; CHECK-BE-NEXT:    .cfi_offset r29, -24
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
-; CHECK-BE-NEXT:    std r29, 136(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    std r30, 144(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
+; CHECK-BE-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    bl call_2
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_13
@@ -111,12 +103,10 @@
 ; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-BE-NEXT:  # %bb.2: # %bb4
 ; CHECK-BE-NEXT:    cmpdi cr3, r3, 0
+; CHECK-BE-NEXT:    lwz r3, 0(r3)
 ; CHECK-BE-NEXT:    addis r30, r2, call_1@toc@ha
 ; CHECK-BE-NEXT:    # implicit-def: $r29
-; CHECK-BE-NEXT:    crnot 4*cr5+lt, 4*cr3+eq
-; CHECK-BE-NEXT:    setnbc r3, 4*cr5+lt
-; CHECK-BE-NEXT:    stw r3, 132(r1)
-; CHECK-BE-NEXT:    lwz r3, 0(r3)
+; CHECK-BE-NEXT:    crnot 4*cr3+lt, 4*cr3+eq
 ; CHECK-BE-NEXT:    cmpwi cr4, r3, 0
 ; CHECK-BE-NEXT:    .p2align 4
 ; CHECK-BE-NEXT:  .LBB0_3: # %bb12
@@ -146,12 +136,7 @@
 ; CHECK-BE-NEXT:  .LBB0_8: # %bb22
 ; CHECK-BE-NEXT:  .LBB0_9: # %bb35
 ; CHECK-BE-NEXT:  .LBB0_10: # %bb27
-; CHECK-BE-NEXT:    lwz r4, 132(r1)
-; CHECK-BE-NEXT:    # implicit-def: $cr5lt
-; CHECK-BE-NEXT:    mfocrf r3, 4
-; CHECK-BE-NEXT:    rlwimi r3, r4, 12, 20, 20
-; CHECK-BE-NEXT:    mtocrf 4, r3
-; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_12
+; CHECK-BE-NEXT:    bc 4, 4*cr3+lt, .LBB0_12
 ; CHECK-BE-NEXT:  # %bb.11: # %bb28
 ; CHECK-BE-NEXT:  .LBB0_12: # %bb29
 ; CHECK-BE-NEXT:  .LBB0_13: # %bb3
diff --git a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
--- a/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
+++ b/llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll
@@ -20,28 +20,24 @@
 define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
 ; CHECK-LABEL: ass_pair:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vmr v3, v2
+; CHECK-NEXT:    stxv v2, 0(r3)
 ; CHECK-NEXT:    stxv v2, 16(r3)
-; CHECK-NEXT:    stxv v3, 0(r3)
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NOMMA-LABEL: ass_pair:
 ; CHECK-NOMMA:       # %bb.0: # %entry
-; CHECK-NOMMA-NEXT:    vmr v3, v2
+; CHECK-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-NOMMA-NEXT:    stxv v2, 16(r3)
-; CHECK-NOMMA-NEXT:    stxv v3, 0(r3)
 ; CHECK-NOMMA-NEXT:    blr
 ;
 ; CHECK-BE-LABEL: ass_pair:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    vmr v3, v2
 ; CHECK-BE-NEXT:    stxv v2, 16(r3)
 ; CHECK-BE-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NEXT:    blr
 ;
 ; CHECK-BE-NOMMA-LABEL: ass_pair:
 ; CHECK-BE-NOMMA:       # %bb.0: # %entry
-; CHECK-BE-NOMMA-NEXT:    vmr v3, v2
 ; CHECK-BE-NOMMA-NEXT:    stxv v2, 16(r3)
 ; CHECK-BE-NOMMA-NEXT:    stxv v2, 0(r3)
 ; CHECK-BE-NOMMA-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll b/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-fpclass.ll
@@ -171,17 +171,17 @@
 ; CHECK-NEXT:    lwz 6, 16(1)
 ; CHECK-NEXT:    clrlwi. 5, 5, 1
 ; CHECK-NEXT:    cmplwi 5, 5, 0
-; CHECK-NEXT:    crandc 24, 1, 22
+; CHECK-NEXT:    crandc 20, 1, 22
 ; CHECK-NEXT:    cmpwi 3, 0
-; CHECK-NEXT:    crandc 20, 22, 2
+; CHECK-NEXT:    crandc 21, 22, 2
 ; CHECK-NEXT:    cmpwi 6, 0
-; CHECK-NEXT:    cmplwi 7, 4, 0
+; CHECK-NEXT:    cmplwi 6, 4, 0
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    crandc 21, 5, 30
-; CHECK-NEXT:    crandc 22, 30, 2
+; CHECK-NEXT:    crandc 22, 5, 26
+; CHECK-NEXT:    crandc 23, 26, 2
 ; CHECK-NEXT:    cmplwi 3, 0
-; CHECK-NEXT:    cror 20, 20, 24
-; CHECK-NEXT:    cror 21, 22, 21
+; CHECK-NEXT:    cror 20, 21, 20
+; CHECK-NEXT:    cror 21, 23, 22
 ; CHECK-NEXT:    crandc 20, 20, 2
 ; CHECK-NEXT:    crand 21, 2, 21
 ; CHECK-NEXT:    crnor 20, 21, 20
@@ -263,23 +263,23 @@
 ; CHECK-NEXT:    stfd 1, 16(1)
 ; CHECK-NEXT:    cmplwi 5, 9, 0
 ; CHECK-NEXT:    lwz 5, 20(1)
-; CHECK-NEXT:    crandc 24, 1, 22
+; CHECK-NEXT:    crandc 20, 1, 22
 ; CHECK-NEXT:    stfd 2, 24(1)
 ; CHECK-NEXT:    cmpwi 8, 0
 ; CHECK-NEXT:    lwz 4, 16(1)
-; CHECK-NEXT:    cmplw 7, 10, 3
+; CHECK-NEXT:    cmplw 6, 10, 3
 ; CHECK-NEXT:    lwz 7, 28(1)
 ; CHECK-NEXT:    xoris 10, 10, 32752
-; CHECK-NEXT:    crandc 20, 22, 2
+; CHECK-NEXT:    crandc 21, 22, 2
 ; CHECK-NEXT:    cmplwi 10, 0
 ; CHECK-NEXT:    lwz 6, 24(1)
-; CHECK-NEXT:    crandc 21, 29, 2
-; CHECK-NEXT:    cmplw 7, 5, 3
+; CHECK-NEXT:    crandc 22, 25, 2
+; CHECK-NEXT:    cmplw 6, 5, 3
 ; CHECK-NEXT:    xoris 3, 5, 32752
-; CHECK-NEXT:    crandc 22, 2, 6
+; CHECK-NEXT:    crandc 23, 2, 6
 ; CHECK-NEXT:    cmplwi 3, 0
 ; CHECK-NEXT:    cmpwi 1, 4, 0
-; CHECK-NEXT:    crandc 23, 29, 2
+; CHECK-NEXT:    crandc 24, 25, 2
 ; CHECK-NEXT:    crandc 25, 2, 6
 ; CHECK-NEXT:    clrlwi. 3, 7, 1
 ; CHECK-NEXT:    cmplwi 1, 3, 0
@@ -289,10 +289,10 @@
 ; CHECK-NEXT:    crandc 27, 6, 2
 ; CHECK-NEXT:    cmplwi 4, 0
 ; CHECK-NEXT:    or 3, 6, 3
-; CHECK-NEXT:    cror 20, 20, 24
-; CHECK-NEXT:    cror 21, 22, 21
+; CHECK-NEXT:    cror 20, 21, 20
+; CHECK-NEXT:    cror 21, 23, 22
 ; CHECK-NEXT:    cmplwi 1, 3, 0
-; CHECK-NEXT:    cror 22, 25, 23
+; CHECK-NEXT:    cror 22, 25, 24
 ; CHECK-NEXT:    crandc 20, 20, 2
 ; CHECK-NEXT:    crand 21, 2, 21
 ; CHECK-NEXT:    cror 23, 27, 26
@@ -418,23 +418,23 @@
 ; CHECK-NEXT:    stfd 1, 16(1)
 ; CHECK-NEXT:    cmplwi 5, 9, 0
 ; CHECK-NEXT:    lwz 5, 20(1)
-; CHECK-NEXT:    crandc 24, 1, 22
+; CHECK-NEXT:    crandc 20, 1, 22
 ; CHECK-NEXT:    stfd 2, 24(1)
 ; CHECK-NEXT:    cmpwi 8, 0
 ; CHECK-NEXT:    lwz 4, 16(1)
-; CHECK-NEXT:    cmplw 7, 10, 3
+; CHECK-NEXT:    cmplw 6, 10, 3
 ; CHECK-NEXT:    lwz 7, 28(1)
 ; CHECK-NEXT:    xoris 10, 10, 32752
-; CHECK-NEXT:    crandc 20, 22, 2
+; CHECK-NEXT:    crandc 21, 22, 2
 ; CHECK-NEXT:    cmplwi 10, 0
 ; CHECK-NEXT:    lwz 6, 24(1)
-; CHECK-NEXT:    crandc 21, 29, 2
-; CHECK-NEXT:    cmplw 7, 5, 3
+; CHECK-NEXT:    crandc 22, 25, 2
+; CHECK-NEXT:    cmplw 6, 5, 3
 ; CHECK-NEXT:    xoris 3, 5, 32752
-; CHECK-NEXT:    crandc 22, 2, 6
+; CHECK-NEXT:    crandc 23, 2, 6
 ; CHECK-NEXT:    cmplwi 3, 0
 ; CHECK-NEXT:    cmpwi 1, 4, 0
-; CHECK-NEXT:    crandc 23, 29, 2
+; CHECK-NEXT:    crandc 24, 25, 2
 ; CHECK-NEXT:    crandc 25, 2, 6
 ; CHECK-NEXT:    clrlwi. 3, 7, 1
 ; CHECK-NEXT:    cmplwi 1, 3, 0
@@ -444,10 +444,10 @@
 ; CHECK-NEXT:    crandc 27, 6, 2
 ; CHECK-NEXT:    cmplwi 4, 0
 ; CHECK-NEXT:    or 3, 6, 3
-; CHECK-NEXT:    cror 20, 20, 24
-; CHECK-NEXT:    cror 21, 22, 21
+; CHECK-NEXT:    cror 20, 21, 20
+; CHECK-NEXT:    cror 21, 23, 22
 ; CHECK-NEXT:    cmplwi 1, 3, 0
-; CHECK-NEXT:    cror 22, 25, 23
+; CHECK-NEXT:    cror 22, 25, 24
 ; CHECK-NEXT:    crandc 20, 20, 2
 ; CHECK-NEXT:    crand 21, 2, 21
 ; CHECK-NEXT:    cror 23, 27, 26
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc-bugfix.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
 ; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
-; RUN:    | FileCheck %s
+; RUN:     -ppc-track-subreg-liveness=false | FileCheck %s
 
 define void @copy_novsrp() local_unnamed_addr {
 ; CHECK-LABEL: copy_novsrp:
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
--- a/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-acc-regalloc.ll
@@ -29,51 +29,42 @@
 ; CHECK-NEXT:  .LBB0_1: # %bb9
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    addi r6, r6, 2
-; CHECK-NEXT:    lxv vs1, -64(r5)
-; CHECK-NEXT:    lxv vs2, -16(r5)
 ; CHECK-NEXT:    lxv vs0, 16(0)
-; CHECK-NEXT:    vmr v9, v0
-; CHECK-NEXT:    xxlxor v10, v10, v10
-; CHECK-NEXT:    xxlxor v7, v7, v7
+; CHECK-NEXT:    xxlxor vs7, vs7, vs7
+; CHECK-NEXT:    lxv vs1, -64(r5)
+; CHECK-NEXT:    lxv vs4, -16(r5)
+; CHECK-NEXT:    xxlxor vs12, vs12, vs12
+; CHECK-NEXT:    xxlor vs3, v0, v0
+; CHECK-NEXT:    xxlxor vs2, vs2, vs2
 ; CHECK-NEXT:    mulld r6, r6, r3
-; CHECK-NEXT:    xvmaddadp v9, vs1, v2
-; CHECK-NEXT:    xxlxor v8, v8, v8
-; CHECK-NEXT:    xvmaddadp v10, vs2, v10
-; CHECK-NEXT:    xvmaddadp v7, vs0, v5
-; CHECK-NEXT:    xvmuldp v6, vs0, v2
-; CHECK-NEXT:    xvmaddadp v7, v2, v2
-; CHECK-NEXT:    xvmaddadp v6, v2, v2
-; CHECK-NEXT:    lxvdsx v14, r6, r4
-; CHECK-NEXT:    xvmaddadp v8, vs1, v8
-; CHECK-NEXT:    li r6, 0
-; CHECK-NEXT:    xvmuldp v11, vs2, v14
-; CHECK-NEXT:    xvmuldp v3, vs1, v14
-; CHECK-NEXT:    xvmuldp vs5, v14, v2
-; CHECK-NEXT:    xvmuldp v13, v4, v14
-; CHECK-NEXT:    vmr v12, v2
-; CHECK-NEXT:    xxlor vs14, v10, v10
+; CHECK-NEXT:    xxlor vs10, v2, v2
+; CHECK-NEXT:    xxlor vs8, vs10, vs10
+; CHECK-NEXT:    xxlor vs10, v1, v1
+; CHECK-NEXT:    xvmaddadp vs7, vs0, v5
+; CHECK-NEXT:    xvmuldp vs6, vs0, v2
+; CHECK-NEXT:    xvmaddadp vs12, vs4, vs12
+; CHECK-NEXT:    xvmaddadp vs3, vs1, v2
+; CHECK-NEXT:    xvmaddadp vs2, vs1, vs2
 ; CHECK-NEXT:    xxlor vs0, v2, v2
+; CHECK-NEXT:    lxvdsx v6, r6, r4
+; CHECK-NEXT:    li r6, 0
+; CHECK-NEXT:    xvmaddadp vs7, v2, v2
+; CHECK-NEXT:    xvmaddadp vs6, v2, v2
+; CHECK-NEXT:    xxlor vs14, vs12, vs12
+; CHECK-NEXT:    xxlor vs12, v2, v2
+; CHECK-NEXT:    xvmuldp v3, vs1, v6
+; CHECK-NEXT:    xvmuldp vs11, v4, v6
+; CHECK-NEXT:    xvmuldp vs13, vs4, v6
+; CHECK-NEXT:    xvmuldp vs5, v6, v2
 ; CHECK-NEXT:    xxlor vs4, v2, v2
-; CHECK-NEXT:    # kill: def $vsrp2 killed $vsrp2 def $uacc1
-; CHECK-NEXT:    xxlor vs6, v6, v6
-; CHECK-NEXT:    xxlor vs7, v7, v7
-; CHECK-NEXT:    xxlor vs8, v12, v12
-; CHECK-NEXT:    xxlor vs9, v13, v13
-; CHECK-NEXT:    vmr v12, v1
-; CHECK-NEXT:    xxlor vs15, v11, v11
-; CHECK-NEXT:    vmr v10, v2
 ; CHECK-NEXT:    xxlor vs1, v3, v3
-; CHECK-NEXT:    xxlor vs2, v8, v8
-; CHECK-NEXT:    xxlor vs3, v9, v9
-; CHECK-NEXT:    xxlor vs10, v12, v12
-; CHECK-NEXT:    xxlor vs11, v13, v13
+; CHECK-NEXT:    xxlor vs9, vs11, vs11
+; CHECK-NEXT:    xxlor vs15, vs13, vs13
 ; CHECK-NEXT:    xxmtacc acc1
-; CHECK-NEXT:    xxlor vs12, v10, v10
-; CHECK-NEXT:    xxlor vs13, v11, v11
 ; CHECK-NEXT:    xxmtacc acc0
 ; CHECK-NEXT:    xxmtacc acc2
-; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
 ; CHECK-NEXT:    xxmtacc acc3
+; CHECK-NEXT:    xvf64gerpp acc0, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc1, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc2, vsp34, vs0
 ; CHECK-NEXT:    xvf64gerpp acc3, vsp34, vs0
diff --git a/llvm/test/CodeGen/PowerPC/pr45709.ll b/llvm/test/CodeGen/PowerPC/pr45709.ll
--- a/llvm/test/CodeGen/PowerPC/pr45709.ll
+++ b/llvm/test/CodeGen/PowerPC/pr45709.ll
@@ -40,6 +40,7 @@
 ; CHECK-NEXT:    lvx v2, 0, r3
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    stvx v2, 0, r3
+; CHECK-NEXT:    lfs f0, -16(r1)
 ; CHECK-NEXT:  .LBB0_6:
 ; CHECK-NEXT:    blr
   br i1 undef, label %7, label %1
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1422,8 +1422,8 @@
 ; SPE-NEXT:    efdcmpeq 0, 4, 4
 ; SPE-NEXT:    efdcmpeq 1, 3, 3
 ; SPE-NEXT:    efdcmplt 5, 3, 4
-; SPE-NEXT:    crand 24, 5, 1
-; SPE-NEXT:    crorc 20, 21, 24
+; SPE-NEXT:    crand 20, 5, 1
+; SPE-NEXT:    crorc 20, 21, 20
 ; SPE-NEXT:    bc 12, 20, .LBB47_2
 ; SPE-NEXT:  # %bb.1: # %entry
 ; SPE-NEXT:    ori 3, 7, 0
diff --git a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
--- a/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
+++ b/llvm/test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
@@ -59,35 +59,32 @@
 ; PPC32-NEXT:    stw 12, 24(1)
 ; PPC32-NEXT:    bl __multi3
 ; PPC32-NEXT:    mulhwu. 9, 26, 27
-; PPC32-NEXT:    mfcr 9 # cr0
+; PPC32-NEXT:    mcrf 1, 0
 ; PPC32-NEXT:    cmpwi 2, 26, 0
-; PPC32-NEXT:    stw 9, 20(1)
 ; PPC32-NEXT:    cmpwi 3, 23, 0
-; PPC32-NEXT:    crnor 12, 14, 10
 ; PPC32-NEXT:    cmpwi 4, 24, 0
 ; PPC32-NEXT:    mulhwu. 9, 23, 29
 ; PPC32-NEXT:    mcrf 5, 0
-; PPC32-NEXT:    cmpwi 1, 25, 0
-; PPC32-NEXT:    crnor 4, 6, 18
+; PPC32-NEXT:    crnor 20, 14, 10
+; PPC32-NEXT:    cmpwi 3, 25, 0
+; PPC32-NEXT:    crnor 21, 14, 18
+; PPC32-NEXT:    crorc 20, 20, 6
 ; PPC32-NEXT:    mulhwu. 9, 24, 30
 ; PPC32-NEXT:    mcrf 6, 0
+; PPC32-NEXT:    crorc 20, 20, 22
+; PPC32-NEXT:    crorc 21, 21, 26
+; PPC32-NEXT:    mullw 9, 23, 29
+; PPC32-NEXT:    mullw 10, 26, 27
+; PPC32-NEXT:    add 9, 10, 9
 ; PPC32-NEXT:    mulhwu. 0, 25, 28
 ; PPC32-NEXT:    mcrf 7, 0
 ; PPC32-NEXT:    or. 0, 28, 24
 ; PPC32-NEXT:    mcrf 2, 0
 ; PPC32-NEXT:    or. 0, 29, 26
-; PPC32-NEXT:    crnor 5, 2, 10
-; PPC32-NEXT:    mullw 10, 26, 27
-; PPC32-NEXT:    lwz 26, 20(1)
-; PPC32-NEXT:    mullw 9, 23, 29
-; PPC32-NEXT:    add 9, 10, 9
-; PPC32-NEXT:    mtcrf 128, 26 # cr0
-; PPC32-NEXT:    crorc 6, 12, 2
-; PPC32-NEXT:    crorc 20, 6, 22
+; PPC32-NEXT:    crnor 23, 2, 10
 ; PPC32-NEXT:    mulhwu 7, 29, 27
 ; PPC32-NEXT:    add 9, 7, 9
 ; PPC32-NEXT:    cmplw 9, 7
-; PPC32-NEXT:    crorc 21, 4, 26
 ; PPC32-NEXT:    cror 20, 20, 0
 ; PPC32-NEXT:    crorc 21, 21, 30
 ; PPC32-NEXT:    mullw 11, 25, 28
@@ -99,7 +96,7 @@
 ; PPC32-NEXT:    add 10, 8, 10
 ; PPC32-NEXT:    cmplw 10, 8
 ; PPC32-NEXT:    cror 21, 21, 0
-; PPC32-NEXT:    cror 21, 5, 21
+; PPC32-NEXT:    cror 21, 23, 21
 ; PPC32-NEXT:    cror 20, 21, 20
 ; PPC32-NEXT:    mullw 0, 29, 27
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2
@@ -111,11 +108,11 @@
 ; PPC32-NEXT:    adde 11, 10, 9
 ; PPC32-NEXT:    addc 9, 4, 7
 ; PPC32-NEXT:    adde 8, 3, 11
-; PPC32-NEXT:    cmplw 6, 9, 4
+; PPC32-NEXT:    cmplw 1, 9, 4
 ; PPC32-NEXT:    cmplw 8, 3
-; PPC32-NEXT:    crand 22, 2, 24
-; PPC32-NEXT:    crandc 23, 0, 2
-; PPC32-NEXT:    cror 22, 22, 23
+; PPC32-NEXT:    crand 22, 2, 4
+; PPC32-NEXT:    crandc 24, 0, 2
+; PPC32-NEXT:    cror 22, 22, 24
 ; PPC32-NEXT:    crnor 20, 20, 22
 ; PPC32-NEXT:    li 3, 1
 ; PPC32-NEXT:    bc 12, 20, .LBB0_2