diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -45,6 +45,13 @@ // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64" +// mcpu with mabi option +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s +// MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51" +// MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a" +// MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit" +// MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64" + // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s // MCPU-SIFIVE-U54: "-nostdsysteminc" "-target-cpu" "sifive-u54" diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def --- a/llvm/include/llvm/Support/RISCVTargetParser.def +++ b/llvm/include/llvm/Support/RISCVTargetParser.def @@ -20,6 +20,7 @@ PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""}) PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""}) PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"}) +PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"}) PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"}) PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"}) PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -254,6 +254,11 @@ FeatureStdExtA, FeatureStdExtC]>; +def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtC]>; + def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit, FeatureStdExtM, FeatureStdExtA,