diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -509,6 +509,7 @@
     setLibcallName(RTLIB::SHL_I128, nullptr);
     setLibcallName(RTLIB::SRL_I128, nullptr);
     setLibcallName(RTLIB::SRA_I128, nullptr);
+    setLibcallName(RTLIB::MULO_I64, nullptr);
   }
 
   setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
diff --git a/llvm/test/CodeGen/Mips/overflow-intrinsic-optimizations.ll b/llvm/test/CodeGen/Mips/overflow-intrinsic-optimizations.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/overflow-intrinsic-optimizations.ll
@@ -0,0 +1,28 @@
+; RUN: llc %s -mtriple=mipsel -o - | FileCheck %s
+
+define void @no__mulodi4(i32 %a, i64 %b, i32* %c) {
+; CHECK-LABEL: no__mulodi4
+; CHECK-NOT: jal __mulodi4
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i32*, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i64 %b, i64* %b.addr, align 8
+  store i32* %c, i32** %c.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i64, i64* %b.addr, align 8
+  %2 = load i32*, i32** %c.addr, align 4
+  %3 = sext i32 %0 to i64
+  %4 = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %3, i64 %1)
+  %5 = extractvalue { i64, i1 } %4, 1
+  %6 = extractvalue { i64, i1 } %4, 0
+  %7 = trunc i64 %6 to i32
+  %8 = sext i32 %7 to i64
+  %9 = icmp ne i64 %6, %8
+  %10 = or i1 %5, %9
+  store i32 %7, i32* %2, align 4
+  ret void
+}
+
+declare { i64, i1 } @llvm.smul.with.overflow.i64(i64, i64)