Index: lldb/source/Plugins/ABI/X86/ABIX86.h =================================================================== --- lldb/source/Plugins/ABI/X86/ABIX86.h +++ lldb/source/Plugins/ABI/X86/ABIX86.h @@ -17,6 +17,10 @@ static void Initialize(); static void Terminate(); +protected: + void AugmentRegisterInfo( + std::vector ®s) override; + private: using lldb_private::MCBasedABI::MCBasedABI; }; Index: lldb/source/Plugins/ABI/X86/ABIX86.cpp =================================================================== --- lldb/source/Plugins/ABI/X86/ABIX86.cpp +++ lldb/source/Plugins/ABI/X86/ABIX86.cpp @@ -6,12 +6,19 @@ // //===----------------------------------------------------------------------===// -#include "ABIX86.h" #include "ABIMacOSX_i386.h" #include "ABISysV_i386.h" #include "ABISysV_x86_64.h" #include "ABIWindows_x86_64.h" +#include "ABIX86.h" #include "lldb/Core/PluginManager.h" +#include "lldb/Target/Process.h" + +#include +#include + +using namespace lldb; +using namespace lldb_private; LLDB_PLUGIN_DEFINE(ABIX86) @@ -28,3 +35,166 @@ ABISysV_x86_64::Terminate(); ABIWindows_x86_64::Terminate(); } + +static void addPartialRegister(std::vector ®s, + uint32_t full_reg_index, uint32_t full_reg_size, + const std::string &partial_reg_name, + uint32_t partial_reg_size, uint32_t offset = 0, + lldb::Encoding encoding = eEncodingInvalid, + lldb::Format format = eFormatInvalid) { + if (full_reg_index == LLDB_INVALID_REGNUM) + return; + DynamicRegisterInfo::Register &full_reg = regs[full_reg_index]; + if (full_reg.byte_size != full_reg_size) + return; + + lldb_private::DynamicRegisterInfo::Register partial_reg{ + lldb_private::ConstString(partial_reg_name), + lldb_private::ConstString(), + lldb_private::ConstString("supplementary registers"), + partial_reg_size, + LLDB_INVALID_INDEX32, + encoding != eEncodingInvalid ? encoding : full_reg.encoding, + format != eFormatInvalid ? format : full_reg.format, + LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, + LLDB_INVALID_REGNUM, + {full_reg_index}, + {}, + offset}; + + addSupplementaryRegister(regs, partial_reg); +} + +struct GPRReg { + std::string name32; + std::string name16; + std::string name8h; + std::string name8; + std::array names; + uint32_t base_index = LLDB_INVALID_REGNUM; +}; + +enum { + GPR32 = 0, + GPR16, + GPR8h, + GPR8, +}; + +static void +addGPRs(std::vector ®s, + llvm::ArrayRef base_reg_indices, + std::unordered_map> reg_names, + uint32_t base_size, int name_index, uint32_t subreg_size, + uint32_t subreg_offset = 0) { + for (uint32_t base_index : base_reg_indices) { + if (base_index == LLDB_INVALID_REGNUM) + break; + assert(base_index < regs.size()); + DynamicRegisterInfo::Register &full_reg = regs[base_index]; + const std::string &subreg_name = + reg_names[full_reg.name.AsCString() + 1][name_index]; + if (subreg_name.empty()) + continue; + addPartialRegister(regs, base_index, base_size, subreg_name, subreg_size, + subreg_offset); + } +} + +struct STReg { + std::string name_mm; + uint32_t base_index = LLDB_INVALID_REGNUM; +}; + +void ABIX86::AugmentRegisterInfo( + std::vector ®s) { + MCBasedABI::AugmentRegisterInfo(regs); + + ProcessSP process_sp = GetProcessSP(); + if (!process_sp) + return; + + ArchSpec arch = process_sp->GetTarget().GetArchitecture(); + bool is64bit = arch.GetAddressByteSize() == 8; + + typedef std::pair> GPRPair; + std::unordered_map> gpr_regs{{ + GPRPair("ax", {"eax", "ax", "ah", "al"}), + GPRPair("bx", {"ebx", "bx", "bh", "bl"}), + GPRPair("cx", {"ecx", "cx", "ch", "cl"}), + GPRPair("dx", {"edx", "dx", "dh", "dl"}), + GPRPair("si", {"esi", "si", "", "sil"}), + GPRPair("di", {"edi", "di", "", "dil"}), + GPRPair("bp", {"ebp", "bp", "", "bpl"}), + GPRPair("sp", {"esp", "sp", "", "spl"}), + }}; + if (is64bit) { + for (int i = 8; i < 16; i++) + gpr_regs.insert( + GPRPair(llvm::utostr(i), { + llvm::formatv("r{0}d", i).str(), + llvm::formatv("r{0}w", i).str(), + "", + llvm::formatv("r{0}l", i).str(), + })); + } + + char gpr_base_reg_prefix = is64bit ? 'r' : 'e'; + uint32_t gpr_base_size = is64bit ? 8 : 4; + // regs from gpr_basenames, in list order + std::vector gpr_base_reg_indices; + // st0..st7, sorted + std::array st_reg_indices; + // map used for fast register lookups + std::unordered_set subreg_name_set; + + // put all subreg names into the lookup set + for (const auto &kv : gpr_regs) + subreg_name_set.insert(kv.second.begin(), kv.second.end()); + + // find base registers and store their indices + // (note that with incorrect input we could get less than 8 regs) + for (const auto &x : llvm::enumerate(regs)) { + const char *reg_name = x.value().name.AsCString(); + // handle regs from gpr_regs + if (reg_name[0] == gpr_base_reg_prefix && + gpr_regs.find(reg_name + 1) != gpr_regs.end()) + gpr_base_reg_indices.push_back(x.index()); + + // st0..st7 regs + if (llvm::StringRef(reg_name).startswith("st")) { + unsigned int suffix; + if (llvm::to_integer(reg_name + 2, suffix, 10) && suffix < 8) { + STReg ®_rec = st_reg_indices[suffix]; + reg_rec.base_index = x.index(); + + std::string new_regname{"mm"}; + new_regname += llvm::utostr(suffix); + reg_rec.name_mm = new_regname; + subreg_name_set.insert(new_regname); + + continue; + } + } + } + + // abort if we have at least one existing subregister + for (const DynamicRegisterInfo::Register &x : regs) { + const char *reg_name = x.name.AsCString(); + if (llvm::is_contained(subreg_name_set, reg_name)) + return; + } + + if (is64bit) + addGPRs(regs, gpr_base_reg_indices, gpr_regs, gpr_base_size, GPR32, 4); + addGPRs(regs, gpr_base_reg_indices, gpr_regs, gpr_base_size, GPR16, 2); + addGPRs(regs, gpr_base_reg_indices, gpr_regs, gpr_base_size, GPR8h, 1, 1); + addGPRs(regs, gpr_base_reg_indices, gpr_regs, gpr_base_size, GPR8, 1); + + // add mm registers + for (const STReg ® : st_reg_indices) + addPartialRegister(regs, reg.base_index, 10, reg.name_mm, 8, 0, + eEncodingUint, eFormatHex); +} Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py =================================================================== --- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py +++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py @@ -163,6 +163,67 @@ ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) + # test pseudo-registers + self.match("register read ecx", + ["ecx = 0x04030201"]) + self.match("register read cx", + ["cx = 0x0201"]) + self.match("register read ch", + ["ch = 0x02"]) + self.match("register read cl", + ["cl = 0x01"]) + self.match("register read r8d", + ["r8d = 0x64636261"]) + self.match("register read r8w", + ["r8w = 0x6261"]) + self.match("register read r8l", + ["r8l = 0x61"]) + self.match("register read mm0", + ["mm0 = 0x0807060504030201"]) + self.match("register read mm1", + ["mm1 = 0x1817161514131211"]) + + # test writing into pseudo-registers + self.runCmd("register write ecx 0xfffefdfc") + reg_data[0] = "fcfdfeff05060708" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read rcx", + ["rcx = 0x08070605fffefdfc"]) + + self.runCmd("register write cx 0xfbfa") + reg_data[0] = "fafbfeff05060708" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ecx", + ["ecx = 0xfffefbfa"]) + self.match("register read rcx", + ["rcx = 0x08070605fffefbfa"]) + + self.runCmd("register write ch 0xf9") + reg_data[0] = "faf9feff05060708" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9fa"]) + self.match("register read ecx", + ["ecx = 0xfffef9fa"]) + self.match("register read rcx", + ["rcx = 0x08070605fffef9fa"]) + + self.runCmd("register write cl 0xf8") + reg_data[0] = "f8f9feff05060708" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9f8"]) + self.match("register read ecx", + ["ecx = 0xfffef9f8"]) + self.match("register read rcx", + ["rcx = 0x08070605fffef9f8"]) + + self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") + reg_data[10] = "f8f9fafbfcfdfeff090a" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read st0", + ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) + @skipIfXmlSupportMissing @skipIfRemote @skipIfLLVMTargetMissing("X86") @@ -272,11 +333,25 @@ # test generic aliases self.match("register read fp", ["ebp = 0x54535251"]) + self.match("register read sp", + ["esp = 0x44434241"]) self.match("register read pc", ["eip = 0x84838281"]) self.match("register read flags", ["eflags = 0x94939291"]) + # test pseudo-registers + self.match("register read cx", + ["cx = 0x1211"]) + self.match("register read ch", + ["ch = 0x12"]) + self.match("register read cl", + ["cl = 0x11"]) + self.match("register read mm0", + ["mm0 = 0x0807060504030201"]) + self.match("register read mm1", + ["mm1 = 0x1817161514131211"]) + # both stX and xmmX should be displayed as vectors self.match("register read st0", ["st0 = {0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a}"]) @@ -289,6 +364,35 @@ ["xmm1 = {0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 " "0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0}"]) + # test writing into pseudo-registers + self.runCmd("register write cx 0xfbfa") + reg_data[1] = "fafb1314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read ecx", + ["ecx = 0x1413fbfa"]) + + self.runCmd("register write ch 0xf9") + reg_data[1] = "faf91314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9fa"]) + self.match("register read ecx", + ["ecx = 0x1413f9fa"]) + + self.runCmd("register write cl 0xf8") + reg_data[1] = "f8f91314" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read cx", + ["cx = 0xf9f8"]) + self.match("register read ecx", + ["ecx = 0x1413f9f8"]) + + self.runCmd("register write mm0 0xfffefdfcfbfaf9f8") + reg_data[10] = "f8f9fafbfcfdfeff090a" + self.assertPacketLogContains(["G" + "".join(reg_data)]) + self.match("register read st0", + ["st0 = {0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff 0x09 0x0a}"]) + @skipIfXmlSupportMissing @skipIfRemote @skipIfLLVMTargetMissing("AArch64")