diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -251,6 +251,9 @@
 def : SysReg<"pmpaddr14", 0x3BE>;
 def : SysReg<"pmpaddr15", 0x3BF>;
 
+def : SysReg<"mseccfg", 0x747>;
+let isRV32Only = 1 in
+def : SysReg<"mseccfgh", 0x757>;
 
 //===--------------------------
 // Machine Counter and Timers
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -276,6 +276,19 @@
 # uimm12
 csrrs t2, 0x3A2, zero
 
+# mseccfg
+# name
+# CHECK-INST: csrrs t1, mseccfg, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t1, mseccfg
+# uimm12
+# CHECK-INST: csrrs t2, mseccfg, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x74]
+# CHECK-INST-ALIAS: csrr t2, mseccfg
+# name
+csrrs t1, mseccfg, zero
+# uimm12
+csrrs t2, 0x747, zero
 
 ######################################
 # Machine Counter and Timers
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -36,6 +36,20 @@
 # uimm12
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# name
+# CHECK-INST: csrrs t1, mseccfgh, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t1, mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, mseccfgh, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, mseccfgh
+# name
+csrrs t1, mseccfgh, zero
+# uimm12
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################
diff --git a/llvm/test/MC/RISCV/rv64-machine-csr-names.s b/llvm/test/MC/RISCV/rv64-machine-csr-names.s
--- a/llvm/test/MC/RISCV/rv64-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv64-machine-csr-names.s
@@ -25,6 +25,13 @@
 # CHECK-INST-ALIAS: csrr t2, 931
 csrrs t2, 0x3A3, zero
 
+# mseccfgh
+# uimm12
+# CHECK-INST: csrrs t2, 1879, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x70,0x75]
+# CHECK-INST-ALIAS: csrr t2, 1879
+csrrs t2, 0x757, zero
+
 ######################################
 # Machine Counter and Timers
 ######################################