Index: lib/Target/WebAssembly/WebAssembly.td =================================================================== --- lib/Target/WebAssembly/WebAssembly.td +++ lib/Target/WebAssembly/WebAssembly.td @@ -22,8 +22,12 @@ // WebAssembly Subtarget features. //===----------------------------------------------------------------------===// -def FeatureSIMD : SubtargetFeature<"simd", "HasSIMD", "true", - "Enable SIMD">; +def FeatureAddr64 : SubtargetFeature<"addr64", "HasAddr64", "false", + "Enable 64-bit address space">; +def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false", + "Enable 128-bit SIMD">; +def FeatureThreads : SubtargetFeature<"threads", "HasThreads", "false", + "Enable threads and atomics">; //===----------------------------------------------------------------------===// // Architectures. @@ -47,7 +51,14 @@ // WebAssembly Processors supported. //===----------------------------------------------------------------------===// -def : ProcessorModel<"generic", NoSchedModel, [FeatureSIMD]>; +// Minimal Viable Product. +def : ProcessorModel<"mvp", NoSchedModel, []>; + +// Latest and greatest experimental version of WebAssembly. Bugs included! +def : ProcessorModel<"bleeding-edge-32", NoSchedModel, + [FeatureSIMD128, FeatureThreads]>; +def : ProcessorModel<"bleeding-edge-64", NoSchedModel, + [FeatureAddr64, FeatureSIMD128, FeatureThreads]>; //===----------------------------------------------------------------------===// // Target Declaration Index: lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp +++ lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp @@ -32,7 +32,7 @@ #include "llvm/Support/Debug.h" using namespace llvm; -#define DEBUG_TYPE "frame-info" +#define DEBUG_TYPE "wasm-frame-info" // TODO: Implement a red zone? Index: lib/Target/WebAssembly/WebAssemblyInstrAtomics.td =================================================================== --- lib/Target/WebAssembly/WebAssemblyInstrAtomics.td +++ lib/Target/WebAssembly/WebAssemblyInstrAtomics.td @@ -11,6 +11,9 @@ // //===----------------------------------------------------------------------===// +// TODO: Implement atomic instructions. +// Note: use Requires<[HasThreads]>, fall back to regular load/store otherwise. + //===----------------------------------------------------------------------===// // Atomic fences //===----------------------------------------------------------------------===// Index: lib/Target/WebAssembly/WebAssemblyInstrInfo.td =================================================================== --- lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -15,6 +15,13 @@ // WebAssembly Instruction Predicate Definitions. //===----------------------------------------------------------------------===// +def HasAddr64 : Predicate<"Subtarget->hasAddr64()">, + AssemblerPredicate<"FeatureAddr64", "addr64">; +def HasSIMD128 : Predicate<"Subtarget->hasSIMD128()">, + AssemblerPredicate<"FeatureSIMD128", "simd128">; +def HasThreads : Predicate<"Subtarget->hasThreads()">, + AssemblerPredicate<"FeatureThreads", "threads">; + //===----------------------------------------------------------------------===// // WebAssembly-specific DAG Node Types. //===----------------------------------------------------------------------===// Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td =================================================================== --- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td +++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td @@ -12,4 +12,4 @@ //===----------------------------------------------------------------------===// // TODO: Implement SIMD instructions. -// Note: use Requires<[HasSIMD]>. +// Note: use Requires<[HasSIMD128]>. Index: lib/Target/WebAssembly/WebAssemblySubtarget.h =================================================================== --- lib/Target/WebAssembly/WebAssemblySubtarget.h +++ lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -29,7 +29,9 @@ namespace llvm { class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { - bool HasSIMD; + bool HasAddr64; + bool HasSIMD128; + bool HasThreads; /// String name of used CPU. std::string CPUString; @@ -66,7 +68,9 @@ bool useAA() const override { return true; } // Predicates used by WebAssemblyInstrInfo.td. - bool hasSIMD() const { return HasSIMD; } + bool hasAddr64() const { return HasAddr64; } + bool hasSIMD128() const { return HasSIMD128; } + bool hasThreads() const { return HasThreads; } /// Parses features string setting specified subtarget options. Definition of /// function is auto generated by tblgen. Index: lib/Target/WebAssembly/WebAssemblySubtarget.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblySubtarget.cpp +++ lib/Target/WebAssembly/WebAssemblySubtarget.cpp @@ -19,7 +19,7 @@ #include "llvm/Support/TargetRegistry.h" using namespace llvm; -#define DEBUG_TYPE "subtarget" +#define DEBUG_TYPE "wasm-subtarget" #define GET_SUBTARGETINFO_CTOR #define GET_SUBTARGETINFO_TARGET_DESC @@ -40,9 +40,9 @@ const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD(true), CPUString(CPU), - TargetTriple(TT), FrameLowering(), - InstrInfo(initializeSubtargetDependencies(FS)), + : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasAddr64(false), + HasSIMD128(false), HasThreads(false), CPUString(CPU), TargetTriple(TT), + FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {} bool WebAssemblySubtarget::enableMachineScheduler() const { return true; }