diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp --- a/clang/lib/Basic/Targets/RISCV.cpp +++ b/clang/lib/Basic/Targets/RISCV.cpp @@ -125,6 +125,7 @@ Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32"); StringRef CodeModel = getTargetOpts().CodeModel; unsigned FLen = ISAInfo->getFLen(); + unsigned MinVLen = ISAInfo->getMinVLen(); if (CodeModel == "default") CodeModel = "small"; @@ -176,6 +177,9 @@ Builder.defineMacro("__riscv_fsqrt"); } + if (MinVLen) + Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen)); + if (ISAInfo->hasExtension("c")) Builder.defineMacro("__riscv_compressed"); diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -448,3 +448,17 @@ // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ // RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s // RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg" + +// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -### %s -c 2>&1 | \ +// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s +// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izvl32b0p10' +// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions' + +// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s +// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izvl32b0p1' +// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension + +// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \ +// RUN: FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s +// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -223,3 +223,8 @@ // RUN: -march=rv64izfh0p1 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s // CHECK-ZFH-EXT: __riscv_zfh 1000 + +// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \ +// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \ +// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s +// CHECK-V-MINVLEN: __riscv_v_min_vlen 128 diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/Support/RISCVISAInfo.h --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/Support/RISCVISAInfo.h @@ -61,6 +61,7 @@ unsigned getXLen() const { return XLen; }; unsigned getFLen() const { return FLen; }; + unsigned getMinVLen() const { return MinVLen; } bool hasExtension(StringRef Ext) const; std::string toString() const; @@ -71,10 +72,11 @@ unsigned MinorVersion); private: - RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0) {} + RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0), MinVLen(0) {} unsigned XLen; unsigned FLen; + unsigned MinVLen; OrderedExtensionMap Exts; @@ -85,6 +87,7 @@ void updateImplication(); void updateFLen(); + void updateMinVLen(); }; } // namespace llvm diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -9,6 +9,7 @@ #include "llvm/Support/RISCVISAInfo.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Errc.h" @@ -63,6 +64,18 @@ {"zvamo", RISCVExtensionVersion{0, 10}}, {"zvlsseg", RISCVExtensionVersion{0, 10}}, + {"zvl32b", RISCVExtensionVersion{0, 10}}, + {"zvl64b", RISCVExtensionVersion{0, 10}}, + {"zvl128b", RISCVExtensionVersion{0, 10}}, + {"zvl256b", RISCVExtensionVersion{0, 10}}, + {"zvl512b", RISCVExtensionVersion{0, 10}}, + {"zvl1024b", RISCVExtensionVersion{0, 10}}, + {"zvl2048b", RISCVExtensionVersion{0, 10}}, + {"zvl4096b", RISCVExtensionVersion{0, 10}}, + {"zvl8192b", RISCVExtensionVersion{0, 10}}, + {"zvl16384b", RISCVExtensionVersion{0, 10}}, + {"zvl32768b", RISCVExtensionVersion{0, 10}}, + {"zvl65536b", RISCVExtensionVersion{0, 10}}, {"zfh", RISCVExtensionVersion{0, 1}}, }; @@ -443,6 +456,7 @@ ISAInfo->updateImplication(); ISAInfo->updateFLen(); + ISAInfo->updateMinVLen(); if (Error Result = ISAInfo->checkDependency()) return std::move(Result); @@ -666,6 +680,7 @@ ISAInfo->updateImplication(); ISAInfo->updateFLen(); + ISAInfo->updateMinVLen(); if (Error Result = ISAInfo->checkDependency()) return std::move(Result); @@ -700,9 +715,23 @@ } void RISCVISAInfo::updateImplication() { + const StringMap> Implications = { + {"v", {"zvlsseg", "zvl128b"}}, + + {"zvl64b", {"zvl32b"}}, + {"zvl128b", {"zvl64b"}}, + {"zvl256b", {"zvl128b"}}, + {"zvl512b", {"zvl256b"}}, + {"zvl1024b", {"zvl512b"}}, + {"zvl2048b", {"zvl1024b"}}, + {"zvl4096b", {"zvl2048b"}}, + {"zvl8192b", {"zvl4096b"}}, + {"zvl16384b", {"zvl8192b"}}, + {"zvl32768b", {"zvl16384b"}}, + {"zvl65536b", {"zvl32768b"}}, + }; bool HasE = Exts.count("e") == 1; bool HasI = Exts.count("i") == 1; - bool HasV = Exts.count("v") == 1; // If not in e extension and i extension does not exist, i extension is // implied @@ -711,9 +740,26 @@ addExtension("i", Version->Major, Version->Minor); } - if (HasV) { - auto Version = findDefaultVersion("zvlsseg"); - addExtension("zvlsseg", Version->Major, Version->Minor); + // This loop may execute over 1 iteration since implication can be layered + // Exits loop if no more implication is applied + SmallSetVector WorkList; + for (auto &Ext : Exts) + WorkList.insert(Ext.first); + + while (!WorkList.empty()) { + auto ExtName = WorkList.pop_back_val(); + auto Implication = Implications.find(ExtName); + if (Implication != Implications.end()) { + for (auto ImpliedExtName : Implication->second) { + if (WorkList.count(ImpliedExtName)) + continue; + if (Exts.count(ImpliedExtName.str())) + continue; + auto Version = findDefaultVersion(ImpliedExtName); + addExtension(ImpliedExtName, Version->Major, Version->Minor); + WorkList.insert(ImpliedExtName); + } + } } } @@ -726,6 +772,19 @@ FLen = 32; } +void RISCVISAInfo::updateMinVLen() { + for (auto Ext : Exts) { + StringRef ExtName = Ext.first; + bool IsZvlExt = ExtName.consume_front("zvl"); + if (IsZvlExt) { + ExtName.consume_back("b"); + unsigned ZvlLen; + ExtName.getAsInteger(10, ZvlLen); + MinVLen = std::max(MinVLen, ZvlLen); + } + } +} + std::string RISCVISAInfo::toString() const { std::string Buffer; raw_string_ostream Arch(Buffer); diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -142,9 +142,47 @@ AssemblerPredicate<(all_of(not FeatureNoRVCHints)), "RVC Hint Instructions">; +def FeatureStdExtZvl32b : SubtargetFeature<"experimental-zvl32b", "ZvlLen", "ExtZvl::Zvl32b", + "'Zvl' (Minimum Vector Length) 32">; +def FeatureStdExtZvl64b : SubtargetFeature<"experimental-zvl64b", "ZvlLen", "ExtZvl::Zvl64b", + "'Zvl' (Minimum Vector Length) 64", + [FeatureStdExtZvl32b]>; +def FeatureStdExtZvl128b : SubtargetFeature<"experimental-zvl128b", "ZvlLen", "ExtZvl::Zvl128b", + "'Zvl' (Minimum Vector Length) 128", + [FeatureStdExtZvl64b]>; +def FeatureStdExtZvl256b : SubtargetFeature<"experimental-zvl256b", "ZvlLen", "ExtZvl::Zvl256b", + "'Zvl' (Minimum Vector Length) 256", + [FeatureStdExtZvl128b]>; +def FeatureStdExtZvl512b : SubtargetFeature<"experimental-zvl512b", "ZvlLen", "ExtZvl::Zvl512b", + "'Zvl' (Minimum Vector Length) 512", + [FeatureStdExtZvl256b]>; +def FeatureStdExtZvl1024b : SubtargetFeature<"experimental-zvl1024b", "ZvlLen", "ExtZvl::Zvl1024b", + "'Zvl' (Minimum Vector Length) 1024", + [FeatureStdExtZvl512b]>; +def FeatureStdExtZvl2048b : SubtargetFeature<"experimental-zvl2048b", "ZvlLen", "ExtZvl::Zvl2048b", + "'Zvl' (Minimum Vector Length) 2048", + [FeatureStdExtZvl1024b]>; +def FeatureStdExtZvl4096b : SubtargetFeature<"experimental-zvl4096b", "ZvlLen", "ExtZvl::Zvl4096b", + "'Zvl' (Minimum Vector Length) 4096", + [FeatureStdExtZvl2048b]>; +def FeatureStdExtZvl8192b : SubtargetFeature<"experimental-zvl8192b", "ZvlLen", "ExtZvl::Zvl8192b", + "'Zvl' (Minimum Vector Length) 8192", + [FeatureStdExtZvl4096b]>; +def FeatureStdExtZvl16384b : SubtargetFeature<"experimental-zvl16384b", "ZvlLen", "ExtZvl::Zvl16384b", + "'Zvl' (Minimum Vector Length) 16384", + [FeatureStdExtZvl8192b]>; +def FeatureStdExtZvl32768b : SubtargetFeature<"experimental-zvl32768b", "ZvlLen", "ExtZvl::Zvl32768b", + "'Zvl' (Minimum Vector Length) 32768", + [FeatureStdExtZvl16384b]>; +def FeatureStdExtZvl65536b : SubtargetFeature<"experimental-zvl65536b", "ZvlLen", "ExtZvl::Zvl65536b", + "'Zvl' (Minimum Vector Length) 65536", + [FeatureStdExtZvl32768b]>; +def HasStdExtZvl : Predicate<"Subtarget->hasStdExtZvl()">; + def FeatureStdExtV : SubtargetFeature<"experimental-v", "HasStdExtV", "true", - "'V' (Vector Instructions)">; + "'V' (Vector Instructions)", + [FeatureStdExtZvl128b]>; def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, AssemblerPredicate<(all_of FeatureStdExtV), "'V' (Vector Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -33,6 +33,22 @@ class StringRef; class RISCVSubtarget : public RISCVGenSubtargetInfo { + enum ExtZvl : unsigned { + NotSet = 0, + Zvl32b = 32, + Zvl64b = 64, + Zvl128b = 128, + Zvl256b = 256, + Zvl512b = 512, + Zvl1024b = 1024, + Zvl2048b = 2048, + Zvl4096b = 4096, + Zvl8192b = 8192, + Zvl16384b = 16384, + Zvl32768b = 32768, + Zvl65536b = 65536 + }; + virtual void anchor(); bool HasStdExtM = false; bool HasStdExtA = false; @@ -59,6 +75,7 @@ bool EnableRVCHintInstrs = true; bool EnableSaveRestore = false; unsigned XLen = 32; + ExtZvl ZvlLen = ExtZvl::NotSet; MVT XLenVT = MVT::i32; uint8_t MaxInterleaveFactor = 2; RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; @@ -117,6 +134,7 @@ bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; } + bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; } bool hasStdExtZvamo() const { return HasStdExtZvamo; } bool hasStdExtZfh() const { return HasStdExtZfh; } bool is64Bit() const { return HasRV64; } diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -114,7 +114,8 @@ assert(hasStdExtV() && "Tried to get vector length without V support!"); if (RVVVectorBitsMax == 0) return 0; - assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 && + // FIXME: Change to >= 32 when VLEN = 32 is supported + assert(RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 && isPowerOf2_32(RVVVectorBitsMax) && "V extension requires vector length to be in the range of 128 to " "65536 and a power of 2!"); @@ -128,14 +129,18 @@ unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const { assert(hasStdExtV() && "Tried to get vector length without V extension support!"); + // FIXME: Change to >= 32 when VLEN = 32 is supported assert((RVVVectorBitsMin == 0 || - (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 && + (RVVVectorBitsMin >= 64 && RVVVectorBitsMax <= 65536 && isPowerOf2_32(RVVVectorBitsMin))) && "V extension requires vector length to be in the range of 128 to " "65536 and a power of 2!"); assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) && "Minimum V extension vector length should not be larger than its " "maximum!"); + if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen) + report_fatal_error(Twine("riscv-v-vector-bits-min specified is lower than " + "the Zvl*b limitation")); unsigned Min = RVVVectorBitsMin; if (RVVVectorBitsMax != 0) Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax); diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -17,7 +17,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV32ZBR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s @@ -35,14 +35,14 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbr %s -o - | FileCheck --check-prefix=RV64ZBR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32A: .attribute 5, "rv32i2p0_a2p0" ; RV32F: .attribute 5, "rv32i2p0_f2p0" ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32C: .attribute 5, "rv32i2p0_c2p0" -; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" +; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1" ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0" @@ -54,7 +54,7 @@ ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93" ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0" ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93" -; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" +; RV32COMBINED: .attribute 5, "rv32i2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0" @@ -72,8 +72,8 @@ ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93" ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0" ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93" -; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10" -; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvlsseg0p10" +; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" +; RV64COMBINED: .attribute 5, "rv64i2p0_v0p10_zfh0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" define i32 @addi(i32 %a) { diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -34,7 +34,7 @@ # CHECK: attribute 5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0" .attribute arch, "rv32iv" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32izba" # CHECK: attribute 5, "rv32i2p0_zba1p0" @@ -70,7 +70,43 @@ # CHECK: attribute 5, "rv32i2p0_f2p0_zfh0p1" .attribute arch, "rv32ivzvamo_zvlsseg" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" .attribute arch, "rv32iv_zvamo0p10_zvlsseg" -# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvlsseg0p10" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl32b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl64b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl128b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl256b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl512b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl1024b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl2048b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl4096b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl8192b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl16384b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl32768b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10" + +.attribute arch, "rv32iv_zvl65536b" +# CHECK: attribute 5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"