Index: llvm/include/llvm/ADT/Any.h =================================================================== --- llvm/include/llvm/ADT/Any.h +++ llvm/include/llvm/ADT/Any.h @@ -23,7 +23,7 @@ namespace llvm { -class LLVM_EXTERNAL_VISIBILITY Any { +class Any { // The `Typeid::Id` static data member below is a globally unique // identifier for the type `T`. It is explicitly marked with default Index: llvm/lib/Target/AArch64/AArch64.h =================================================================== --- llvm/lib/Target/AArch64/AArch64.h +++ llvm/lib/Target/AArch64/AArch64.h @@ -19,7 +19,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64RegisterBankInfo; class AArch64Subtarget; @@ -93,6 +93,6 @@ void initializeSVEIntrinsicOptsPass(PassRegistry&); void initializeAArch64StackTaggingPass(PassRegistry&); void initializeAArch64StackTaggingPreRAPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64CallingConvention.h =================================================================== --- llvm/lib/Target/AArch64/AArch64CallingConvention.h +++ llvm/lib/Target/AArch64/AArch64CallingConvention.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/CallingConvLower.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { bool CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); @@ -46,6 +46,6 @@ bool RetCC_AArch64_WebKit_JS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64ExpandImm.h =================================================================== --- llvm/lib/Target/AArch64/AArch64ExpandImm.h +++ llvm/lib/Target/AArch64/AArch64ExpandImm.h @@ -15,7 +15,7 @@ #include "llvm/ADT/SmallVector.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64_IMM { @@ -30,6 +30,6 @@ } // end namespace AArch64_IMM -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64ExpandImm.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64ExpandImm.cpp +++ llvm/lib/Target/AArch64/AArch64ExpandImm.cpp @@ -14,7 +14,7 @@ #include "AArch64ExpandImm.h" #include "MCTargetDesc/AArch64AddressingModes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64_IMM { @@ -408,4 +408,4 @@ } // end namespace AArch64_AM -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/AArch64FastISel.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -5230,11 +5230,11 @@ return selectOperator(I, I->getOpcode()); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) { return new AArch64FastISel(FuncInfo, LibInfo); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/AArch64FrameLowering.h =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.h +++ llvm/lib/Target/AArch64/AArch64FrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/Support/TypeSize.h" #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCCFIInstruction; @@ -140,6 +140,6 @@ unsigned StackBumpBytes) const; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def =================================================================== --- llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ llvm/lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -10,7 +10,7 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{ /* StartIdx, Length, RegBank */ // 0: FPR 16-bit value. Index: llvm/lib/Target/AArch64/AArch64ISelLowering.h =================================================================== --- llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -21,7 +21,7 @@ #include "llvm/IR/CallingConv.h" #include "llvm/IR/Instruction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64ISD { @@ -1045,6 +1045,6 @@ const TargetLibraryInfo *libInfo); } // end namespace AArch64 -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -23,7 +23,7 @@ #define GET_INSTRINFO_HEADER #include "AArch64GenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64Subtarget; class AArch64TargetMachine; @@ -489,6 +489,6 @@ int getSVENonRevInstr(uint16_t Opcode); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64MCInstLower.h =================================================================== --- llvm/lib/Target/AArch64/AArch64MCInstLower.h +++ llvm/lib/Target/AArch64/AArch64MCInstLower.h @@ -12,7 +12,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AsmPrinter; class MCAsmInfo; class MCContext; @@ -48,6 +48,6 @@ MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h +++ llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h @@ -24,7 +24,7 @@ #include "llvm/MC/MCLinkerOptimizationHint.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace yaml { struct AArch64FunctionInfo; @@ -399,6 +399,6 @@ } // end namespace yaml -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_AARCH64MACHINEFUNCTIONINFO_H Index: llvm/lib/Target/AArch64/AArch64MacroFusion.h =================================================================== --- llvm/lib/Target/AArch64/AArch64MacroFusion.h +++ llvm/lib/Target/AArch64/AArch64MacroFusion.h @@ -13,11 +13,11 @@ #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Note that you have to add: /// DAG.addMutation(createAArch64MacroFusionDAGMutation()); /// to AArch64PassConfig::createMachineScheduler() to have an effect. std::unique_ptr createAArch64MacroFusionDAGMutation(); -} // llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/AArch64MacroFusion.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64MacroFusion.cpp +++ llvm/lib/Target/AArch64/AArch64MacroFusion.cpp @@ -412,11 +412,10 @@ } // end namespace - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createAArch64MacroFusionDAGMutation () { return createMacroFusionDAGMutation(shouldScheduleAdjacent); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h =================================================================== --- llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h +++ llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.h @@ -12,7 +12,7 @@ #include "llvm/ADT/SetVector.h" #include "llvm/CodeGen/PBQPRAConstraint.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; @@ -35,6 +35,6 @@ void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_AARCH64PBQPREGALOC_H Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -16,7 +16,7 @@ #define GET_REGINFO_HEADER #include "AArch64GenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class RegScavenger; @@ -139,6 +139,6 @@ SmallVectorImpl &Ops) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h +++ llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64SelectionDAGInfo : public SelectionDAGTargetInfo { public: @@ -30,6 +30,6 @@ bool ZeroData) const override; bool generateFMAsInMachineCombiner(CodeGenOpt::Level OptLevel) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp +++ llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp @@ -214,7 +214,7 @@ } }; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template <> struct DenseMapInfo { static inline SlotWithTag getEmptyKey() { return {-2, -2}; } static inline SlotWithTag getTombstoneKey() { return {-3, -3}; } @@ -226,7 +226,7 @@ return A == B; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static bool isSlotPreAllocated(MachineFrameInfo *MFI, int FI) { return MFI->getUseLocalStackAllocationBlock() && Index: llvm/lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- llvm/lib/Target/AArch64/AArch64Subtarget.h +++ llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -30,7 +30,7 @@ #define GET_SUBTARGETINFO_HEADER #include "AArch64GenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GlobalValue; class StringRef; class Triple; @@ -583,6 +583,6 @@ unsigned getMinSVEVectorSizeInBits() const; bool useSVEForFixedLengthVectors() const; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64TargetMachine.h =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetMachine.h +++ llvm/lib/Target/AArch64/AArch64TargetMachine.h @@ -18,7 +18,7 @@ #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64RegisterBankInfo; @@ -91,6 +91,6 @@ bool JIT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64TargetObjectFile.h =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetObjectFile.h +++ llvm/lib/Target/AArch64/AArch64TargetObjectFile.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/Target/TargetLoweringObjectFile.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64TargetMachine; /// This implementation is used for AArch64 ELF targets (Linux in particular). @@ -53,6 +53,6 @@ /// This implementation is used for AArch64 COFF targets. class AArch64_COFFTargetObjectFile : public TargetLoweringObjectFileCOFF {}; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -26,7 +26,7 @@ #include "llvm/IR/Intrinsics.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class APInt; class Instruction; @@ -261,6 +261,6 @@ /// @} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_AARCH64TARGETTRANSFORMINFO_H Index: llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h =================================================================== --- llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h +++ llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.h @@ -14,7 +14,7 @@ #include "llvm/MC/MCDisassembler/MCDisassembler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64Disassembler : public MCDisassembler { public: @@ -28,6 +28,6 @@ uint64_t Address, raw_ostream &CStream) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64DISASSEMBLER_H Index: llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.h =================================================================== --- llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.h +++ llvm/lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.h @@ -14,8 +14,9 @@ #define LLVM_LIB_TARGET_AARCH64_DISASSEMBLER_AARCH64EXTERNALSYMBOLIZER_H #include "llvm/MC/MCDisassembler/MCExternalSymbolizer.h" +#include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64ExternalSymbolizer : public MCExternalSymbolizer { public: @@ -32,6 +33,6 @@ uint64_t Offset, uint64_t InstSize) override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/GISel/AArch64CallLowering.h =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64CallLowering.h +++ llvm/lib/Target/AArch64/GISel/AArch64CallLowering.h @@ -20,7 +20,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64TargetLowering; class CCValAssign; @@ -80,6 +80,6 @@ SmallVectorImpl &OutArgs) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING_H Index: llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h +++ llvm/lib/Target/AArch64/GISel/AArch64GlobalISelUtils.h @@ -14,7 +14,7 @@ #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64GISelUtils { /// \returns true if \p C is a legal immediate operand for an arithmetic @@ -24,6 +24,6 @@ } } // namespace AArch64GISelUtils -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp @@ -6013,11 +6013,11 @@ } } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { InstructionSelector * createAArch64InstructionSelector(const AArch64TargetMachine &TM, AArch64Subtarget &Subtarget, AArch64RegisterBankInfo &RBI) { return new AArch64InstructionSelector(TM, Subtarget, RBI); } -} +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h +++ llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LLVMContext; class AArch64Subtarget; @@ -49,5 +49,5 @@ bool legalizeVectorTrunc(MachineInstr &MI, LegalizerHelper &Helper) const; const AArch64Subtarget *ST; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp @@ -347,8 +347,8 @@ "Combine AArch64 MachineInstrs after legalization", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone) { return new AArch64PostLegalizerCombiner(IsOptNone); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp @@ -697,8 +697,8 @@ "Lower AArch64 MachineInstrs after legalization", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAArch64PostLegalizerLowering() { return new AArch64PostLegalizerLowering(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp @@ -180,8 +180,8 @@ "Optimize AArch64 selected instructions", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAArch64PostSelectOptimize() { return new AArch64PostSelectOptimize(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp +++ llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp @@ -186,9 +186,8 @@ "Combine AArch64 machine instrs before legalization", false, false) - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAArch64PreLegalizerCombiner(bool IsOptNone) { return new AArch64PreLegalizerCombiner(IsOptNone); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h =================================================================== --- llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h +++ llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.h @@ -18,7 +18,7 @@ #define GET_REGBANK_DECLARATIONS #include "AArch64GenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; @@ -144,5 +144,5 @@ const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h @@ -20,7 +20,7 @@ #include "llvm/Support/MathExtras.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// AArch64_AM - AArch64 Addressing Mode Stuff namespace AArch64_AM { @@ -844,6 +844,6 @@ } // end namespace AArch64_AM -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCELFStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCELFStreamer *createAArch64ELFStreamer(MCContext &Context, std::unique_ptr TAB, Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp @@ -243,7 +243,7 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AArch64ELFStreamer &AArch64TargetELFStreamer::getStreamer() { return static_cast(Streamer); @@ -276,4 +276,4 @@ return S; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64 { enum Fixups { @@ -64,6 +64,6 @@ }; } // end namespace AArch64 -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h @@ -18,7 +18,7 @@ #include "llvm/MC/MCInstPrinter.h" #include "../Utils/AArch64BaseInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64InstPrinter : public MCInstPrinter { public: @@ -226,6 +226,6 @@ unsigned AltIdx = AArch64::NoRegAltName); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCAsmInfoDarwin.h" #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCStreamer; class Target; class Triple; @@ -41,6 +41,6 @@ explicit AArch64MCAsmInfoGNUCOFF(); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64MCExpr : public MCTargetExpr { public: @@ -173,6 +173,6 @@ static bool classof(const AArch64MCExpr *) { return true; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h @@ -13,11 +13,12 @@ #ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H #define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class formatted_raw_ostream; class MCAsmBackend; class MCCodeEmitter; @@ -69,7 +70,7 @@ void initLLVMToCVRegMapping(MCRegisterInfo *MRI); } -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for AArch64 registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.h @@ -15,7 +15,7 @@ class AArch64ELFStreamer; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AArch64TargetStreamer : public MCTargetStreamer { public: @@ -127,6 +127,6 @@ MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64TargetStreamer.cpp @@ -107,7 +107,7 @@ getStreamer().emitBytes(StringRef(Buffer, 4)); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCTargetStreamer * createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { @@ -119,4 +119,4 @@ return nullptr; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp @@ -141,10 +141,10 @@ return true; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createAArch64WinCOFFObjectWriter() { return std::make_unique(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.h =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.h +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.h @@ -16,12 +16,12 @@ #include "AArch64TargetStreamer.h" #include "llvm/MC/MCWinCOFFStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCWinCOFFStreamer *createAArch64WinCOFFStreamer( MCContext &Context, std::unique_ptr TAB, std::unique_ptr OW, std::unique_ptr Emitter, bool RelaxAll, bool IncrementalLinkerCompatible); -} // end llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp =================================================================== --- llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp +++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp @@ -59,7 +59,7 @@ } } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Helper function to common out unwind code setup for those codes that can // belong to both prolog and epilog. @@ -233,4 +233,4 @@ return S; } -} // end llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp =================================================================== --- llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp +++ llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp @@ -39,7 +39,7 @@ #define DEBUG_TYPE "aarch64-sve-intrinsic-opts" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeSVEIntrinsicOptsPass(PassRegistry &); } @@ -78,9 +78,9 @@ INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass); INITIALIZE_PASS_END(SVEIntrinsicOpts, DEBUG_TYPE, name, false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { ModulePass *createSVEIntrinsicOptsPass() { return new SVEIntrinsicOpts(); } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY /// Returns V if it's a cast from (aka svbool_t), nullptr /// otherwise. Index: llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.h =================================================================== --- llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.h +++ llvm/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.h @@ -9,7 +9,8 @@ #ifndef LLVM_LIB_TARGET_AARCH64_TARGETINFO_AARCH64TARGETINFO_H #define LLVM_LIB_TARGET_AARCH64_TARGETINFO_AARCH64TARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -19,6 +20,6 @@ Target &getTheARM64Target(); Target &getTheARM64_32Target(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AARCH64_TARGETINFO_AARCH64TARGETINFO_H Index: llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h =================================================================== --- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h +++ llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h @@ -24,7 +24,7 @@ #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { inline static unsigned getWRegFromXReg(unsigned Reg) { switch (Reg) { @@ -677,6 +677,6 @@ static constexpr unsigned SVEMaxBitsPerVector = 2048; const unsigned NeonBitsPerVector = 128; } // end namespace AArch64 -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp +++ llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp @@ -17,118 +17,117 @@ using namespace llvm; -namespace llvm { - namespace AArch64AT { +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace AArch64AT { #define GET_AT_IMPL #include "AArch64GenSystemOperands.inc" - } -} - +} // namespace AArch64AT +} // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { - namespace AArch64DBnXS { +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace AArch64DBnXS { #define GET_DBNXS_IMPL #include "AArch64GenSystemOperands.inc" - } -} +} // namespace AArch64DBnXS +} // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64DB { #define GET_DB_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64DC { #define GET_DC_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64IC { #define GET_IC_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64ISB { #define GET_ISB_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64TSB { #define GET_TSB_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64PRCTX { #define GET_PRCTX_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64PRFM { #define GET_PRFM_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64SVEPRFM { #define GET_SVEPRFM_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64SVEPredPattern { #define GET_SVEPREDPAT_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64ExactFPImm { #define GET_EXACTFPIMM_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64PState { #define GET_PSTATE_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64PSBHint { #define GET_PSB_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64BTIHint { #define GET_BTI_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { + namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AArch64SysReg { #define GET_SYSREG_IMPL #include "AArch64GenSystemOperands.inc" } -} + } // namespace LLVM_LIBRARY_VISIBILITY uint32_t AArch64SysReg::parseGenericRegister(StringRef Name) { // Try to parse an S____ register name @@ -163,9 +162,9 @@ utostr(CRm) + "_" + utostr(Op2); } -namespace llvm { - namespace AArch64TLBI { +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace AArch64TLBI { #define GET_TLBITable_IMPL #include "AArch64GenSystemOperands.inc" - } -} +} // namespace AArch64TLBI +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPU.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPU.h +++ llvm/lib/Target/AMDGPU/AMDGPU.h @@ -13,7 +13,7 @@ #include "llvm/IR/PassManager.h" #include "llvm/Support/CodeGen.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUTargetMachine; class FunctionPass; @@ -414,6 +414,6 @@ } } -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h +++ llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h @@ -15,7 +15,7 @@ #include "AMDGPU.h" #include "llvm/Analysis/AliasAnalysis.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class DataLayout; class MDNode; @@ -100,6 +100,6 @@ }) {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUALIASANALYSIS_H Index: llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/Register.h" #include "llvm/Pass.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Function; class LLT; @@ -182,6 +182,6 @@ const AMDGPUFunctionArgInfo &lookupFuncArgInfo(const Function &F) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h +++ llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h @@ -19,7 +19,7 @@ struct amd_kernel_code_t; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUMachineFunction; class AMDGPUTargetStreamer; @@ -150,6 +150,6 @@ size_t DisasmLineMaxLen; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUASMPRINTER_H Index: llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h +++ llvm/lib/Target/AMDGPU/AMDGPUCallLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUTargetLowering; class MachineInstrBuilder; @@ -74,5 +74,5 @@ static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg); static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg); }; -} // End of namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUExportClustering.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUExportClustering.h +++ llvm/lib/Target/AMDGPU/AMDGPUExportClustering.h @@ -7,10 +7,11 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/ScheduleDAGMutation.h" +#include "llvm/Support/Compiler.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createAMDGPUExportClusteringDAGMutation(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp @@ -139,10 +139,10 @@ } // end namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createAMDGPUExportClusteringDAGMutation() { return std::make_unique(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h +++ llvm/lib/Target/AMDGPU/AMDGPUFrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Information about the stack frame layout on the AMDGPU targets. /// @@ -34,6 +34,6 @@ unsigned getStackWidth(const MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUFRAMELOWERING_H Index: llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def +++ llvm/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def @@ -10,7 +10,7 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { enum PartialMappingIdx { Index: llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h +++ llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/Register.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineRegisterInfo; @@ -25,6 +25,6 @@ bool isLegalVOP3PShuffleMask(ArrayRef Mask); } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h +++ llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h @@ -19,7 +19,7 @@ #include "llvm/Support/AMDGPUMetadata.h" #include "llvm/Support/Alignment.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUTargetStreamer; class Argument; @@ -182,6 +182,6 @@ } // end namespace HSAMD } // end namespace AMDGPU -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUHSAMETADATASTREAMER_H Index: llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp @@ -36,7 +36,7 @@ return std::make_pair(Ty, *ArgAlign); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static cl::opt DumpHSAMetadata( "amdgpu-dump-hsa-metadata", @@ -923,4 +923,4 @@ } // end namespace HSAMD } // end namespace AMDGPU -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -32,11 +32,11 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600InstrInfo; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY //===----------------------------------------------------------------------===// // Instruction Selector Implementation Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUMachineFunction; class AMDGPUSubtarget; @@ -530,6 +530,6 @@ } // End namespace AMDGPUISD -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.h @@ -17,7 +17,7 @@ #include "Utils/AMDGPUBaseInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNSubtarget; class MachineFunction; @@ -80,6 +80,6 @@ unsigned Dim); } // end AMDGPU namespace -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h +++ llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h @@ -27,7 +27,7 @@ #undef AMDGPUSubtarget } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { struct ImageDimIntrinsicInfo; @@ -335,5 +335,5 @@ #undef GET_GLOBALISEL_TEMPORARIES_DECL }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h @@ -18,7 +18,7 @@ #include "AMDGPUArgumentUsageInfo.h" #include "SIInstrInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNTargetMachine; class LLVMContext; @@ -189,5 +189,5 @@ bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp +++ llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp @@ -39,7 +39,7 @@ #define MATH_SQRT2 numbers::sqrt2 #define MATH_SQRT1_2 numbers::inv_sqrt2 -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPULibCalls { private: @@ -148,7 +148,7 @@ bool useNative(CallInst *CI); }; -} // end llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY namespace { @@ -837,7 +837,7 @@ return false; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static double log2(double V) { #if _XOPEN_SOURCE >= 600 || defined(_ISOC99_SOURCE) || _POSIX_C_SOURCE >= 200112L return ::log2(V); @@ -845,7 +845,7 @@ return log(V) / numbers::ln2; #endif } -} +} // namespace LLVM_LIBRARY_VISIBILITY bool AMDGPULibCalls::fold_pow(CallInst *CI, IRBuilder<> &B, const FuncInfo &FInfo) { Index: llvm/lib/Target/AMDGPU/AMDGPULibFunc.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPULibFunc.h +++ llvm/lib/Target/AMDGPU/AMDGPULibFunc.h @@ -11,7 +11,7 @@ #include "llvm/ADT/StringRef.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionCallee; class FunctionType; @@ -455,5 +455,5 @@ void setFunctionType(FunctionType *FT) { FuncTy = FT; } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif // _AMDGPU_LIBFUNC_H_ Index: llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h +++ llvm/lib/Target/AMDGPU/AMDGPUMIRFormatter.h @@ -22,7 +22,7 @@ #include "llvm/Support/raw_ostream.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class MachineInstr; @@ -42,6 +42,6 @@ ErrorCallbackType ErrorCallback) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h +++ llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.h @@ -13,7 +13,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNSubtarget; @@ -100,5 +100,5 @@ void setDynLDSAlign(const DataLayout &DL, const GlobalVariable &GV); }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineModuleInfoImpls.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUMachineModuleInfo final : public MachineModuleInfoELF { private: @@ -136,6 +136,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINEMODULEINFO_H Index: llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUMachineModuleInfo.cpp @@ -14,7 +14,7 @@ #include "AMDGPUMachineModuleInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AMDGPUMachineModuleInfo::AMDGPUMachineModuleInfo(const MachineModuleInfo &MMI) : MachineModuleInfoELF(MMI) { @@ -34,4 +34,4 @@ CTX.getOrInsertSyncScopeID("singlethread-one-as"); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h +++ llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.h @@ -7,13 +7,14 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/ScheduleDAGMutation.h" +#include "llvm/Support/Compiler.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Note that you have to add: /// DAG.addMutation(createAMDGPUMacroFusionDAGMutation()); /// to AMDGPUPassConfig::createMachineScheduler() to have an effect. std::unique_ptr createAMDGPUMacroFusionDAGMutation(); -} // llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUMacroFusion.cpp @@ -56,11 +56,10 @@ } // end namespace - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createAMDGPUMacroFusionDAGMutation () { return createMacroFusionDAGMutation(shouldScheduleAdjacent); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUPTNote.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPTNote.h +++ llvm/lib/Target/AMDGPU/AMDGPUPTNote.h @@ -16,7 +16,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUPTNOTE_H #define LLVM_LIB_TARGET_AMDGPU_AMDGPUPTNOTE_H -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { namespace ElfNote { @@ -44,5 +44,5 @@ } // End namespace ElfNote } // End namespace AMDGPU -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUNOTETYPE_H Index: llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.h +++ llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.h @@ -18,7 +18,7 @@ #include "llvm/Analysis/CallGraphSCCPass.h" #include "llvm/IR/ValueMap.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct AMDGPUPerfHintAnalysis : public CallGraphSCCPass { static char ID; @@ -51,5 +51,5 @@ FuncInfoMap FIM; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_MDGPUPERFHINTANALYSIS_H Index: llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp @@ -386,8 +386,8 @@ "Combine AMDGPU machine instrs after legalization", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAMDGPUPostLegalizeCombiner(bool IsOptNone) { return new AMDGPUPostLegalizerCombiner(IsOptNone); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp @@ -144,8 +144,8 @@ "Combine AMDGPU machine instrs before legalization", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAMDGPUPreLegalizeCombiner(bool IsOptNone) { return new AMDGPUPreLegalizerCombiner(IsOptNone); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp @@ -88,11 +88,11 @@ char &llvm::AMDGPUPrintfRuntimeBindingID = AMDGPUPrintfRuntimeBinding::ID; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { ModulePass *createAMDGPUPrintfRuntimeBinding() { return new AMDGPUPrintfRuntimeBinding(); } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY AMDGPUPrintfRuntimeBinding::AMDGPUPrintfRuntimeBinding() : ModulePass(ID) { initializeAMDGPUPrintfRuntimeBindingPass(*PassRegistry::getPassRegistry()); Index: llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp +++ llvm/lib/Target/AMDGPU/AMDGPUPropagateAttributes.cpp @@ -40,7 +40,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { extern const SubtargetFeatureKV AMDGPUFeatureKV[AMDGPU::NumSubtargetFeatures-1]; } Index: llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp +++ llvm/lib/Target/AMDGPU/AMDGPURegBankCombiner.cpp @@ -145,8 +145,8 @@ "Combine AMDGPU machine instrs after regbankselect", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAMDGPURegBankCombiner(bool IsOptNone) { return new AMDGPURegBankCombiner(IsOptNone); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h @@ -21,7 +21,7 @@ #define GET_REGBANK_DECLARATIONS #include "AMDGPUGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LLT; class GCNSubtarget; @@ -190,5 +190,5 @@ MachineRegisterInfo &MRI, const OperandsMapper &OpdMapper) const; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -18,7 +18,7 @@ #include "llvm/IR/CallingConv.h" #include "llvm/Support/Alignment.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { enum AMDGPUDwarfFlavour : unsigned; class Function; @@ -237,6 +237,6 @@ virtual ~AMDGPUSubtarget() {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H Index: llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h +++ llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h @@ -18,7 +18,7 @@ #include "R600Subtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { //===----------------------------------------------------------------------===// // AMDGPU Target Machine (R600+) @@ -121,6 +121,6 @@ SMRange &SourceRange) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H Index: llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h +++ llvm/lib/Target/AMDGPU/AMDGPUTargetObjectFile.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUTargetObjectFile : public TargetLoweringObjectFileELF { public: @@ -27,6 +27,6 @@ const TargetMachine &TM) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -22,7 +22,7 @@ #include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "llvm/CodeGen/BasicTTIImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUTargetLowering; class GCNSubtarget; @@ -256,6 +256,6 @@ int getVectorInstrCost(unsigned Opcode, Type *ValTy, unsigned Index); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETTRANSFORMINFO_H Index: llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp =================================================================== --- llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp +++ llvm/lib/Target/AMDGPU/AMDILCFGStructurizer.cpp @@ -40,11 +40,11 @@ STATISTIC(numClonedBlock, "CFGStructurizer cloned blocks"); STATISTIC(numClonedInstr, "CFGStructurizer cloned instructions"); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeAMDGPUCFGStructurizerPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h =================================================================== --- llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h +++ llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h @@ -20,7 +20,7 @@ #include "llvm/Support/DataExtractor.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInst; class MCOperand; @@ -189,6 +189,6 @@ uint64_t Address) override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H Index: llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h =================================================================== --- llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h +++ llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h @@ -19,7 +19,7 @@ #include "llvm/CodeGen/TargetSchedule.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class MachineInstr; @@ -112,6 +112,6 @@ void Reset() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H Index: llvm/lib/Target/AMDGPU/GCNILPSched.cpp =================================================================== --- llvm/lib/Target/AMDGPU/GCNILPSched.cpp +++ llvm/lib/Target/AMDGPU/GCNILPSched.cpp @@ -353,10 +353,10 @@ return Schedule; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::vector makeGCNILPScheduler(ArrayRef BotRoots, const ScheduleDAG &DAG) { GCNILPScheduler S; return S.schedule(BotRoots, DAG); } -} +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/GCNIterativeScheduler.h =================================================================== --- llvm/lib/Target/AMDGPU/GCNIterativeScheduler.h +++ llvm/lib/Target/AMDGPU/GCNIterativeScheduler.h @@ -20,7 +20,7 @@ #include "GCNRegPressure.h" #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstr; class SUnit; @@ -121,6 +121,6 @@ const GCNRegPressure &After) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_GCNITERATIVESCHEDULER_H Index: llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp =================================================================== --- llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp +++ llvm/lib/Target/AMDGPU/GCNIterativeScheduler.cpp @@ -19,14 +19,14 @@ #define DEBUG_TYPE "machine-scheduler" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::vector makeMinRegSchedule(ArrayRef TopRoots, const ScheduleDAG &DAG); std::vector makeGCNILPScheduler(ArrayRef BotRoots, const ScheduleDAG &DAG); -} + } // namespace LLVM_LIBRARY_VISIBILITY // shim accessors for different order containers static inline MachineInstr *getMachineInstr(MachineInstr *MI) { Index: llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp =================================================================== --- llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp +++ llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp @@ -266,7 +266,7 @@ return Schedule; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::vector makeMinRegSchedule(ArrayRef TopRoots, const ScheduleDAG &DAG) { @@ -274,4 +274,4 @@ return S.schedule(TopRoots, DAG); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/GCNRegPressure.h =================================================================== --- llvm/lib/Target/AMDGPU/GCNRegPressure.h +++ llvm/lib/Target/AMDGPU/GCNRegPressure.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/LiveIntervals.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineRegisterInfo; class raw_ostream; @@ -267,6 +267,6 @@ const LiveIntervals &LIS, const MachineRegisterInfo &MRI); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_GCNREGPRESSURE_H Index: llvm/lib/Target/AMDGPU/GCNSchedStrategy.h =================================================================== --- llvm/lib/Target/AMDGPU/GCNSchedStrategy.h +++ llvm/lib/Target/AMDGPU/GCNSchedStrategy.h @@ -16,7 +16,7 @@ #include "GCNRegPressure.h" #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SIMachineFunctionInfo; class SIRegisterInfo; @@ -124,6 +124,6 @@ void finalizeSchedule() override; }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // GCNSCHEDSTRATEGY_H Index: llvm/lib/Target/AMDGPU/GCNSubtarget.h =================================================================== --- llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -21,17 +21,17 @@ #include "SIInstrInfo.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInst; class MCInstrInfo; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_SUBTARGETINFO_HEADER #include "AMDGPUGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNTargetMachine; @@ -1059,6 +1059,6 @@ SDep &Dep) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFStreamer.h @@ -14,8 +14,10 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUELFSTREAMER_H +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -29,6 +31,6 @@ std::unique_ptr OW, std::unique_ptr Emitter, bool RelaxAll); -} // namespace llvm. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { enum Fixups { /// 16-bit PC relative fixup for SOPP branch instructions. @@ -22,6 +22,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -14,7 +14,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AMDGPUInstPrinter : public MCInstPrinter { public: @@ -274,6 +274,6 @@ void printWrite(const MCInst *MI, unsigned OpNo, raw_ostream &O); }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h @@ -14,7 +14,7 @@ #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -29,5 +29,5 @@ bool shouldOmitSectionDirective(StringRef SectionName) const override; unsigned getMaxInstLength(const MCSubtargetInfo *STI) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -15,9 +15,11 @@ #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCCODEEMITTER_H #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInst; class MCInstrInfo; @@ -82,6 +84,6 @@ const FeatureBitset &AvailableFeatures) const; }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h @@ -15,9 +15,11 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUMCTARGETDESC_H +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -52,7 +54,7 @@ std::unique_ptr createAMDGPUELFObjectWriter(bool Is64Bit, uint8_t OSABI, bool HasRelocationAddend, uint8_t ABIVersion); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_REGINFO_ENUM #include "AMDGPUGenRegisterInfo.inc" Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h =================================================================== --- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h +++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h @@ -14,7 +14,7 @@ struct amd_kernel_code_t; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class DataLayout; class Function; @@ -185,5 +185,5 @@ bool ReserveXNACK) override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/R600AsmPrinter.h =================================================================== --- llvm/lib/Target/AMDGPU/R600AsmPrinter.h +++ llvm/lib/Target/AMDGPU/R600AsmPrinter.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/AsmPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600AsmPrinter final : public AsmPrinter { @@ -40,6 +40,6 @@ createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr &&Streamer); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_R600ASMPRINTER_H Index: llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp =================================================================== --- llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp +++ llvm/lib/Target/AMDGPU/R600EmitClauseMarkers.cpp @@ -20,11 +20,11 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeR600EmitClauseMarkersPass(PassRegistry&); +void initializeR600EmitClauseMarkersPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/AMDGPU/R600FrameLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/R600FrameLowering.h +++ llvm/lib/Target/AMDGPU/R600FrameLowering.h @@ -11,7 +11,7 @@ #include "AMDGPUFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600FrameLowering : public AMDGPUFrameLowering { public: @@ -32,6 +32,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_R600FRAMELOWERING_H Index: llvm/lib/Target/AMDGPU/R600ISelLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/R600ISelLowering.h +++ llvm/lib/Target/AMDGPU/R600ISelLowering.h @@ -16,7 +16,7 @@ #include "AMDGPUISelLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600InstrInfo; class R600Subtarget; @@ -107,6 +107,6 @@ SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override; }; -} // End namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/R600InstrInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/R600InstrInfo.h +++ llvm/lib/Target/AMDGPU/R600InstrInfo.h @@ -20,7 +20,7 @@ #define GET_INSTRINFO_HEADER #include "R600GenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace R600InstrFlags { enum : uint64_t { @@ -332,6 +332,6 @@ } //End namespace AMDGPU -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/R600MachineFunctionInfo.h @@ -14,7 +14,7 @@ #include "AMDGPUMachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600MachineFunctionInfo final : public AMDGPUMachineFunction { public: @@ -22,6 +22,6 @@ unsigned CFStackSize; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/R600MachineScheduler.h =================================================================== --- llvm/lib/Target/AMDGPU/R600MachineScheduler.h +++ llvm/lib/Target/AMDGPU/R600MachineScheduler.h @@ -19,7 +19,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600InstrInfo; struct R600RegisterInfo; @@ -94,6 +94,6 @@ void MoveUnits(std::vector &QSrc, std::vector &QDst); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_R600MACHINESCHEDULER_H Index: llvm/lib/Target/AMDGPU/R600RegisterInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/R600RegisterInfo.h +++ llvm/lib/Target/AMDGPU/R600RegisterInfo.h @@ -17,7 +17,7 @@ #define GET_REGINFO_HEADER #include "R600GenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct R600RegisterInfo final : public R600GenRegisterInfo { R600RegisterInfo() : R600GenRegisterInfo(0) {} @@ -54,6 +54,6 @@ void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const; }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/R600Subtarget.h =================================================================== --- llvm/lib/Target/AMDGPU/R600Subtarget.h +++ llvm/lib/Target/AMDGPU/R600Subtarget.h @@ -21,17 +21,17 @@ #include "Utils/AMDGPUBaseInfo.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInst; class MCInstrInfo; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_SUBTARGETINFO_HEADER #include "R600GenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class R600Subtarget final : public R600GenSubtargetInfo, public AMDGPUSubtarget { @@ -169,6 +169,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_R600SUBTARGET_H Index: llvm/lib/Target/AMDGPU/SIDefines.h =================================================================== --- llvm/lib/Target/AMDGPU/SIDefines.h +++ llvm/lib/Target/AMDGPU/SIDefines.h @@ -12,7 +12,7 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SIInstrFlags { // This needs to be kept in sync with the field bits in InstSI. @@ -866,6 +866,6 @@ #define R_SPILLED_SGPRS 0x4 #define R_SPILLED_VGPRS 0x8 -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/SIFrameLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/SIFrameLowering.h +++ llvm/lib/Target/AMDGPU/SIFrameLowering.h @@ -11,7 +11,7 @@ #include "AMDGPUFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SIInstrInfo; class SIMachineFunctionInfo; @@ -75,6 +75,6 @@ bool requiresStackPointerReference(const MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H Index: llvm/lib/Target/AMDGPU/SIISelLowering.h =================================================================== --- llvm/lib/Target/AMDGPU/SIISelLowering.h +++ llvm/lib/Target/AMDGPU/SIISelLowering.h @@ -17,7 +17,7 @@ #include "AMDGPUISelLowering.h" #include "AMDGPUArgumentUsageInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNSubtarget; class SIMachineFunctionInfo; @@ -487,6 +487,6 @@ Type *Ty) const; }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -24,7 +24,7 @@ #define GET_INSTRINFO_HEADER #include "AMDGPUGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class APInt; class GCNSubtarget; @@ -1212,6 +1212,6 @@ } // end namespace KernelInputOffsets } // end namespace SI -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -35,7 +35,7 @@ #define GET_INSTRINFO_CTOR_DTOR #include "AMDGPUGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AAResults; @@ -45,8 +45,7 @@ #define GET_RsrcIntrinsics_IMPL #include "AMDGPUGenSearchableTables.inc" } -} - +} // namespace LLVM_LIBRARY_VISIBILITY // Must be at least 4 to be able to branch over minimum unconditional branch // code. This is only for making it possible to write reasonably small tests for Index: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/raw_ostream.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFrameInfo; class MachineFunction; @@ -932,6 +932,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/AMDGPU/SIMachineScheduler.h =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineScheduler.h +++ llvm/lib/Target/AMDGPU/SIMachineScheduler.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SIInstrInfo; class SIRegisterInfo; @@ -495,6 +495,6 @@ std::vector BottomUpIndex2SU; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINESCHEDULER_H Index: llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp =================================================================== --- llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp +++ llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp @@ -135,7 +135,7 @@ #endif -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SISched { static bool tryLess(int TryVal, int CandVal, SISchedulerCandidate &TryCand, @@ -171,7 +171,7 @@ return false; } } // end namespace SISched -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // SIScheduleBlock // Index: llvm/lib/Target/AMDGPU/SIProgramInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIProgramInfo.h +++ llvm/lib/Target/AMDGPU/SIProgramInfo.h @@ -17,9 +17,10 @@ #define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H #include "llvm/IR/CallingConv.h" +#include "llvm/Support/Compiler.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Track resource usage for kernels / entry functions. struct SIProgramInfo { @@ -72,6 +73,6 @@ uint64_t getPGMRSrc1(CallingConv::ID CC) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -17,7 +17,7 @@ #define GET_REGINFO_HEADER #include "AMDGPUGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GCNSubtarget; class LiveIntervals; @@ -330,6 +330,6 @@ RegScavenger *RS) const; }; -} // End namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h +++ llvm/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.h @@ -13,7 +13,9 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_TARGETINFO_AMDGPUTARGETINFO_H #define LLVM_LIB_TARGET_AMDGPU_TARGETINFO_AMDGPUTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -24,6 +26,6 @@ /// The target for GCN GPUs Target &getTheGCNTarget(); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_TARGETINFO_AMDGPUTARGETINFO_H Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUASMUTILS_H #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUASMUTILS_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringLiteral; @@ -53,6 +55,6 @@ } // namespace VGPRIndexMode } // namespace AMDGPU -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -10,7 +10,7 @@ #include "llvm/ADT/StringRef.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { namespace SendMsg { @@ -360,4 +360,4 @@ } // namespace VGPRIndexMode } // namespace AMDGPU -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h @@ -15,7 +15,7 @@ struct amd_kernel_code_t; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct Align; class Argument; @@ -955,6 +955,6 @@ raw_ostream &operator<<(raw_ostream &OS, const AMDGPU::IsaInfo::TargetIDSetting S); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp @@ -83,7 +83,7 @@ } // end namespace anonymous -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AMDGPU { @@ -1796,4 +1796,4 @@ return OS; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h @@ -15,7 +15,7 @@ #define LLVM_LIB_TARGET_AMDGPU_AMDGPUPALMETADATA_H #include "llvm/BinaryFormat/MsgPackDocument.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class Module; @@ -142,6 +142,6 @@ void toMsgPackBlob(std::string &Blob); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUPALMETADATA_H Index: llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h =================================================================== --- llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h +++ llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.h @@ -13,9 +13,11 @@ #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H +#include "llvm/Support/Compiler.h" + struct amd_kernel_code_t; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmParser; class raw_ostream; @@ -30,6 +32,6 @@ bool parseAmdKernelCodeField(StringRef ID, MCAsmParser &Parser, amd_kernel_code_t &C, raw_ostream &Err); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDKERNELCODETUTILS_H Index: llvm/lib/Target/ARC/ARC.h =================================================================== --- llvm/lib/Target/ARC/ARC.h +++ llvm/lib/Target/ARC/ARC.h @@ -17,7 +17,7 @@ #include "MCTargetDesc/ARCMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; class ARCTargetMachine; @@ -28,6 +28,6 @@ FunctionPass *createARCOptAddrMode(); FunctionPass *createARCBranchFinalizePass(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARC_H Index: llvm/lib/Target/ARC/ARCBranchFinalize.cpp =================================================================== --- llvm/lib/Target/ARC/ARCBranchFinalize.cpp +++ llvm/lib/Target/ARC/ARCBranchFinalize.cpp @@ -26,12 +26,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeARCBranchFinalizePass(PassRegistry &Registry); FunctionPass *createARCBranchFinalizePass(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/ARC/ARCFrameLowering.h =================================================================== --- llvm/lib/Target/ARC/ARCFrameLowering.h +++ llvm/lib/Target/ARC/ARCFrameLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class ARCSubtarget; @@ -72,6 +72,6 @@ const ARCSubtarget &ST; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCFRAMELOWERING_H Index: llvm/lib/Target/ARC/ARCISelLowering.h =================================================================== --- llvm/lib/Target/ARC/ARCISelLowering.h +++ llvm/lib/Target/ARC/ARCISelLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Forward delcarations class ARCSubtarget; @@ -114,6 +114,6 @@ bool mayBeEmittedAsTailCall(const CallInst *CI) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCISELLOWERING_H Index: llvm/lib/Target/ARC/ARCInstrInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCInstrInfo.h +++ llvm/lib/Target/ARC/ARCInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "ARCGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARCSubtarget; @@ -98,6 +98,6 @@ unsigned Reg, uint64_t Value) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCINSTRINFO_H Index: llvm/lib/Target/ARC/ARCMCInstLower.h =================================================================== --- llvm/lib/Target/ARC/ARCMCInstLower.h +++ llvm/lib/Target/ARC/ARCMCInstLower.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCInst; @@ -38,6 +38,6 @@ MachineOperandType MOTy, unsigned Offset) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCMCINSTLOWER_H Index: llvm/lib/Target/ARC/ARCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCMachineFunctionInfo.h +++ llvm/lib/Target/ARC/ARCMachineFunctionInfo.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// ARCFunctionInfo - This class is derived from MachineFunction private /// ARC target-specific information for each MachineFunction. @@ -54,6 +54,6 @@ unsigned MaxCallStackReq; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/ARC/ARCOptAddrMode.cpp =================================================================== --- llvm/lib/Target/ARC/ARCOptAddrMode.cpp +++ llvm/lib/Target/ARC/ARCOptAddrMode.cpp @@ -32,10 +32,10 @@ #define OPTADDRMODE_NAME "arc-addr-mode" #define DEBUG_TYPE "arc-addr-mode" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createARCOptAddrMode(); void initializeARCOptAddrModePass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { class ARCOptAddrMode : public MachineFunctionPass { Index: llvm/lib/Target/ARC/ARCRegisterInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCRegisterInfo.h +++ llvm/lib/Target/ARC/ARCRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "ARCGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetInstrInfo; @@ -50,6 +50,6 @@ static bool needsFrameMoves(const MachineFunction &MF); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCREGISTERINFO_H Index: llvm/lib/Target/ARC/ARCSubtarget.h =================================================================== --- llvm/lib/Target/ARC/ARCSubtarget.h +++ llvm/lib/Target/ARC/ARCSubtarget.h @@ -23,7 +23,7 @@ #define GET_SUBTARGETINFO_HEADER #include "ARCGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class TargetMachine; @@ -60,6 +60,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCSUBTARGET_H Index: llvm/lib/Target/ARC/ARCTargetMachine.h =================================================================== --- llvm/lib/Target/ARC/ARCTargetMachine.h +++ llvm/lib/Target/ARC/ARCTargetMachine.h @@ -16,7 +16,7 @@ #include "ARCSubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetPassConfig; @@ -45,6 +45,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCTARGETMACHINE_H Index: llvm/lib/Target/ARC/ARCTargetStreamer.h =================================================================== --- llvm/lib/Target/ARC/ARCTargetStreamer.h +++ llvm/lib/Target/ARC/ARCTargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARCTargetStreamer : public MCTargetStreamer { public: @@ -19,6 +19,6 @@ ~ARCTargetStreamer() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCTARGETSTREAMER_H Index: llvm/lib/Target/ARC/ARCTargetTransformInfo.h =================================================================== --- llvm/lib/Target/ARC/ARCTargetTransformInfo.h +++ llvm/lib/Target/ARC/ARCTargetTransformInfo.h @@ -20,7 +20,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARCSubtarget; class ARCTargetLowering; @@ -49,6 +49,6 @@ TLI(std::move(Arg.TLI)) {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_ARCTARGETTRANSFORMINFO_H Index: llvm/lib/Target/ARC/MCTargetDesc/ARCInfo.h =================================================================== --- llvm/lib/Target/ARC/MCTargetDesc/ARCInfo.h +++ llvm/lib/Target/ARC/MCTargetDesc/ARCInfo.h @@ -16,7 +16,7 @@ #ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H #define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCINFO_H -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Enums corresponding to ARC condition codes namespace ARCCC { @@ -53,6 +53,6 @@ } // end namespace ARCCC -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h =================================================================== --- llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h +++ llvm/lib/Target/ARC/MCTargetDesc/ARCInstPrinter.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARCInstPrinter : public MCInstPrinter { public: @@ -45,6 +45,6 @@ void printBRCCPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_INSTPRINTER_ARCINSTPRINTER_H Index: llvm/lib/Target/ARC/MCTargetDesc/ARCMCAsmInfo.h =================================================================== --- llvm/lib/Target/ARC/MCTargetDesc/ARCMCAsmInfo.h +++ llvm/lib/Target/ARC/MCTargetDesc/ARCMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -26,6 +26,6 @@ explicit ARCMCAsmInfo(const Triple &TT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCMCASMINFO_H Index: llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.h =================================================================== --- llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.h +++ llvm/lib/Target/ARC/MCTargetDesc/ARCMCTargetDesc.h @@ -13,13 +13,14 @@ #ifndef LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCMCTARGETDESC_H #define LLVM_LIB_TARGET_ARC_MCTARGETDESC_ARCMCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for ARC registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/ARC/TargetInfo/ARCTargetInfo.h =================================================================== --- llvm/lib/Target/ARC/TargetInfo/ARCTargetInfo.h +++ llvm/lib/Target/ARC/TargetInfo/ARCTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_ARC_TARGETINFO_ARCTARGETINFO_H #define LLVM_LIB_TARGET_ARC_TARGETINFO_ARCTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheARCTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARC_TARGETINFO_ARCTARGETINFO_H Index: llvm/lib/Target/ARM/ARM.h =================================================================== --- llvm/lib/Target/ARM/ARM.h +++ llvm/lib/Target/ARM/ARM.h @@ -19,7 +19,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMAsmPrinter; class ARMBaseTargetMachine; @@ -77,6 +77,6 @@ void initializeMVEGatherScatterLoweringPass(PassRegistry &); void initializeARMSLSHardeningPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARM_H Index: llvm/lib/Target/ARM/ARMAsmPrinter.h =================================================================== --- llvm/lib/Target/ARM/ARMAsmPrinter.h +++ llvm/lib/Target/ARM/ARMAsmPrinter.h @@ -13,7 +13,7 @@ #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMFunctionInfo; class MCOperand; @@ -152,6 +152,6 @@ /// the .s file. void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -29,7 +29,7 @@ #define GET_INSTRINFO_HEADER #include "ARMGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMBaseRegisterInfo; class ARMSubtarget; @@ -934,6 +934,6 @@ unsigned gettBLXrOpcode(const MachineFunction &MF); unsigned getBLXpredOpcode(const MachineFunction &MF); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -728,7 +728,7 @@ return true; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template <> bool IsCPSRDead(const MachineInstr *MI) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -744,7 +744,7 @@ return true; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY /// GetInstSize - Return the size of the specified MachineInstr. /// Index: llvm/lib/Target/ARM/ARMBaseRegisterInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMBaseRegisterInfo.h +++ llvm/lib/Target/ARM/ARMBaseRegisterInfo.h @@ -24,7 +24,7 @@ #define GET_REGINFO_HEADER #include "ARMGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LiveIntervals; @@ -211,6 +211,6 @@ LiveIntervals &LIS) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H Index: llvm/lib/Target/ARM/ARMBasicBlockInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMBasicBlockInfo.h +++ llvm/lib/Target/ARM/ARMBasicBlockInfo.h @@ -19,7 +19,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct BasicBlockInfo; using BBInfoVector = SmallVectorImpl; @@ -154,6 +154,6 @@ }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMBASICBLOCKINFO_H Index: llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp +++ llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp @@ -22,7 +22,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // mayOptimizeThumb2Instruction - Returns true if optimizeThumb2Instructions // below may shrink MI. @@ -145,4 +145,4 @@ } } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/ARM/ARMBlockPlacement.cpp =================================================================== --- llvm/lib/Target/ARM/ARMBlockPlacement.cpp +++ llvm/lib/Target/ARM/ARMBlockPlacement.cpp @@ -24,7 +24,7 @@ #define DEBUG_TYPE "arm-block-placement" #define DEBUG_PREFIX "ARM Block Placement: " -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMBlockPlacement : public MachineFunctionPass { private: const ARMBaseInstrInfo *TII; @@ -46,7 +46,7 @@ } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY FunctionPass *llvm::createARMBlockPlacementPass() { return new ARMBlockPlacement(); Index: llvm/lib/Target/ARM/ARMCallLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMCallLowering.h +++ llvm/lib/Target/ARM/ARMCallLowering.h @@ -20,7 +20,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMTargetLowering; class MachineFunction; @@ -55,6 +55,6 @@ MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMCALLLOWERING_H Index: llvm/lib/Target/ARM/ARMCallingConv.h =================================================================== --- llvm/lib/Target/ARM/ARMCallingConv.h +++ llvm/lib/Target/ARM/ARMCallingConv.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/CallingConvLower.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { bool CC_ARM_AAPCS(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, @@ -48,6 +48,6 @@ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMConstantPoolValue.h =================================================================== --- llvm/lib/Target/ARM/ARMConstantPoolValue.h +++ llvm/lib/Target/ARM/ARMConstantPoolValue.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BlockAddress; class Constant; @@ -276,6 +276,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMCONSTANTPOOLVALUE_H Index: llvm/lib/Target/ARM/ARMFastISel.cpp =================================================================== --- llvm/lib/Target/ARM/ARMFastISel.cpp +++ llvm/lib/Target/ARM/ARMFastISel.cpp @@ -3074,14 +3074,14 @@ return true; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, - const TargetLibraryInfo *libInfo) { - if (funcInfo.MF->getSubtarget().useFastISel()) - return new ARMFastISel(funcInfo, libInfo); +FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, + const TargetLibraryInfo *libInfo) { + if (funcInfo.MF->getSubtarget().useFastISel()) + return new ARMFastISel(funcInfo, libInfo); - return nullptr; - } + return nullptr; +} -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/ARM/ARMFeatures.h =================================================================== --- llvm/lib/Target/ARM/ARMFeatures.h +++ llvm/lib/Target/ARM/ARMFeatures.h @@ -15,7 +15,7 @@ #include "MCTargetDesc/ARMMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template // could be MachineInstr or MCInst bool IsCPSRDead(const InstrType *Instr); @@ -92,6 +92,6 @@ } } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMFrameLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMFrameLowering.h +++ llvm/lib/Target/ARM/ARMFrameLowering.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; class CalleeSavedInfo; @@ -95,6 +95,6 @@ MachineBasicBlock::iterator MI) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H Index: llvm/lib/Target/ARM/ARMHazardRecognizer.h =================================================================== --- llvm/lib/Target/ARM/ARMHazardRecognizer.h +++ llvm/lib/Target/ARM/ARMHazardRecognizer.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class DataLayout; class MachineFunction; @@ -64,6 +64,6 @@ inline HazardType CheckOffsets(unsigned O0, unsigned O1); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMISelLowering.h =================================================================== --- llvm/lib/Target/ARM/ARMISelLowering.h +++ llvm/lib/Target/ARM/ARMISelLowering.h @@ -32,7 +32,7 @@ #include "llvm/Support/MachineValueType.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; class DataLayout; @@ -931,6 +931,6 @@ } // end namespace ARM -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H Index: llvm/lib/Target/ARM/ARMInstrInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMInstrInfo.h +++ llvm/lib/Target/ARM/ARMInstrInfo.h @@ -16,8 +16,8 @@ #include "ARMBaseInstrInfo.h" #include "ARMRegisterInfo.h" -namespace llvm { - class ARMSubtarget; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class ARMSubtarget; class ARMInstrInfo : public ARMBaseInstrInfo { ARMRegisterInfo RI; @@ -41,6 +41,6 @@ void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMInstructionSelector.cpp =================================================================== --- llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -155,14 +155,14 @@ }; } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { InstructionSelector * createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI, const ARMRegisterBankInfo &RBI) { return new ARMInstructionSelector(TM, STI, RBI); } -} +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_GLOBALISEL_IMPL #include "ARMGenGlobalISel.inc" Index: llvm/lib/Target/ARM/ARMLegalizerInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMLegalizerInfo.h +++ llvm/lib/Target/ARM/ARMLegalizerInfo.h @@ -19,7 +19,7 @@ #include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/IR/Instructions.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; @@ -60,5 +60,5 @@ // bits. FCmpLibcallsList getFCmpLibcalls(CmpInst::Predicate, unsigned Size) const; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMMachineFunctionInfo.h +++ llvm/lib/Target/ARM/ARMMachineFunctionInfo.h @@ -20,7 +20,7 @@ #include "llvm/Support/ErrorHandling.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// ARMFunctionInfo - This class is derived from MachineFunctionInfo and /// contains private ARM-specific information for each MachineFunction. @@ -261,6 +261,6 @@ bool getPreservesR0() const { return PreservesR0; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/ARM/ARMMacroFusion.h =================================================================== --- llvm/lib/Target/ARM/ARMMacroFusion.h +++ llvm/lib/Target/ARM/ARMMacroFusion.h @@ -16,13 +16,13 @@ #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Note that you have to add: /// DAG.addMutation(createARMMacroFusionDAGMutation()); /// to ARMPassConfig::createMachineScheduler() to have an effect. std::unique_ptr createARMMacroFusionDAGMutation(); -} // llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMMacroFusion.cpp =================================================================== --- llvm/lib/Target/ARM/ARMMacroFusion.cpp +++ llvm/lib/Target/ARM/ARMMacroFusion.cpp @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MacroFusion.h" #include "llvm/CodeGen/TargetInstrInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Fuse AES crypto encoding or decoding. static bool isAESPair(const MachineInstr *FirstMI, @@ -66,4 +66,4 @@ return createMacroFusionDAGMutation(shouldScheduleAdjacent); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/ARM/ARMRegisterBankInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMRegisterBankInfo.h +++ llvm/lib/Target/ARM/ARMRegisterBankInfo.h @@ -18,7 +18,7 @@ #define GET_REGBANK_DECLARATIONS #include "ARMGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; @@ -38,5 +38,5 @@ const InstructionMapping & getInstrMapping(const MachineInstr &MI) const override; }; -} // End llvm namespace. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -26,7 +26,7 @@ // FIXME: TableGen this. // If it grows too much and TableGen still isn't ready to do the job, extract it // into an ARMGenRegisterBankInfo.def (similar to AArch64). -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace ARM { enum PartialMappingIdx { PMI_GPR, @@ -127,7 +127,7 @@ } #endif } // end namespace arm -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI) : ARMGenRegisterBankInfo() { Index: llvm/lib/Target/ARM/ARMRegisterInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMRegisterInfo.h +++ llvm/lib/Target/ARM/ARMRegisterInfo.h @@ -15,7 +15,7 @@ #include "ARMBaseRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; @@ -25,6 +25,6 @@ ARMRegisterInfo(); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMSelectionDAGInfo.h +++ llvm/lib/Target/ARM/ARMSelectionDAGInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/RuntimeLibcalls.h" #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace ARM_AM { static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { @@ -63,6 +63,6 @@ RTLIB::Libcall LC) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ARMSubtarget.h =================================================================== --- llvm/lib/Target/ARM/ARMSubtarget.h +++ llvm/lib/Target/ARM/ARMSubtarget.h @@ -36,7 +36,7 @@ #define GET_SUBTARGETINFO_HEADER #include "ARMGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMBaseTargetMachine; class GlobalValue; @@ -920,6 +920,6 @@ bool hardenSlsBlr() const { return HardenSlsBlr; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H Index: llvm/lib/Target/ARM/ARMTargetMachine.h =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.h +++ llvm/lib/Target/ARM/ARMTargetMachine.h @@ -22,7 +22,7 @@ #include "llvm/Target/TargetMachine.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMBaseTargetMachine : public LLVMTargetMachine { public: @@ -100,6 +100,6 @@ CodeGenOpt::Level OL, bool JIT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H Index: llvm/lib/Target/ARM/ARMTargetMachine.cpp =================================================================== --- llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -75,8 +75,8 @@ EnableGlobalMerge("arm-global-merge", cl::Hidden, cl::desc("Enable the global merge pass")); -namespace llvm { - void initializeARMExecutionDomainFixPass(PassRegistry&); +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeARMExecutionDomainFixPass(PassRegistry &); } extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { Index: llvm/lib/Target/ARM/ARMTargetObjectFile.h =================================================================== --- llvm/lib/Target/ARM/ARMTargetObjectFile.h +++ llvm/lib/Target/ARM/ARMTargetObjectFile.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF { public: @@ -39,6 +39,6 @@ const TargetMachine &TM) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMTARGETOBJECTFILE_H Index: llvm/lib/Target/ARM/ARMTargetTransformInfo.h =================================================================== --- llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -27,7 +27,7 @@ #include "llvm/IR/Function.h" #include "llvm/MC/SubtargetFeature.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class APInt; class ARMTargetLowering; @@ -285,6 +285,6 @@ /// @} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -71,9 +71,9 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { extern const MCInstrDesc ARMInsts[]; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { @@ -10635,13 +10635,13 @@ return Match_Success; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template <> inline bool IsCPSRDead(const MCInst *Instr) { return true; // In an assembly source, no need to second-guess } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Returns true if Inst is unpredictable if it is in and IT block, but is not // the last instruction in the block. Index: llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp =================================================================== --- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -682,11 +682,11 @@ return MCDisassembler::Fail; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { extern const MCInstrDesc ARMInsts[]; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the /// immediate Value in the MCInst. The immediate Value has had any PC Index: llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h @@ -20,7 +20,7 @@ #include "llvm/Support/MathExtras.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// ARM_AM - ARM Addressing Mode Stuff namespace ARM_AM { @@ -756,7 +756,7 @@ } } // end namespace ARM_AM -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/TargetRegistry.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMAsmBackend : public MCAsmBackend { // The STI from the target triple the MCAsmBackend was instantiated with @@ -77,6 +77,6 @@ bool isThumb() const { return isThumbMode; } void setIsThumb(bool it) { isThumbMode = it; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h @@ -13,7 +13,7 @@ #include "llvm/BinaryFormat/MachO.h" #include "llvm/MC/MCObjectWriter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMAsmBackendDarwin : public ARMAsmBackend { const MCRegisterInfo &MRI; Triple TT; @@ -35,6 +35,6 @@ uint32_t generateCompactUnwindEncoding( ArrayRef Instrs) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h @@ -20,7 +20,7 @@ #include "llvm/Support/ErrorHandling.h" #include "Utils/ARMBaseInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace ARM_PROC { enum IMod { @@ -450,6 +450,6 @@ } // end namespace ARMII -} // end namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp +++ llvm/lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp @@ -1477,7 +1477,7 @@ UnwindOpAsm.EmitRaw(Opcodes); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCTargetStreamer *createARMTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS, @@ -1517,4 +1517,4 @@ return S; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace ARM { enum Fixups { // 12-bit PC relative relocation for symbol addresses @@ -117,6 +117,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h @@ -16,7 +16,7 @@ #include "MCTargetDesc/ARMMCTargetDesc.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMInstPrinter : public MCInstPrinter { public: @@ -282,6 +282,6 @@ unsigned DefaultAltIdx = ARM::NoRegAltName; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMINSTPRINTER_H Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCAsmInfoDarwin.h" #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin { @@ -50,6 +50,6 @@ explicit ARMCOFFMCAsmInfoGNU(); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCExpr.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMMCExpr : public MCTargetExpr { public: @@ -73,6 +73,6 @@ return E->getKind() == MCExpr::Target; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h @@ -18,7 +18,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class formatted_raw_ostream; class MCAsmBackend; class MCCodeEmitter; @@ -127,7 +127,7 @@ } // end namespace ARM -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for ARM registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h +++ llvm/lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.h @@ -18,7 +18,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCSymbol; @@ -86,6 +86,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMUNWINDOPASM_H Index: llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp =================================================================== --- llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp +++ llvm/lib/Target/ARM/MCTargetDesc/ARMWinCOFFObjectWriter.cpp @@ -88,11 +88,11 @@ return static_cast(Fixup.getKind()) != ARM::fixup_t2_movt_hi16; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createARMWinCOFFObjectWriter(bool Is64Bit) { return std::make_unique(Is64Bit); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/ARM/MVETailPredUtils.h =================================================================== --- llvm/lib/Target/ARM/MVETailPredUtils.h +++ llvm/lib/Target/ARM/MVETailPredUtils.h @@ -20,7 +20,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/CodeGen/TargetInstrInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static inline unsigned VCTPOpcodeToLSTP(unsigned Opcode, bool IsDoLoop) { switch (Opcode) { @@ -152,6 +152,6 @@ MI->eraseFromParent(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_MVETAILPREDUTILS_H Index: llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.h =================================================================== --- llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.h +++ llvm/lib/Target/ARM/TargetInfo/ARMTargetInfo.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_ARM_TARGETINFO_ARMTARGETINFO_H #define LLVM_LIB_TARGET_ARM_TARGETINFO_ARMTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -18,6 +20,6 @@ Target &getTheThumbLETarget(); Target &getTheThumbBETarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_TARGETINFO_ARMTARGETINFO_H Index: llvm/lib/Target/ARM/Thumb1FrameLowering.h =================================================================== --- llvm/lib/Target/ARM/Thumb1FrameLowering.h +++ llvm/lib/Target/ARM/Thumb1FrameLowering.h @@ -11,7 +11,7 @@ #include "ARMFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; class MachineFunction; @@ -84,6 +84,6 @@ bool emitPopSpecialFixUp(MachineBasicBlock &MBB, bool DoIt) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_THUMB1FRAMELOWERING_H Index: llvm/lib/Target/ARM/Thumb1InstrInfo.h =================================================================== --- llvm/lib/Target/ARM/Thumb1InstrInfo.h +++ llvm/lib/Target/ARM/Thumb1InstrInfo.h @@ -16,8 +16,8 @@ #include "ARMBaseInstrInfo.h" #include "ThumbRegisterInfo.h" -namespace llvm { - class ARMSubtarget; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class ARMSubtarget; class Thumb1InstrInfo : public ARMBaseInstrInfo { ThumbRegisterInfo RI; @@ -56,6 +56,6 @@ private: void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/Thumb2InstrInfo.h =================================================================== --- llvm/lib/Target/ARM/Thumb2InstrInfo.h +++ llvm/lib/Target/ARM/Thumb2InstrInfo.h @@ -16,7 +16,7 @@ #include "ARMBaseInstrInfo.h" #include "ThumbRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ARMSubtarget; class ScheduleHazardRecognizer; @@ -93,6 +93,6 @@ // MVEVPTBlockInsertion pass has run, and should be used whenever a predicated // instruction is added to/removed from the block. void recomputeVPTBlockMask(MachineInstr &Instr); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ThumbRegisterInfo.h =================================================================== --- llvm/lib/Target/ARM/ThumbRegisterInfo.h +++ llvm/lib/Target/ARM/ThumbRegisterInfo.h @@ -18,9 +18,9 @@ #include "ARMBaseRegisterInfo.h" #include "llvm/CodeGen/TargetRegisterInfo.h" -namespace llvm { - class ARMSubtarget; - class ARMBaseInstrInfo; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class ARMSubtarget; +class ARMBaseInstrInfo; struct ThumbRegisterInfo : public ARMBaseRegisterInfo { public: @@ -56,6 +56,6 @@ RegScavenger *RS = nullptr) const override; bool useFPForScavengingIndex(const MachineFunction &MF) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/ARM/ThumbRegisterInfo.cpp =================================================================== --- llvm/lib/Target/ARM/ThumbRegisterInfo.cpp +++ llvm/lib/Target/ARM/ThumbRegisterInfo.cpp @@ -31,7 +31,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { extern cl::opt ReuseFrameIndexVals; } Index: llvm/lib/Target/ARM/Utils/ARMBaseInfo.h =================================================================== --- llvm/lib/Target/ARM/Utils/ARMBaseInfo.h +++ llvm/lib/Target/ARM/Utils/ARMBaseInfo.h @@ -21,7 +21,7 @@ #include "llvm/MC/SubtargetFeature.h" #include "MCTargetDesc/ARMMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Enums corresponding to ARM condition codes namespace ARMCC { @@ -232,6 +232,6 @@ #include "ARMGenSystemRegister.inc" } // end namespace ARMBankedReg -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_ARM_UTILS_ARMBASEINFO_H Index: llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp =================================================================== --- llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp +++ llvm/lib/Target/ARM/Utils/ARMBaseInfo.cpp @@ -14,7 +14,7 @@ #include "llvm/ADT/SmallVector.h" using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { ARM::PredBlockMask expandPredBlockMask(ARM::PredBlockMask BlockMask, ARMVCC::VPTCodes Kind) { using PredBlockMask = ARM::PredBlockMask; @@ -74,4 +74,4 @@ #define GET_BANKEDREG_IMPL #include "ARMGenSystemRegister.inc" } // end namespce ARMSysReg -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVR.h =================================================================== --- llvm/lib/Target/AVR/AVR.h +++ llvm/lib/Target/AVR/AVR.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AVRTargetMachine; class FunctionPass; @@ -52,6 +52,6 @@ } // end of namespace AVR -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_H Index: llvm/lib/Target/AVR/AVRAsmPrinter.cpp =================================================================== --- llvm/lib/Target/AVR/AVRAsmPrinter.cpp +++ llvm/lib/Target/AVR/AVRAsmPrinter.cpp @@ -32,7 +32,7 @@ #define DEBUG_TYPE "avr-asm-printer" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// An AVR assembly code printer. class AVRAsmPrinter : public AsmPrinter { @@ -176,7 +176,7 @@ EmitToStreamer(*OutStreamer, I); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmPrinter() { llvm::RegisterAsmPrinter X(llvm::getTheAVRTarget()); Index: llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp =================================================================== --- llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp +++ llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp @@ -1818,8 +1818,8 @@ INITIALIZE_PASS(AVRExpandPseudo, "avr-expand-pseudo", AVR_EXPAND_PSEUDO_NAME, false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAVRExpandPseudoPass() { return new AVRExpandPseudo(); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRFrameLowering.h =================================================================== --- llvm/lib/Target/AVR/AVRFrameLowering.h +++ llvm/lib/Target/AVR/AVRFrameLowering.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Utilities for creating function call frames. class AVRFrameLowering : public TargetFrameLowering { @@ -40,6 +40,6 @@ MachineBasicBlock::iterator MI) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_FRAME_LOWERING_H Index: llvm/lib/Target/AVR/AVRFrameLowering.cpp =================================================================== --- llvm/lib/Target/AVR/AVRFrameLowering.cpp +++ llvm/lib/Target/AVR/AVRFrameLowering.cpp @@ -27,7 +27,7 @@ #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRFrameLowering::AVRFrameLowering() : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(1), -2) {} @@ -530,5 +530,4 @@ /// pointer save/restore pass. FunctionPass *createAVRDynAllocaSRPass() { return new AVRDynAllocaSR(); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp +++ llvm/lib/Target/AVR/AVRISelDAGToDAG.cpp @@ -21,7 +21,7 @@ #define DEBUG_TYPE "avr-isel" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Lowers LLVM IR (in DAG form) to AVR MC instructions (in DAG form). class AVRDAGToDAGISel : public SelectionDAGISel { @@ -550,5 +550,4 @@ return new AVRDAGToDAGISel(TM, OptLevel); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRISelLowering.h =================================================================== --- llvm/lib/Target/AVR/AVRISelLowering.h +++ llvm/lib/Target/AVR/AVRISelLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AVRISD { @@ -184,6 +184,6 @@ MachineBasicBlock *insertMul(MachineInstr &MI, MachineBasicBlock *BB) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_ISEL_LOWERING_H Index: llvm/lib/Target/AVR/AVRISelLowering.cpp =================================================================== --- llvm/lib/Target/AVR/AVRISelLowering.cpp +++ llvm/lib/Target/AVR/AVRISelLowering.cpp @@ -30,7 +30,7 @@ #include "AVRTargetMachine.h" #include "MCTargetDesc/AVRMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM, const AVRSubtarget &STI) @@ -2064,4 +2064,4 @@ report_fatal_error("Invalid register name global variable"); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRInstrInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRInstrInfo.h +++ llvm/lib/Target/AVR/AVRInstrInfo.h @@ -21,7 +21,7 @@ #include "AVRGenInstrInfo.inc" #undef GET_INSTRINFO_HEADER -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AVRCC { @@ -116,6 +116,6 @@ const AVRRegisterInfo RI; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_INSTR_INFO_H Index: llvm/lib/Target/AVR/AVRInstrInfo.cpp =================================================================== --- llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -33,7 +33,7 @@ #define GET_INSTRINFO_CTOR_DTOR #include "AVRGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRInstrInfo::AVRInstrInfo() : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {} @@ -570,5 +570,4 @@ return getInstSizeInBytes(MI); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRMCInstLower.h =================================================================== --- llvm/lib/Target/AVR/AVRMCInstLower.h +++ llvm/lib/Target/AVR/AVRMCInstLower.h @@ -11,7 +11,7 @@ #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AsmPrinter; class MachineInstr; @@ -36,7 +36,7 @@ AsmPrinter &Printer; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_MCINST_LOWER_H Index: llvm/lib/Target/AVR/AVRMCInstLower.cpp =================================================================== --- llvm/lib/Target/AVR/AVRMCInstLower.cpp +++ llvm/lib/Target/AVR/AVRMCInstLower.cpp @@ -21,7 +21,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCOperand AVRMCInstLower::lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const { @@ -107,5 +107,4 @@ } } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRMachineFunctionInfo.h +++ llvm/lib/Target/AVR/AVRMachineFunctionInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Contains AVR-specific information for each MachineFunction. class AVRMachineFunctionInfo : public MachineFunctionInfo { @@ -81,6 +81,6 @@ void setVarArgsFrameIndex(int Idx) { VarArgsFrameIndex = Idx; } }; -} // end llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_MACHINE_FUNCTION_INFO_H Index: llvm/lib/Target/AVR/AVRRegisterInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRRegisterInfo.h +++ llvm/lib/Target/AVR/AVRRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "AVRGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Utilities relating to AVR registers. class AVRRegisterInfo : public AVRGenRegisterInfo { @@ -60,6 +60,6 @@ LiveIntervals &LIS) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_REGISTER_INFO_H Index: llvm/lib/Target/AVR/AVRRegisterInfo.cpp =================================================================== --- llvm/lib/Target/AVR/AVRRegisterInfo.cpp +++ llvm/lib/Target/AVR/AVRRegisterInfo.cpp @@ -29,7 +29,7 @@ #define GET_REGINFO_TARGET_DESC #include "AVRGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRRegisterInfo::AVRRegisterInfo() : AVRGenRegisterInfo(0) {} @@ -290,4 +290,4 @@ return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp =================================================================== --- llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp +++ llvm/lib/Target/AVR/AVRRelaxMemOperations.cpp @@ -141,8 +141,8 @@ INITIALIZE_PASS(AVRRelaxMem, "avr-relax-mem", AVR_RELAX_MEM_OPS_NAME, false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createAVRRelaxMemPass() { return new AVRRelaxMem(); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/AVR/AVRSelectionDAGInfo.h +++ llvm/lib/Target/AVR/AVRSelectionDAGInfo.h @@ -15,13 +15,13 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Holds information about the AVR instruction selection DAG. class AVRSelectionDAGInfo : public SelectionDAGTargetInfo { public: }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_SELECTION_DAG_INFO_H Index: llvm/lib/Target/AVR/AVRSubtarget.h =================================================================== --- llvm/lib/Target/AVR/AVRSubtarget.h +++ llvm/lib/Target/AVR/AVRSubtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "AVRGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A specific AVR target MCU. class AVRSubtarget : public AVRGenSubtargetInfo { @@ -120,6 +120,6 @@ AVRSelectionDAGInfo TSInfo; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_SUBTARGET_H Index: llvm/lib/Target/AVR/AVRSubtarget.cpp =================================================================== --- llvm/lib/Target/AVR/AVRSubtarget.cpp +++ llvm/lib/Target/AVR/AVRSubtarget.cpp @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_CTOR #include "AVRGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRSubtarget::AVRSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const AVRTargetMachine &TM) @@ -54,4 +54,4 @@ return *this; } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRTargetMachine.h =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.h +++ llvm/lib/Target/AVR/AVRTargetMachine.h @@ -22,7 +22,7 @@ #include "AVRSelectionDAGInfo.h" #include "AVRSubtarget.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A generic AVR implementation. class AVRTargetMachine : public LLVMTargetMachine { @@ -51,6 +51,6 @@ AVRSubtarget SubTarget; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_TARGET_MACHINE_H Index: llvm/lib/Target/AVR/AVRTargetMachine.cpp =================================================================== --- llvm/lib/Target/AVR/AVRTargetMachine.cpp +++ llvm/lib/Target/AVR/AVRTargetMachine.cpp @@ -23,7 +23,7 @@ #include "MCTargetDesc/AVRMCTargetDesc.h" #include "TargetInfo/AVRTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static const char *AVRDataLayout = "e-P1-p:16:8-i8:8-i16:8-i32:8-i64:8-f32:8-f64:8-n8-a:8"; @@ -121,4 +121,4 @@ addPass(&BranchRelaxationPassID); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/AVRTargetObjectFile.h =================================================================== --- llvm/lib/Target/AVR/AVRTargetObjectFile.h +++ llvm/lib/Target/AVR/AVRTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Lowering for an AVR ELF32 object file. class AVRTargetObjectFile : public TargetLoweringObjectFileELF { @@ -27,6 +27,6 @@ MCSection *ProgmemDataSection; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_TARGET_OBJECT_FILE_H Index: llvm/lib/Target/AVR/AVRTargetObjectFile.cpp =================================================================== --- llvm/lib/Target/AVR/AVRTargetObjectFile.cpp +++ llvm/lib/Target/AVR/AVRTargetObjectFile.cpp @@ -17,7 +17,7 @@ #include "AVR.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void AVRTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM) { Base::Initialize(Ctx, TM); ProgmemDataSection = @@ -36,5 +36,4 @@ // Otherwise, we work the same way as ELF. return Base::SelectSectionForGlobal(GO, Kind, TM); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.h @@ -19,7 +19,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmBackend.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAssembler; class MCContext; @@ -64,7 +64,7 @@ Triple::OSType OSType; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_ASM_BACKEND_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRAsmBackend.cpp @@ -236,7 +236,7 @@ } // end of ldi namespace } // end of adjust namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Prepare value for the target space for it void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup, @@ -484,5 +484,4 @@ return new AVRAsmBackend(STI.getTargetTriple().getOS()); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRELFObjectWriter.cpp @@ -17,7 +17,7 @@ #include "llvm/MC/MCValue.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Writes AVR machine code into an ELF32 object file. class AVRELFObjectWriter : public MCELFObjectTargetWriter { @@ -155,5 +155,4 @@ return std::make_unique(OSABI); } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.h @@ -11,7 +11,7 @@ #include "AVRTargetStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A target streamer for an AVR ELF object file. class AVRELFStreamer : public AVRTargetStreamer { @@ -23,6 +23,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRELFStreamer.cpp @@ -7,7 +7,7 @@ #include "AVRMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static unsigned getEFlagsForFeatureSet(const FeatureBitset &Features) { unsigned EFlags = 0; @@ -65,4 +65,4 @@ MCA.setELFHeaderEFlags(EFlags); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace AVR { /// The set of supported fixups. @@ -142,6 +142,6 @@ } // end of namespace fixups } -} // end of namespace llvm::AVR +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_FIXUP_KINDS_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.h @@ -17,7 +17,7 @@ #include "MCTargetDesc/AVRMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Prints AVR instructions to a textual stream. class AVRInstPrinter : public MCInstPrinter { @@ -53,7 +53,7 @@ raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_INST_PRINTER_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp @@ -26,7 +26,7 @@ #define DEBUG_TYPE "asm-printer" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Include the auto-generated portion of the assembly writer. #define PRINT_ALIAS_INSTR @@ -194,5 +194,4 @@ } } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -25,6 +25,6 @@ explicit AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_ASM_INFO_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp @@ -14,7 +14,7 @@ #include "llvm/ADT/Triple.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) { CodePointerSize = 2; @@ -26,4 +26,4 @@ SupportsDebugInformation = true; } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.h @@ -22,7 +22,7 @@ #define GET_INSTRINFO_OPERAND_TYPES_ENUM #include "AVRGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCExpr; @@ -109,7 +109,7 @@ MCContext &Ctx; }; -} // end namespace of llvm. +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_CODE_EMITTER_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp @@ -34,7 +34,7 @@ #include "AVRGenInstrInfo.inc" #undef GET_INSTRMAP_INFO -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Performs a post-encoding step on a `LD` or `ST` instruction. /// @@ -299,4 +299,4 @@ #include "AVRGenMCCodeEmitter.inc" -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectWriter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { const int SIZE_LONG = 4; const int SIZE_WORD = 2; @@ -51,6 +51,6 @@ std::unique_ptr OW, std::unique_ptr CE); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_AVR_MCTARGETDESC_AVRMCELFSTREAMER_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp @@ -40,7 +40,7 @@ SizeInBytes, Loc); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCStreamer *createAVRELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr MAB, std::unique_ptr OW, @@ -49,4 +49,4 @@ std::move(CE)); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.h @@ -13,7 +13,7 @@ #include "MCTargetDesc/AVRFixupKinds.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A expression in AVR machine code. class AVRMCExpr : public MCTargetExpr { @@ -86,6 +86,6 @@ ~AVRMCExpr() {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_MCEXPR_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCExpr.cpp @@ -14,7 +14,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCValue.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace { @@ -212,5 +212,4 @@ return VK_AVR_None; } -} // end of namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRMCTargetDesc.h @@ -17,7 +17,7 @@ #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -44,7 +44,7 @@ /// Creates an ELF object writer for AVR. std::unique_ptr createAVRELFObjectWriter(uint8_t OSABI); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_REGINFO_ENUM #include "AVRGenRegisterInfo.inc" Index: llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h +++ llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCELFStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCStreamer; /// A generic AVR target output stream. @@ -28,6 +28,6 @@ explicit AVRTargetAsmStreamer(MCStreamer &S); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_TARGET_STREAMER_H Index: llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp =================================================================== --- llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp +++ llvm/lib/Target/AVR/MCTargetDesc/AVRTargetStreamer.cpp @@ -14,7 +14,7 @@ #include "llvm/MC/MCContext.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { AVRTargetStreamer::AVRTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} @@ -39,5 +39,4 @@ OS.emitSymbolAttribute(DoClearBss, MCSA_Global); } -} // end namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.h =================================================================== --- llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.h +++ llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.h @@ -9,10 +9,12 @@ #ifndef LLVM_AVR_TARGET_INFO_H #define LLVM_AVR_TARGET_INFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheAVRTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_AVR_TARGET_INFO_H Index: llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp =================================================================== --- llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp +++ llvm/lib/Target/AVR/TargetInfo/AVRTargetInfo.cpp @@ -8,12 +8,12 @@ #include "TargetInfo/AVRTargetInfo.h" #include "llvm/Support/TargetRegistry.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { Target &getTheAVRTarget() { static Target TheAVRTarget; return TheAVRTarget; } -} +} // namespace LLVM_LIBRARY_VISIBILITY extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRTargetInfo() { llvm::RegisterTarget X(llvm::getTheAVRTarget(), "avr", Index: llvm/lib/Target/BPF/BPF.h =================================================================== --- llvm/lib/Target/BPF/BPF.h +++ llvm/lib/Target/BPF/BPF.h @@ -13,7 +13,7 @@ #include "llvm/IR/PassManager.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFTargetMachine; ModulePass *createBPFAdjustOpt(); @@ -61,6 +61,6 @@ public: PreservedAnalyses run(Module &M, ModuleAnalysisManager &AM); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp =================================================================== --- llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp +++ llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp @@ -93,7 +93,7 @@ #define DEBUG_TYPE "bpf-abstract-member-access" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { constexpr StringRef BPFCoreSharedInfo::AmaAttr; uint32_t BPFCoreSharedInfo::SeqNum; @@ -109,7 +109,7 @@ BB->getInstList().insert(Before->getIterator(), NewInst); return NewInst; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY using namespace llvm; Index: llvm/lib/Target/BPF/BPFCORE.h =================================================================== --- llvm/lib/Target/BPF/BPFCORE.h +++ llvm/lib/Target/BPF/BPFCORE.h @@ -11,7 +11,7 @@ #include "llvm/ADT/StringRef.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BasicBlock; class Instruction; @@ -71,6 +71,6 @@ Instruction *Before); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFFrameLowering.h =================================================================== --- llvm/lib/Target/BPF/BPFFrameLowering.h +++ llvm/lib/Target/BPF/BPFFrameLowering.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFSubtarget; class BPFFrameLowering : public TargetFrameLowering { @@ -36,5 +36,5 @@ return MBB.erase(MI); } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFISelLowering.h =================================================================== --- llvm/lib/Target/BPF/BPFISelLowering.h +++ llvm/lib/Target/BPF/BPFISelLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFSubtarget; namespace BPFISD { enum NodeType : unsigned { @@ -140,6 +140,6 @@ const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFInstrInfo.h =================================================================== --- llvm/lib/Target/BPF/BPFInstrInfo.h +++ llvm/lib/Target/BPF/BPFInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "BPFGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFInstrInfo : public BPFGenInstrInfo { const BPFRegisterInfo RI; @@ -60,6 +60,6 @@ void expandMEMCPY(MachineBasicBlock::iterator) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFMCInstLower.h =================================================================== --- llvm/lib/Target/BPF/BPFMCInstLower.h +++ llvm/lib/Target/BPF/BPFMCInstLower.h @@ -11,7 +11,7 @@ #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AsmPrinter; class MCContext; class MCInst; @@ -36,6 +36,6 @@ MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const; MCSymbol *GetExternalSymbolSymbol(const MachineOperand &MO) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFPreserveDIType.cpp =================================================================== --- llvm/lib/Target/BPF/BPFPreserveDIType.cpp +++ llvm/lib/Target/BPF/BPFPreserveDIType.cpp @@ -26,9 +26,9 @@ #define DEBUG_TYPE "bpf-preserve-di-type" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { constexpr StringRef BPFCoreSharedInfo::TypeIdAttr; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY using namespace llvm; Index: llvm/lib/Target/BPF/BPFRegisterInfo.h =================================================================== --- llvm/lib/Target/BPF/BPFRegisterInfo.h +++ llvm/lib/Target/BPF/BPFRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "BPFGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct BPFRegisterInfo : public BPFGenRegisterInfo { @@ -34,6 +34,6 @@ Register getFrameRegister(const MachineFunction &MF) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/BPF/BPFSelectionDAGInfo.h +++ llvm/lib/Target/BPF/BPFSelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFSelectionDAGInfo : public SelectionDAGTargetInfo { public: @@ -30,6 +30,6 @@ }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFSubtarget.h =================================================================== --- llvm/lib/Target/BPF/BPFSubtarget.h +++ llvm/lib/Target/BPF/BPFSubtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "BPFGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class BPFSubtarget : public BPFGenSubtargetInfo { @@ -87,6 +87,6 @@ return &InstrInfo.getRegisterInfo(); } }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFTargetMachine.h =================================================================== --- llvm/lib/Target/BPF/BPFTargetMachine.h +++ llvm/lib/Target/BPF/BPFTargetMachine.h @@ -16,7 +16,7 @@ #include "BPFSubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; BPFSubtarget Subtarget; @@ -44,6 +44,6 @@ void registerPassBuilderCallbacks(PassBuilder &PB, bool DebugPassManager) override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BPFTargetTransformInfo.h =================================================================== --- llvm/lib/Target/BPF/BPFTargetTransformInfo.h +++ llvm/lib/Target/BPF/BPFTargetTransformInfo.h @@ -20,7 +20,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; typedef TargetTransformInfo TTI; @@ -56,6 +56,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_BPF_BPFTARGETTRANSFORMINFO_H Index: llvm/lib/Target/BPF/BTF.h =================================================================== --- llvm/lib/Target/BPF/BTF.h +++ llvm/lib/Target/BPF/BTF.h @@ -48,7 +48,7 @@ #ifndef LLVM_LIB_TARGET_BPF_BTF_H #define LLVM_LIB_TARGET_BPF_BTF_H -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace BTF { enum : uint32_t { MAGIC = 0xeB9F, VERSION = 1 }; @@ -256,6 +256,6 @@ }; } // End namespace BTF. -} // End namespace llvm. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/BTFDebug.h =================================================================== --- llvm/lib/Target/BPF/BTFDebug.h +++ llvm/lib/Target/BPF/BTFDebug.h @@ -22,7 +22,7 @@ #include #include "BTF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AsmPrinter; class BTFDebug; @@ -371,6 +371,6 @@ void endModule() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h =================================================================== --- llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h +++ llvm/lib/Target/BPF/MCTargetDesc/BPFInstPrinter.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFInstPrinter : public MCInstPrinter { public: BPFInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -36,6 +36,6 @@ void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); static const char *getRegisterName(unsigned RegNo); }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h =================================================================== --- llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h +++ llvm/lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h @@ -16,7 +16,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BPFMCAsmInfo : public MCAsmInfo { public: @@ -49,6 +49,6 @@ DwarfUsesRelocationsAcrossSections = enable; } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h =================================================================== --- llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h +++ llvm/lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h @@ -14,11 +14,12 @@ #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCTARGETDESC_H #include "llvm/Config/config.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -44,7 +45,7 @@ const MCTargetOptions &Options); std::unique_ptr createBPFELFObjectWriter(uint8_t OSABI); -} +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for BPF registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.h =================================================================== --- llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.h +++ llvm/lib/Target/BPF/TargetInfo/BPFTargetInfo.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_BPF_TARGETINFO_BPFTARGETINFO_H #define LLVM_LIB_TARGET_BPF_TARGETINFO_BPFTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -17,6 +19,6 @@ Target &getTheBPFbeTarget(); Target &getTheBPFTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_BPF_TARGETINFO_BPFTARGETINFO_H Index: llvm/lib/Target/CMakeLists.txt =================================================================== --- llvm/lib/Target/CMakeLists.txt +++ llvm/lib/Target/CMakeLists.txt @@ -22,9 +22,7 @@ # When building shared objects for each target there are some internal APIs # that are used across shared objects which we can't hide. if (NOT BUILD_SHARED_LIBS AND NOT APPLE) - # Set default visibility to hidden, so we don't export all the Target classes - # in libLLVM.so. - set(CMAKE_CXX_VISIBILITY_PRESET hidden) + #add_compile_definitions(LLVM_LIBRARY_VISIBILITY) endif() foreach(t ${LLVM_TARGETS_TO_BUILD}) Index: llvm/lib/Target/CSKY/CSKYTargetMachine.h =================================================================== --- llvm/lib/Target/CSKY/CSKYTargetMachine.h +++ llvm/lib/Target/CSKY/CSKYTargetMachine.h @@ -16,7 +16,7 @@ #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class CSKYTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -33,6 +33,6 @@ return TLOF.get(); } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h =================================================================== --- llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h +++ llvm/lib/Target/CSKY/MCTargetDesc/CSKYAsmBackend.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCTargetOptions.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class CSKYAsmBackend : public MCAsmBackend { @@ -34,6 +34,6 @@ std::unique_ptr createObjectTargetWriter() const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYASMBACKEND_H Index: llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h =================================================================== --- llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h +++ llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class CSKYMCAsmInfo : public MCAsmInfoELF { @@ -24,6 +24,6 @@ public: explicit CSKYMCAsmInfo(const Triple &TargetTriple); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCASMINFO_H Index: llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h =================================================================== --- llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h +++ llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCCodeEmitter.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class CSKYMCCodeEmitter : public MCCodeEmitter { MCContext &Ctx; @@ -56,6 +56,6 @@ const MCSubtargetInfo &STI) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYMCCODEEMITTER_H Index: llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h =================================================================== --- llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h +++ llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCTargetOptions.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -37,7 +37,7 @@ MCCodeEmitter *createCSKYMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, MCContext &Ctx); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_REGINFO_ENUM #include "CSKYGenRegisterInfo.inc" Index: llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.h =================================================================== --- llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.h +++ llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_CSKY_TARGETINFO_CSKYTARGETINFO_H #define LLVM_LIB_TARGET_CSKY_TARGETINFO_CSKYTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheCSKYTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_CSKY_TARGETINFO_CSKYTARGETINFO_H Index: llvm/lib/Target/Hexagon/BitTracker.h =================================================================== --- llvm/lib/Target/Hexagon/BitTracker.h +++ llvm/lib/Target/Hexagon/BitTracker.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BitVector; class ConstantInt; @@ -491,6 +491,6 @@ MachineRegisterInfo &MRI; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_BITTRACKER_H Index: llvm/lib/Target/Hexagon/BitTracker.cpp =================================================================== --- llvm/lib/Target/Hexagon/BitTracker.cpp +++ llvm/lib/Target/Hexagon/BitTracker.cpp @@ -92,25 +92,25 @@ } // end anonymous namespace -namespace llvm { - - raw_ostream &operator<<(raw_ostream &OS, const BT::BitValue &BV) { - switch (BV.Type) { - case BT::BitValue::Top: - OS << 'T'; - break; - case BT::BitValue::Zero: - OS << '0'; - break; - case BT::BitValue::One: - OS << '1'; - break; - case BT::BitValue::Ref: - OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; - break; - } - return OS; +namespace llvm LLVM_LIBRARY_VISIBILITY { + +raw_ostream &operator<<(raw_ostream &OS, const BT::BitValue &BV) { + switch (BV.Type) { + case BT::BitValue::Top: + OS << 'T'; + break; + case BT::BitValue::Zero: + OS << '0'; + break; + case BT::BitValue::One: + OS << '1'; + break; + case BT::BitValue::Ref: + OS << printv(BV.RefI.Reg) << '[' << BV.RefI.Pos << ']'; + break; } + return OS; +} raw_ostream &operator<<(raw_ostream &OS, const BT::RegisterCell &RC) { unsigned n = RC.Bits.size(); @@ -177,7 +177,7 @@ return OS; } -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY void BitTracker::print_cells(raw_ostream &OS) const { for (const std::pair P : Map) Index: llvm/lib/Target/Hexagon/Hexagon.h =================================================================== --- llvm/lib/Target/Hexagon/Hexagon.h +++ llvm/lib/Target/Hexagon/Hexagon.h @@ -14,12 +14,15 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGON_H #define LLVM_LIB_TARGET_HEXAGON_HEXAGON_H -namespace llvm { - class HexagonTargetMachine; - class ImmutablePass; +#include "llvm/Support/Compiler.h" - /// Creates a Hexagon-specific Target Transformation Info pass. - ImmutablePass *createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM); -} // end namespace llvm; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class HexagonTargetMachine; +class ImmutablePass; + +/// Creates a Hexagon-specific Target Transformation Info pass. +ImmutablePass * +createHexagonTargetTransformInfoPass(const HexagonTargetMachine *TM); +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonArch.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonArch.h +++ llvm/lib/Target/Hexagon/HexagonArch.h @@ -15,7 +15,7 @@ #include "HexagonDepArch.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Hexagon { template @@ -33,5 +33,5 @@ return Res; } } // namespace Hexagon -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONARCH_H Index: llvm/lib/Target/Hexagon/HexagonAsmPrinter.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonAsmPrinter.h +++ llvm/lib/Target/Hexagon/HexagonAsmPrinter.h @@ -19,7 +19,7 @@ #include "llvm/MC/MCStreamer.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstr; class MCInst; @@ -56,6 +56,6 @@ const char *ExtraCode, raw_ostream &OS) override; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONASMPRINTER_H Index: llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -53,12 +53,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define DEBUG_TYPE "asm-printer" Index: llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -62,12 +62,12 @@ cl::init(std::numeric_limits::max())); static unsigned CountBitSplit = 0; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonBitSimplifyPass(PassRegistry& Registry); - FunctionPass *createHexagonBitSimplify(); +void initializeHexagonBitSimplifyPass(PassRegistry &Registry); +FunctionPass *createHexagonBitSimplify(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { @@ -2887,12 +2887,12 @@ // r5:4 = memd(r0++#8) // }:endloop0 -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonLoopRescheduling(); - void initializeHexagonLoopReschedulingPass(PassRegistry&); +FunctionPass *createHexagonLoopRescheduling(); +void initializeHexagonLoopReschedulingPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonBitTracker.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonBitTracker.h +++ llvm/lib/Target/Hexagon/HexagonBitTracker.h @@ -13,7 +13,7 @@ #include "llvm/ADT/DenseMap.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonInstrInfo; class HexagonRegisterInfo; @@ -72,6 +72,6 @@ RegExtMap VRX; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBITTRACKER_H Index: llvm/lib/Target/Hexagon/HexagonBlockRanges.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonBlockRanges.h +++ llvm/lib/Target/Hexagon/HexagonBlockRanges.h @@ -17,7 +17,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonSubtarget; class MachineBasicBlock; @@ -244,6 +244,6 @@ raw_ostream &operator<< (raw_ostream &OS, const HexagonBlockRanges::PrintRangeMap &P); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H Index: llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -36,12 +36,12 @@ static cl::opt BranchRelaxSafetyBuffer("branch-relax-safety-buffer", cl::init(200), cl::Hidden, cl::ZeroOrMore, cl::desc("safety buffer size")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonBranchRelaxation(); - void initializeHexagonBranchRelaxationPass(PassRegistry&); +FunctionPass *createHexagonBranchRelaxation(); +void initializeHexagonBranchRelaxationPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -25,12 +25,12 @@ #define DEBUG_TYPE "hexagon_cfg" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonCFGOptimizer(); void initializeHexagonCFGOptimizerPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp +++ llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp @@ -59,11 +59,11 @@ static cl::opt OptEnableConst("commgep-const", cl::init(true), cl::Hidden, cl::ZeroOrMore); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonCommonGEPPass(PassRegistry&); +void initializeHexagonCommonGEPPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { @@ -1298,10 +1298,8 @@ return true; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonCommonGEP() { - return new HexagonCommonGEP(); - } +FunctionPass *createHexagonCommonGEP() { return new HexagonCommonGEP(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp +++ llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp @@ -35,10 +35,10 @@ static cl::opt ReplaceLimit("hexagon-cext-limit", cl::init(0), cl::Hidden, cl::ZeroOrMore, cl::desc("Maximum number of replacements")); -namespace llvm { - void initializeHexagonConstExtendersPass(PassRegistry&); - FunctionPass *createHexagonConstExtenders(); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeHexagonConstExtendersPass(PassRegistry &); +FunctionPass *createHexagonConstExtenders(); +} // namespace LLVM_LIBRARY_VISIBILITY static int32_t adjustUp(int32_t V, uint8_t A, uint8_t O) { assert(isPowerOf2_32(A)); Index: llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp +++ llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp @@ -1835,12 +1835,12 @@ // ---------------------------------------------------------------------- // Hexagon-specific code. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonConstPropagationPass(); - void initializeHexagonConstPropagationPass(PassRegistry &Registry); +FunctionPass *createHexagonConstPropagationPass(); +void initializeHexagonConstPropagationPass(PassRegistry &Registry); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -50,11 +50,10 @@ cl::desc("Maximum distance between a tfr feeding a store we " "consider the store still to be newifiable")); -namespace llvm { - FunctionPass *createHexagonCopyToCombine(); - void initializeHexagonCopyToCombinePass(PassRegistry&); -} - +namespace llvm LLVM_LIBRARY_VISIBILITY { +FunctionPass *createHexagonCopyToCombine(); +void initializeHexagonCopyToCombinePass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonDepArch.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonDepArch.h +++ llvm/lib/Target/Hexagon/HexagonDepArch.h @@ -16,7 +16,7 @@ #include "llvm/ADT/StringRef.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Hexagon { enum class ArchEnum { NoArch, Generic, V5, V55, V60, V62, V65, V66, V67 }; @@ -44,5 +44,5 @@ {"hexagonv67t", Hexagon::ArchEnum::V67}, }; } // namespace Hexagon -} // namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPARCH_H Index: llvm/lib/Target/Hexagon/HexagonDepITypes.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonDepITypes.h +++ llvm/lib/Target/Hexagon/HexagonDepITypes.h @@ -7,8 +7,10 @@ //===----------------------------------------------------------------------===// // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// +// +#include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace HexagonII { enum Type { TypeALU32_2op = 0, @@ -60,4 +62,4 @@ TypeV4LDST = 50, }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h +++ llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h @@ -14,7 +14,7 @@ #include "HexagonInstrInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { inline bool is_TC1(unsigned SchedClass) { switch (SchedClass) { @@ -151,6 +151,6 @@ return false; } } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONDEPTIMINGCLASSES_H Index: llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -91,12 +91,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonEarlyIfConversion(); - void initializeHexagonEarlyIfConversionPass(PassRegistry& Registry); +FunctionPass *createHexagonEarlyIfConversion(); +void initializeHexagonEarlyIfConversionPass(PassRegistry &Registry); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static cl::opt EnableHexagonBP("enable-hexagon-br-prob", cl::Hidden, cl::init(true), cl::desc("Enable branch probability info")); Index: llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -127,12 +127,12 @@ static cl::opt OptCoaLimit("expand-condsets-coa-limit", cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonExpandCondsetsPass(PassRegistry&); - FunctionPass *createHexagonExpandCondsets(); +void initializeHexagonExpandCondsetsPass(PassRegistry &); +FunctionPass *createHexagonExpandCondsets(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { @@ -244,11 +244,11 @@ char HexagonExpandCondsets::ID = 0; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID; +char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets", "Hexagon Expand Condsets", false, false) Index: llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -28,10 +28,10 @@ "hexagon-loop-range", cl::Hidden, cl::init(200), cl::desc("Restrict range of loopN instructions (testing only)")); -namespace llvm { - FunctionPass *createHexagonFixupHwLoops(); - void initializeHexagonFixupHwLoopsPass(PassRegistry&); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +FunctionPass *createHexagonFixupHwLoops(); +void initializeHexagonFixupHwLoopsPass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { struct HexagonFixupHwLoops : public MachineFunctionPass { Index: llvm/lib/Target/Hexagon/HexagonFrameLowering.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonFrameLowering.h +++ llvm/lib/Target/Hexagon/HexagonFrameLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BitVector; class HexagonInstrInfo; @@ -179,6 +179,6 @@ bool mayOverflowFrameOffset(MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONFRAMELOWERING_H Index: llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -192,12 +192,12 @@ static unsigned SpillOptCount = 0; #endif -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonCallFrameInformationPass(PassRegistry&); - FunctionPass *createHexagonCallFrameInformation(); +void initializeHexagonCallFrameInformationPass(PassRegistry &); +FunctionPass *createHexagonCallFrameInformation(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonGenExtract.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenExtract.cpp +++ llvm/lib/Target/Hexagon/HexagonGenExtract.cpp @@ -46,12 +46,12 @@ static cl::opt NeedAnd("extract-needand", cl::init(true), cl::Hidden, cl::desc("Require & in extract patterns")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeHexagonGenExtractPass(PassRegistry&); FunctionPass *createHexagonGenExtract(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonGenInsert.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -494,12 +494,12 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonGenInsertPass(PassRegistry&); - FunctionPass *createHexagonGenInsert(); +void initializeHexagonGenInsertPass(PassRegistry &); +FunctionPass *createHexagonGenInsert(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonGenMux.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -49,12 +49,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonGenMux(); - void initializeHexagonGenMuxPass(PassRegistry& Registry); +FunctionPass *createHexagonGenMux(); +void initializeHexagonGenMuxPass(PassRegistry &Registry); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Initialize this to 0 to always prefer generating mux by default. static cl::opt MinPredDist("hexagon-gen-mux-threshold", cl::Hidden, Index: llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -37,12 +37,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonGenPredicatePass(PassRegistry& Registry); - FunctionPass *createHexagonGenPredicate(); +void initializeHexagonGenPredicatePass(PassRegistry &Registry); +FunctionPass *createHexagonGenPredicate(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -87,12 +87,12 @@ STATISTIC(NumHWLoops, "Number of loops converted to hardware loops"); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonHardwareLoops(); - void initializeHexagonHardwareLoopsPass(PassRegistry&); +FunctionPass *createHexagonHardwareLoops(); +void initializeHexagonHardwareLoopsPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonHazardRecognizer.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonHazardRecognizer.h +++ llvm/lib/Target/Hexagon/HexagonHazardRecognizer.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonHazardRecognizer : public ScheduleHazardRecognizer { DFAPacketizer *Resources; @@ -79,6 +79,6 @@ void AdvanceCycle() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONPROFITRECOGNIZER_H Index: llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h +++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h @@ -21,7 +21,7 @@ #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class HexagonInstrInfo; class HexagonRegisterInfo; @@ -157,6 +157,6 @@ SDValue balanceSubTree(SDNode *N, bool Factorize = false); void rebalanceAddressTrees(); }; // end HexagonDAGToDAGISel -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELDAGTODAG_H Index: llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -57,12 +57,12 @@ /// createHexagonISelDag - This pass converts a legalized DAG into a /// Hexagon-specific DAG, ready for instruction scheduling. /// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, CodeGenOpt::Level OptLevel) { return new HexagonDAGToDAGISel(TM, OptLevel); } -} +} // namespace LLVM_LIBRARY_VISIBILITY void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, const SDLoc &dl) { SDValue Chain = LD->getChain(); Index: llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp +++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp @@ -807,68 +807,67 @@ return static_cast(G.getSubtarget()); } -namespace llvm { - struct HvxSelector { - const HexagonTargetLowering &Lower; - HexagonDAGToDAGISel &ISel; - SelectionDAG &DAG; - const HexagonSubtarget &HST; - const unsigned HwLen; - - HvxSelector(HexagonDAGToDAGISel &HS, SelectionDAG &G) - : Lower(getHexagonLowering(G)), ISel(HS), DAG(G), +namespace llvm LLVM_LIBRARY_VISIBILITY { +struct HvxSelector { + const HexagonTargetLowering &Lower; + HexagonDAGToDAGISel &ISel; + SelectionDAG &DAG; + const HexagonSubtarget &HST; + const unsigned HwLen; + + HvxSelector(HexagonDAGToDAGISel &HS, SelectionDAG &G) + : Lower(getHexagonLowering(G)), ISel(HS), DAG(G), HST(getHexagonSubtarget(G)), HwLen(HST.getVectorLength()) {} - MVT getSingleVT(MVT ElemTy) const { - unsigned NumElems = HwLen / (ElemTy.getSizeInBits()/8); - return MVT::getVectorVT(ElemTy, NumElems); - } + MVT getSingleVT(MVT ElemTy) const { + unsigned NumElems = HwLen / (ElemTy.getSizeInBits() / 8); + return MVT::getVectorVT(ElemTy, NumElems); + } - MVT getPairVT(MVT ElemTy) const { - unsigned NumElems = (2*HwLen) / (ElemTy.getSizeInBits()/8); - return MVT::getVectorVT(ElemTy, NumElems); - } + MVT getPairVT(MVT ElemTy) const { + unsigned NumElems = (2 * HwLen) / (ElemTy.getSizeInBits() / 8); + return MVT::getVectorVT(ElemTy, NumElems); + } + + void selectShuffle(SDNode *N); + void selectRor(SDNode *N); + void selectVAlign(SDNode *N); - void selectShuffle(SDNode *N); - void selectRor(SDNode *N); - void selectVAlign(SDNode *N); - - private: - void select(SDNode *ISelN); - void materialize(const ResultStack &Results); - - SDValue getVectorConstant(ArrayRef Data, const SDLoc &dl); - - enum : unsigned { - None, - PackMux, - }; - OpRef concat(OpRef Va, OpRef Vb, ResultStack &Results); - OpRef packs(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results, - MutableArrayRef NewMask, unsigned Options = None); - OpRef packp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results, - MutableArrayRef NewMask); - OpRef vmuxs(ArrayRef Bytes, OpRef Va, OpRef Vb, - ResultStack &Results); - OpRef vmuxp(ArrayRef Bytes, OpRef Va, OpRef Vb, - ResultStack &Results); - - OpRef shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results); - OpRef shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); - OpRef shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results); - OpRef shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); - - OpRef butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results); - OpRef contracting(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); - OpRef expanding(ShuffleMask SM, OpRef Va, ResultStack &Results); - OpRef perfect(ShuffleMask SM, OpRef Va, ResultStack &Results); - - bool selectVectorConstants(SDNode *N); - bool scalarizeShuffle(ArrayRef Mask, const SDLoc &dl, MVT ResTy, - SDValue Va, SDValue Vb, SDNode *N); +private: + void select(SDNode *ISelN); + void materialize(const ResultStack &Results); + SDValue getVectorConstant(ArrayRef Data, const SDLoc &dl); + + enum : unsigned { + None, + PackMux, }; -} + OpRef concat(OpRef Va, OpRef Vb, ResultStack &Results); + OpRef packs(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results, + MutableArrayRef NewMask, unsigned Options = None); + OpRef packp(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results, + MutableArrayRef NewMask); + OpRef vmuxs(ArrayRef Bytes, OpRef Va, OpRef Vb, + ResultStack &Results); + OpRef vmuxp(ArrayRef Bytes, OpRef Va, OpRef Vb, + ResultStack &Results); + + OpRef shuffs1(ShuffleMask SM, OpRef Va, ResultStack &Results); + OpRef shuffs2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); + OpRef shuffp1(ShuffleMask SM, OpRef Va, ResultStack &Results); + OpRef shuffp2(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); + + OpRef butterfly(ShuffleMask SM, OpRef Va, ResultStack &Results); + OpRef contracting(ShuffleMask SM, OpRef Va, OpRef Vb, ResultStack &Results); + OpRef expanding(ShuffleMask SM, OpRef Va, ResultStack &Results); + OpRef perfect(ShuffleMask SM, OpRef Va, ResultStack &Results); + + bool selectVectorConstants(SDNode *N); + bool scalarizeShuffle(ArrayRef Mask, const SDLoc &dl, MVT ResTy, + SDValue Va, SDValue Vb, SDNode *N); +}; +} // namespace LLVM_LIBRARY_VISIBILITY static void splitMask(ArrayRef Mask, MutableArrayRef MaskL, MutableArrayRef MaskR) { Index: llvm/lib/Target/Hexagon/HexagonISelLowering.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonISelLowering.h +++ llvm/lib/Target/Hexagon/HexagonISelLowering.h @@ -27,7 +27,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace HexagonISD { @@ -504,6 +504,6 @@ SDValue PerformHvxDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONISELLOWERING_H Index: llvm/lib/Target/Hexagon/HexagonInstrInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -26,7 +26,7 @@ #define GET_INSTRINFO_HEADER #include "HexagonGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonSubtarget; class MachineBranchProbabilityInfo; @@ -525,6 +525,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H Index: llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -118,11 +118,11 @@ : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), Subtarget(ST) {} -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace HexagonFUnits { bool isSlot0Only(unsigned units); } -} +} // namespace LLVM_LIBRARY_VISIBILITY static bool isIntRegForSubInst(unsigned Reg) { return (Reg >= Hexagon::R0 && Reg <= Hexagon::R7) || Index: llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h +++ llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.h @@ -12,13 +12,13 @@ #include "llvm/IR/PassManager.h" #include "llvm/Transforms/Scalar/LoopPassManager.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct HexagonLoopIdiomRecognitionPass : PassInfoMixin { PreservedAnalyses run(Loop &L, LoopAnalysisManager &AM, LoopStandardAnalysisResults &AR, LPMUpdater &U); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONLOOPIDIOMRECOGNITION_H Index: llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp +++ llvm/lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp @@ -108,13 +108,12 @@ static const char *HexagonVolatileMemcpyName = "hexagon_memcpy_forward_vp4cp4n2"; - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); Pass *createHexagonLoopIdiomPass(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -31,12 +31,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, MCInst &MCB, HexagonAsmPrinter &AP); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol, HexagonAsmPrinter &Printer, bool MustExtend) { Index: llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ llvm/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Hexagon { @@ -85,6 +85,6 @@ unsigned getStackAlignBasePhysReg() const { return StackAlignBasePhysReg; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/Hexagon/HexagonMachineScheduler.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonMachineScheduler.h +++ llvm/lib/Target/Hexagon/HexagonMachineScheduler.h @@ -28,7 +28,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SUnit; @@ -270,6 +270,6 @@ #endif }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H Index: llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp +++ llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -64,12 +64,12 @@ cl::ZeroOrMore, cl::init(false), cl::desc("Disable New Value Jumps")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonNewValueJump(); void initializeHexagonNewValueJumpPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp +++ llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp @@ -47,12 +47,12 @@ cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode " "optimization")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonOptAddrMode(); - void initializeHexagonOptAddrModePass(PassRegistry&); +FunctionPass *createHexagonOptAddrMode(); +void initializeHexagonOptAddrModePass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp +++ llvm/lib/Target/Hexagon/HexagonOptimizeSZextends.cpp @@ -23,10 +23,10 @@ using namespace llvm; -namespace llvm { - FunctionPass *createHexagonOptimizeSZextends(); - void initializeHexagonOptimizeSZextendsPass(PassRegistry&); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +FunctionPass *createHexagonOptimizeSZextends(); +void initializeHexagonOptimizeSZextendsPass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { struct HexagonOptimizeSZextends : public FunctionPass { Index: llvm/lib/Target/Hexagon/HexagonPeephole.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonPeephole.cpp +++ llvm/lib/Target/Hexagon/HexagonPeephole.cpp @@ -72,10 +72,10 @@ cl::Hidden, cl::ZeroOrMore, cl::init(true), cl::desc("Disable Optimization of extensions to i64.")); -namespace llvm { - FunctionPass *createHexagonPeephole(); - void initializeHexagonPeepholePass(PassRegistry&); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +FunctionPass *createHexagonPeephole(); +void initializeHexagonPeepholePass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { struct HexagonPeephole : public MachineFunctionPass { Index: llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp +++ llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -38,12 +38,12 @@ using namespace llvm; using namespace rdf; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - void initializeHexagonRDFOptPass(PassRegistry&); - FunctionPass *createHexagonRDFOpt(); +void initializeHexagonRDFOptPass(PassRegistry &); +FunctionPass *createHexagonRDFOpt(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static unsigned RDFCount = 0; Index: llvm/lib/Target/Hexagon/HexagonRegisterInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonRegisterInfo.h +++ llvm/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -19,7 +19,7 @@ #define GET_REGINFO_HEADER #include "HexagonGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Hexagon { // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex. @@ -81,6 +81,6 @@ bool isEHReturnCalleeSaveReg(unsigned Reg) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h +++ llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonSelectionDAGInfo : public SelectionDAGTargetInfo { public: @@ -29,6 +29,6 @@ MachinePointerInfo SrcPtrInfo) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ llvm/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -29,10 +29,10 @@ #define DEBUG_TYPE "xfer" -namespace llvm { - FunctionPass *createHexagonSplitConst32AndConst64(); - void initializeHexagonSplitConst32AndConst64Pass(PassRegistry&); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +FunctionPass *createHexagonSplitConst32AndConst64(); +void initializeHexagonSplitConst32AndConst64Pass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { class HexagonSplitConst32AndConst64 : public MachineFunctionPass { Index: llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -44,12 +44,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - FunctionPass *createHexagonSplitDoubleRegs(); - void initializeHexagonSplitDoubleRegsPass(PassRegistry&); +FunctionPass *createHexagonSplitDoubleRegs(); +void initializeHexagonSplitDoubleRegsPass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static cl::opt MaxHSDR("max-hsdr", cl::Hidden, cl::init(-1), cl::desc("Maximum number of split partitions")); Index: llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp +++ llvm/lib/Target/Hexagon/HexagonStoreWidening.cpp @@ -52,12 +52,12 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonStoreWidening(); void initializeHexagonStoreWideningPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonSubtarget.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonSubtarget.h +++ llvm/lib/Target/Hexagon/HexagonSubtarget.h @@ -31,7 +31,7 @@ #define GET_SUBTARGETINFO_HEADER #include "HexagonGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstr; class SDep; @@ -298,6 +298,6 @@ SmallSet &ExclSrc, SmallSet &ExclDst) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONSUBTARGET_H Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.h +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.h @@ -18,7 +18,7 @@ #include "HexagonTargetObjectFile.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Module; @@ -47,6 +47,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -133,58 +133,58 @@ SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", createVLIWMachineSched); -namespace llvm { - extern char &HexagonExpandCondsetsID; - void initializeHexagonBitSimplifyPass(PassRegistry&); - void initializeHexagonConstExtendersPass(PassRegistry&); - void initializeHexagonConstPropagationPass(PassRegistry&); - void initializeHexagonEarlyIfConversionPass(PassRegistry&); - void initializeHexagonExpandCondsetsPass(PassRegistry&); - void initializeHexagonGenMuxPass(PassRegistry&); - void initializeHexagonHardwareLoopsPass(PassRegistry&); - void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); - void initializeHexagonNewValueJumpPass(PassRegistry&); - void initializeHexagonOptAddrModePass(PassRegistry&); - void initializeHexagonPacketizerPass(PassRegistry&); - void initializeHexagonRDFOptPass(PassRegistry&); - void initializeHexagonSplitDoubleRegsPass(PassRegistry&); - void initializeHexagonVectorCombineLegacyPass(PassRegistry&); - void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); - void initializeHexagonVExtractPass(PassRegistry&); - Pass *createHexagonLoopIdiomPass(); - Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); - - FunctionPass *createHexagonBitSimplify(); - FunctionPass *createHexagonBranchRelaxation(); - FunctionPass *createHexagonCallFrameInformation(); - FunctionPass *createHexagonCFGOptimizer(); - FunctionPass *createHexagonCommonGEP(); - FunctionPass *createHexagonConstExtenders(); - FunctionPass *createHexagonConstPropagationPass(); - FunctionPass *createHexagonCopyToCombine(); - FunctionPass *createHexagonEarlyIfConversion(); - FunctionPass *createHexagonFixupHwLoops(); - FunctionPass *createHexagonGenExtract(); - FunctionPass *createHexagonGenInsert(); - FunctionPass *createHexagonGenMux(); - FunctionPass *createHexagonGenPredicate(); - FunctionPass *createHexagonHardwareLoops(); - FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, - CodeGenOpt::Level OptLevel); - FunctionPass *createHexagonLoopRescheduling(); - FunctionPass *createHexagonNewValueJump(); - FunctionPass *createHexagonOptAddrMode(); - FunctionPass *createHexagonOptimizeSZextends(); - FunctionPass *createHexagonPacketizer(bool Minimal); - FunctionPass *createHexagonPeephole(); - FunctionPass *createHexagonRDFOpt(); - FunctionPass *createHexagonSplitConst32AndConst64(); - FunctionPass *createHexagonSplitDoubleRegs(); - FunctionPass *createHexagonStoreWidening(); - FunctionPass *createHexagonVectorCombineLegacyPass(); - FunctionPass *createHexagonVectorPrint(); - FunctionPass *createHexagonVExtract(); -} // end namespace llvm; +namespace llvm LLVM_LIBRARY_VISIBILITY { +extern char &HexagonExpandCondsetsID; +void initializeHexagonBitSimplifyPass(PassRegistry &); +void initializeHexagonConstExtendersPass(PassRegistry &); +void initializeHexagonConstPropagationPass(PassRegistry &); +void initializeHexagonEarlyIfConversionPass(PassRegistry &); +void initializeHexagonExpandCondsetsPass(PassRegistry &); +void initializeHexagonGenMuxPass(PassRegistry &); +void initializeHexagonHardwareLoopsPass(PassRegistry &); +void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); +void initializeHexagonNewValueJumpPass(PassRegistry &); +void initializeHexagonOptAddrModePass(PassRegistry &); +void initializeHexagonPacketizerPass(PassRegistry &); +void initializeHexagonRDFOptPass(PassRegistry &); +void initializeHexagonSplitDoubleRegsPass(PassRegistry &); +void initializeHexagonVectorCombineLegacyPass(PassRegistry &); +void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); +void initializeHexagonVExtractPass(PassRegistry &); +Pass *createHexagonLoopIdiomPass(); +Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); + +FunctionPass *createHexagonBitSimplify(); +FunctionPass *createHexagonBranchRelaxation(); +FunctionPass *createHexagonCallFrameInformation(); +FunctionPass *createHexagonCFGOptimizer(); +FunctionPass *createHexagonCommonGEP(); +FunctionPass *createHexagonConstExtenders(); +FunctionPass *createHexagonConstPropagationPass(); +FunctionPass *createHexagonCopyToCombine(); +FunctionPass *createHexagonEarlyIfConversion(); +FunctionPass *createHexagonFixupHwLoops(); +FunctionPass *createHexagonGenExtract(); +FunctionPass *createHexagonGenInsert(); +FunctionPass *createHexagonGenMux(); +FunctionPass *createHexagonGenPredicate(); +FunctionPass *createHexagonHardwareLoops(); +FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, + CodeGenOpt::Level OptLevel); +FunctionPass *createHexagonLoopRescheduling(); +FunctionPass *createHexagonNewValueJump(); +FunctionPass *createHexagonOptAddrMode(); +FunctionPass *createHexagonOptimizeSZextends(); +FunctionPass *createHexagonPacketizer(bool Minimal); +FunctionPass *createHexagonPeephole(); +FunctionPass *createHexagonRDFOpt(); +FunctionPass *createHexagonSplitConst32AndConst64(); +FunctionPass *createHexagonSplitDoubleRegs(); +FunctionPass *createHexagonStoreWidening(); +FunctionPass *createHexagonVectorCombineLegacyPass(); +FunctionPass *createHexagonVectorPrint(); +FunctionPass *createHexagonVExtract(); +} // namespace LLVM_LIBRARY_VISIBILITY static Reloc::Model getEffectiveRelocModel(Optional RM) { return RM.getValueOr(Reloc::Static); Index: llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h +++ llvm/lib/Target/Hexagon/HexagonTargetObjectFile.h @@ -12,48 +12,47 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/MC/MCSectionELF.h" -namespace llvm { - class Type; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class Type; - class HexagonTargetObjectFile : public TargetLoweringObjectFileELF { - public: - void Initialize(MCContext &Ctx, const TargetMachine &TM) override; +class HexagonTargetObjectFile : public TargetLoweringObjectFileELF { +public: + void Initialize(MCContext &Ctx, const TargetMachine &TM) override; - MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, - const TargetMachine &TM) const override; + MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, + const TargetMachine &TM) const override; - MCSection *getExplicitSectionGlobal(const GlobalObject *GO, - SectionKind Kind, - const TargetMachine &TM) const override; + MCSection *getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, + const TargetMachine &TM) const override; - bool isGlobalInSmallSection(const GlobalObject *GO, - const TargetMachine &TM) const; + bool isGlobalInSmallSection(const GlobalObject *GO, + const TargetMachine &TM) const; - bool isSmallDataEnabled(const TargetMachine &TM) const; + bool isSmallDataEnabled(const TargetMachine &TM) const; - unsigned getSmallDataSize() const; + unsigned getSmallDataSize() const; - bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference, - const Function &F) const override; + bool shouldPutJumpTableInFunctionSection(bool UsesLabelDifference, + const Function &F) const override; - const Function *getLutUsedFunction(const GlobalObject *GO) const; + const Function *getLutUsedFunction(const GlobalObject *GO) const; - private: - MCSectionELF *SmallDataSection; - MCSectionELF *SmallBSSSection; +private: + MCSectionELF *SmallDataSection; + MCSectionELF *SmallBSSSection; - unsigned getSmallestAddressableSize(const Type *Ty, const GlobalValue *GV, - const TargetMachine &TM) const; + unsigned getSmallestAddressableSize(const Type *Ty, const GlobalValue *GV, + const TargetMachine &TM) const; - MCSection *selectSmallSectionForGlobal(const GlobalObject *GO, - SectionKind Kind, - const TargetMachine &TM) const; + MCSection *selectSmallSectionForGlobal(const GlobalObject *GO, + SectionKind Kind, + const TargetMachine &TM) const; - MCSection *selectSectionForLookupTable(const GlobalObject *GO, - const TargetMachine &TM, - const Function *Fn) const; - }; + MCSection *selectSectionForLookupTable(const GlobalObject *GO, + const TargetMachine &TM, + const Function *Fn) const; +}; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonTargetStreamer.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetStreamer.h +++ llvm/lib/Target/Hexagon/HexagonTargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonTargetStreamer : public MCTargetStreamer { public: HexagonTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {} @@ -25,6 +25,6 @@ unsigned ByteAlign, unsigned AccessGranularity){}; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -23,7 +23,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/IR/Function.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Loop; class ScalarEvolution; @@ -168,5 +168,5 @@ bool shouldBuildLookupTables() const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONTARGETTRANSFORMINFO_H Index: llvm/lib/Target/Hexagon/HexagonVExtract.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVExtract.cpp +++ llvm/lib/Target/Hexagon/HexagonVExtract.cpp @@ -31,10 +31,10 @@ cl::Hidden, cl::ZeroOrMore, cl::init(1), cl::desc("Threshold for triggering vextract replacement")); -namespace llvm { - void initializeHexagonVExtractPass(PassRegistry& Registry); - FunctionPass *createHexagonVExtract(); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeHexagonVExtractPass(PassRegistry &Registry); +FunctionPass *createHexagonVExtract(); +} // namespace LLVM_LIBRARY_VISIBILITY namespace { class HexagonVExtract : public MachineFunctionPass { Index: llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h +++ llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.h @@ -14,7 +14,7 @@ #include "llvm/CodeGen/ScheduleDAG.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonInstrInfo; class HexagonRegisterInfo; @@ -159,6 +159,6 @@ bool isPureSlot0InsnWithNoSlot1Store(const MachineInstr &MI); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLIWPACKETIZER_H Index: llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ llvm/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -76,12 +76,12 @@ extern cl::opt ScheduleInlineAsm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonPacketizer(bool Minimal); void initializeHexagonPacketizerPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp +++ llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp @@ -1432,10 +1432,10 @@ // Pass management. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeHexagonVectorCombineLegacyPass(PassRegistry &); FunctionPass *createHexagonVectorCombineLegacyPass(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { class HexagonVectorCombineLegacy : public FunctionPass { Index: llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h =================================================================== --- llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h +++ llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.h @@ -120,7 +120,7 @@ #include "llvm/Transforms/Scalar/LoopPassManager.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Loop; @@ -134,6 +134,6 @@ LoopStandardAnalysisResults &AR, LPMUpdater &U); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONVLCR_H Index: llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp +++ llvm/lib/Target/Hexagon/HexagonVectorLoopCarriedReuse.cpp @@ -58,12 +58,12 @@ cl::desc("Maximum distance of loop carried dependences that are handled"), cl::init(2), cl::ZeroOrMore); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp =================================================================== --- llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp +++ llvm/lib/Target/Hexagon/HexagonVectorPrint.cpp @@ -40,12 +40,12 @@ cl::Hidden, cl::ZeroOrMore, cl::init(false), cl::desc("Enables tracing of vector stores")); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createHexagonVectorPrint(); void initializeHexagonVectorPrintPass(PassRegistry&); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -19,7 +19,7 @@ #include "HexagonDepITypes.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// HexagonII - This namespace holds all of the target specific flags that /// instruction info tracks. @@ -279,6 +279,6 @@ } } // end namespace HexagonII -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Hexagon { enum Fixups { // Branch fixups for R_HEX_B{22,15,7}_PCREL. @@ -137,6 +137,6 @@ Word32_X26 = 0x0fff3fff }; } // namespace Hexagon -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_HEXAGON_HEXAGONFIXUPKINDS_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h @@ -14,7 +14,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Prints bundles as a newline separated list of individual instructions /// Duplexes are separated by a vertical tab \v character /// A trailing line includes bundle properties such as endloop0/1 @@ -47,6 +47,6 @@ bool HasExtender = false; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class HexagonMCAsmInfo : public MCAsmInfoELF { @@ -25,6 +25,6 @@ explicit HexagonMCAsmInfo(const Triple &TT); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.h @@ -22,7 +22,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCInst; @@ -129,6 +129,6 @@ void reportBranchErrors(); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCHECKER_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h @@ -22,7 +22,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCInst; @@ -88,6 +88,6 @@ const FeatureBitset &AvailableFeatures) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCCODEEMITTER_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.h @@ -15,7 +15,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonMCELFStreamer : public MCELFStreamer { std::unique_ptr MCII; @@ -44,6 +44,6 @@ std::unique_ptr OW, std::unique_ptr CE); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCELFSTREAMER_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp @@ -147,8 +147,7 @@ HexagonMCEmitCommonSymbol(Symbol, Size, ByteAlignment, AccessSize); } - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCStreamer *createHexagonELFStreamer(Triple const &TT, MCContext &Context, std::unique_ptr MAB, std::unique_ptr OW, @@ -157,4 +156,4 @@ std::move(CE)); } -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCExpr.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonMCExpr : public MCTargetExpr { public: static HexagonMCExpr *create(MCExpr const *Expr, MCContext &Ctx); @@ -40,6 +40,6 @@ bool S27_2_reloc; bool SignMismatch; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMCEXPR_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class HexagonMCChecker; class MCContext; @@ -367,6 +367,6 @@ } // end namespace HexagonMCInstrInfo -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.h @@ -18,7 +18,7 @@ #include "MCTargetDesc/HexagonShuffler.h" #include "llvm/ADT/SmallVector.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCInst; @@ -62,6 +62,6 @@ MCSubtargetInfo const &STI, MCInst &MCB, SmallVector possibleDuplexes); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCSHUFFLER_H Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -45,7 +45,7 @@ // Name of the global offset table as defined by the Hexagon ABI #define HEXAGON_GOT_SYM_NAME "_GLOBAL_OFFSET_TABLE_" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct InstrStage; class FeatureBitset; @@ -99,7 +99,7 @@ unsigned HexagonGetLastSlot(); unsigned HexagonConvertUnits(unsigned ItinUnits, unsigned *Lanes); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Define symbolic names for Hexagon registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -183,14 +183,13 @@ return (*Lanes = 0, CVI_NONE); } - -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace HexagonFUnits { bool isSlot0Only(unsigned units) { return HexagonItinerariesV62FU::SLOT0 == units; } } // namespace HexagonFUnits -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h =================================================================== --- llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h +++ llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.h @@ -26,7 +26,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCInst; @@ -244,6 +244,6 @@ void reportError(Twine const &Msg); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONSHUFFLER_H Index: llvm/lib/Target/Hexagon/RDFCopy.h =================================================================== --- llvm/lib/Target/Hexagon/RDFCopy.h +++ llvm/lib/Target/Hexagon/RDFCopy.h @@ -16,7 +16,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineDominatorTree; @@ -56,6 +56,6 @@ } // end namespace rdf -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_RDFCOPY_H Index: llvm/lib/Target/Hexagon/RDFDeadCode.h =================================================================== --- llvm/lib/Target/Hexagon/RDFDeadCode.h +++ llvm/lib/Target/Hexagon/RDFDeadCode.h @@ -27,8 +27,8 @@ #include "llvm/CodeGen/RDFLiveness.h" #include "llvm/ADT/SetVector.h" -namespace llvm { - class MachineRegisterInfo; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MachineRegisterInfo; namespace rdf { struct DeadCodeElimination { @@ -61,6 +61,6 @@ void processUse(NodeAddr UA, SetQueue &WorkQ); }; } // namespace rdf -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h =================================================================== --- llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h +++ llvm/lib/Target/Hexagon/TargetInfo/HexagonTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H #define LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheHexagonTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_HEXAGON_TARGETINFO_HEXAGONTARGETINFO_H Index: llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h =================================================================== --- llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h +++ llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCDisassembler/MCDisassembler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiDisassembler : public MCDisassembler { public: @@ -31,6 +31,6 @@ uint64_t Address, raw_ostream &CStream) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_DISASSEMBLER_LANAIDISASSEMBLER_H Index: llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp =================================================================== --- llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp +++ llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp @@ -26,7 +26,7 @@ typedef MCDisassembler::DecodeStatus DecodeStatus; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { Target &getTheLanaiTarget(); } Index: llvm/lib/Target/Lanai/Lanai.h =================================================================== --- llvm/lib/Target/Lanai/Lanai.h +++ llvm/lib/Target/Lanai/Lanai.h @@ -16,7 +16,7 @@ #include "llvm/Pass.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; class LanaiTargetMachine; @@ -36,6 +36,6 @@ // operations. FunctionPass *createLanaiSetflagAluCombinerPass(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAI_H Index: llvm/lib/Target/Lanai/LanaiAluCode.h =================================================================== --- llvm/lib/Target/Lanai/LanaiAluCode.h +++ llvm/lib/Target/Lanai/LanaiAluCode.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/ISDOpcodes.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace LPAC { enum AluCode { ADD = 0x00, @@ -142,6 +142,6 @@ } } } // namespace LPAC -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIALUCODE_H Index: llvm/lib/Target/Lanai/LanaiCondCode.h =================================================================== --- llvm/lib/Target/Lanai/LanaiCondCode.h +++ llvm/lib/Target/Lanai/LanaiCondCode.h @@ -5,7 +5,7 @@ #include "llvm/ADT/StringSwitch.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace LPCC { enum CondCode { ICC_T = 0, // true @@ -95,6 +95,6 @@ .Default(LPCC::UNKNOWN); } } // namespace LPCC -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAICONDCODE_H Index: llvm/lib/Target/Lanai/LanaiFrameLowering.h =================================================================== --- llvm/lib/Target/Lanai/LanaiFrameLowering.h +++ llvm/lib/Target/Lanai/LanaiFrameLowering.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class BitVector; class LanaiSubtarget; @@ -50,6 +50,6 @@ RegScavenger *RS = nullptr) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIFRAMELOWERING_H Index: llvm/lib/Target/Lanai/LanaiISelLowering.h =================================================================== --- llvm/lib/Target/Lanai/LanaiISelLowering.h +++ llvm/lib/Target/Lanai/LanaiISelLowering.h @@ -19,7 +19,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace LanaiISD { enum { FIRST_NUMBER = ISD::BUILTIN_OP_END, @@ -147,6 +147,6 @@ const LanaiRegisterInfo *TRI; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIISELLOWERING_H Index: llvm/lib/Target/Lanai/LanaiInstrInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -20,7 +20,7 @@ #define GET_INSTRINFO_HEADER #include "LanaiGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiInstrInfo : public LanaiGenInstrInfo { const LanaiRegisterInfo RegisterInfo; @@ -184,6 +184,6 @@ } } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H Index: llvm/lib/Target/Lanai/LanaiMCInstLower.h =================================================================== --- llvm/lib/Target/Lanai/LanaiMCInstLower.h +++ llvm/lib/Target/Lanai/LanaiMCInstLower.h @@ -11,7 +11,7 @@ #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class AsmPrinter; class MCContext; class MCInst; @@ -39,6 +39,6 @@ MCSymbol *GetJumpTableSymbol(const MachineOperand &MO) const; MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIMCINSTLOWER_H Index: llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h +++ llvm/lib/Target/Lanai/LanaiMachineFunctionInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // LanaiMachineFunctionInfo - This class is derived from MachineFunction and // contains private Lanai target-specific information for each MachineFunction. @@ -48,6 +48,6 @@ void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp =================================================================== --- llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ llvm/lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -45,9 +45,9 @@ llvm::cl::desc("Do not combine ALU and memory operators"), llvm::cl::Hidden); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeLanaiMemAluCombinerPass(PassRegistry &); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { typedef MachineBasicBlock::iterator MbbIterator; Index: llvm/lib/Target/Lanai/LanaiRegisterInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiRegisterInfo.h +++ llvm/lib/Target/Lanai/LanaiRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "LanaiGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct LanaiRegisterInfo : public LanaiGenRegisterInfo { LanaiRegisterInfo(); @@ -47,6 +47,6 @@ int getDwarfRegNum(unsigned RegNum, bool IsEH) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAIREGISTERINFO_H Index: llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h +++ llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiSelectionDAGInfo : public SelectionDAGTargetInfo { public: @@ -30,6 +30,6 @@ MachinePointerInfo SrcPtrInfo) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAISELECTIONDAGINFO_H Index: llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp =================================================================== --- llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp +++ llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp @@ -16,7 +16,7 @@ #define DEBUG_TYPE "lanai-selectiondag-info" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { SDValue LanaiSelectionDAGInfo::EmitTargetCodeForMemcpy( SelectionDAG & /*DAG*/, const SDLoc & /*dl*/, SDValue /*Chain*/, @@ -31,4 +31,4 @@ return SDValue(); } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Lanai/LanaiSubtarget.h =================================================================== --- llvm/lib/Target/Lanai/LanaiSubtarget.h +++ llvm/lib/Target/Lanai/LanaiSubtarget.h @@ -24,7 +24,7 @@ #define GET_SUBTARGETINFO_HEADER #include "LanaiGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiSubtarget : public LanaiGenSubtargetInfo { public: @@ -69,6 +69,6 @@ LanaiTargetLowering TLInfo; LanaiSelectionDAGInfo TSInfo; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAISUBTARGET_H Index: llvm/lib/Target/Lanai/LanaiTargetMachine.h =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.h +++ llvm/lib/Target/Lanai/LanaiTargetMachine.h @@ -19,7 +19,7 @@ #include "LanaiSubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiTargetMachine : public LLVMTargetMachine { LanaiSubtarget Subtarget; @@ -51,6 +51,6 @@ return false; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAITARGETMACHINE_H Index: llvm/lib/Target/Lanai/LanaiTargetMachine.cpp =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetMachine.cpp +++ llvm/lib/Target/Lanai/LanaiTargetMachine.cpp @@ -26,9 +26,9 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeLanaiMemAluCombinerPass(PassRegistry &); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeLanaiTarget() { // Register the target. Index: llvm/lib/Target/Lanai/LanaiTargetObjectFile.h =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetObjectFile.h +++ llvm/lib/Target/Lanai/LanaiTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiTargetObjectFile : public TargetLoweringObjectFileELF { MCSection *SmallDataSection; MCSection *SmallBSSSection; @@ -39,6 +39,6 @@ const Constant *C, Align &Alignment) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAITARGETOBJECTFILE_H Index: llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h =================================================================== --- llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -24,7 +24,7 @@ #include "llvm/CodeGen/TargetLowering.h" #include "llvm/Support/MathExtras.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; typedef TargetTransformInfo TTI; @@ -109,6 +109,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_LANAITARGETTRANSFORMINFO_H Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiBaseInfo.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiBaseInfo.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiBaseInfo.h @@ -19,7 +19,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // LanaiII - This namespace holds all of the target specific flags that // instruction info tracks. @@ -114,5 +114,5 @@ llvm_unreachable("Unknown register number!"); } } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIBASEINFO_H Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiFixupKinds.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiFixupKinds.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Lanai { // Although most of the current fixup types reflect a unique relocation // one can have multiple fixup types for a given relocation and thus need @@ -37,6 +37,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // namespace Lanai -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIFIXUPKINDS_H Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.h @@ -16,7 +16,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiInstPrinter : public MCInstPrinter { public: @@ -62,6 +62,6 @@ StringRef Opcode, int AddOffset); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIINSTPRINTER_H Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class LanaiMCAsmInfo : public MCAsmInfoELF { @@ -26,6 +26,6 @@ const MCTargetOptions &Options); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_MCTARGETDESC_LANAIMCASMINFO_H Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCCodeEmitter.cpp @@ -32,7 +32,7 @@ STATISTIC(MCNumEmitted, "Number of MC instructions emitted"); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace { @@ -300,7 +300,7 @@ #include "LanaiGenMCCodeEmitter.inc" -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY llvm::MCCodeEmitter * llvm::createLanaiMCCodeEmitter(const MCInstrInfo &InstrInfo, Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCExpr.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCValue.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LanaiMCExpr : public MCTargetExpr { public: @@ -50,6 +50,6 @@ return E->getKind() == MCExpr::Target; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h =================================================================== --- llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h +++ llvm/lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCTargetOptions.h" #include "llvm/Support/DataTypes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -35,7 +35,7 @@ const MCTargetOptions &Options); std::unique_ptr createLanaiELFObjectWriter(uint8_t OSABI); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for Lanai registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.h =================================================================== --- llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.h +++ llvm/lib/Target/Lanai/TargetInfo/LanaiTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_LANAI_TARGETINFO_LANAITARGETINFO_H #define LLVM_LIB_TARGET_LANAI_TARGETINFO_LANAITARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheLanaiTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_LANAI_TARGETINFO_LANAITARGETINFO_H Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430ELFStreamer.cpp @@ -20,7 +20,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MSP430TargetELFStreamer : public MCTargetStreamer { public: @@ -77,4 +77,4 @@ return nullptr; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430FixupKinds.h @@ -13,7 +13,7 @@ #undef MSP430 -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace MSP430 { // This table must be in the same order of @@ -47,6 +47,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // end namespace MSP430 -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430InstPrinter.h @@ -15,24 +15,24 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { - class MSP430InstPrinter : public MCInstPrinter { - public: - MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, - const MCRegisterInfo &MRI) +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MSP430InstPrinter : public MCInstPrinter { +public: + MSP430InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) : MCInstPrinter(MAI, MII, MRI) {} - void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, - const MCSubtargetInfo &STI, raw_ostream &O) override; + void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, + const MCSubtargetInfo &STI, raw_ostream &O) override; - // Autogenerated by tblgen. - std::pair getMnemonic(const MCInst *MI) override; - void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); - bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &O); - void printCustomAliasOperand(const MCInst *MI, uint64_t Address, - unsigned OpIdx, unsigned PrintMethodIdx, - raw_ostream &O); - static const char *getRegisterName(unsigned RegNo); + // Autogenerated by tblgen. + std::pair getMnemonic(const MCInst *MI) override; + void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &O); + void printCustomAliasOperand(const MCInst *MI, uint64_t Address, + unsigned OpIdx, unsigned PrintMethodIdx, + raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); private: void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, @@ -44,8 +44,7 @@ void printPostIndRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printCCOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); - - }; -} +}; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class MSP430MCAsmInfo : public MCAsmInfoELF { @@ -25,6 +25,6 @@ explicit MSP430MCAsmInfo(const Triple &TT, const MCTargetOptions &Options); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp @@ -30,7 +30,7 @@ #define DEBUG_TYPE "mccodeemitter" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MSP430MCCodeEmitter : public MCCodeEmitter { MCContext &Ctx; @@ -207,4 +207,4 @@ #include "MSP430GenMCCodeEmitter.inc" -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h =================================================================== --- llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h +++ llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.h @@ -13,10 +13,12 @@ #ifndef LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H #define LLVM_LIB_TARGET_MSP430_MCTARGETDESC_MSP430MCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; class MCAsmBackend; class MCCodeEmitter; @@ -45,7 +47,7 @@ std::unique_ptr createMSP430ELFObjectWriter(uint8_t OSABI); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for MSP430 registers. // This defines a mapping from register name to register number. Index: llvm/lib/Target/MSP430/MSP430.h =================================================================== --- llvm/lib/Target/MSP430/MSP430.h +++ llvm/lib/Target/MSP430/MSP430.h @@ -33,15 +33,15 @@ }; } -namespace llvm { - class MSP430TargetMachine; - class FunctionPass; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MSP430TargetMachine; +class FunctionPass; - FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, - CodeGenOpt::Level OptLevel); +FunctionPass *createMSP430ISelDag(MSP430TargetMachine &TM, + CodeGenOpt::Level OptLevel); - FunctionPass *createMSP430BranchSelectionPass(); +FunctionPass *createMSP430BranchSelectionPass(); -} // end namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430FrameLowering.h =================================================================== --- llvm/lib/Target/MSP430/MSP430FrameLowering.h +++ llvm/lib/Target/MSP430/MSP430FrameLowering.h @@ -16,7 +16,7 @@ #include "MSP430.h" #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MSP430FrameLowering : public TargetFrameLowering { protected: @@ -50,6 +50,6 @@ RegScavenger *RS = nullptr) const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430ISelLowering.h =================================================================== --- llvm/lib/Target/MSP430/MSP430ISelLowering.h +++ llvm/lib/Target/MSP430/MSP430ISelLowering.h @@ -18,56 +18,57 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { - namespace MSP430ISD { - enum NodeType : unsigned { - FIRST_NUMBER = ISD::BUILTIN_OP_END, +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace MSP430ISD { +enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, - /// Return with a flag operand. Operand 0 is the chain operand. - RET_FLAG, + /// Return with a flag operand. Operand 0 is the chain operand. + RET_FLAG, - /// Same as RET_FLAG, but used for returning from ISRs. - RETI_FLAG, + /// Same as RET_FLAG, but used for returning from ISRs. + RETI_FLAG, - /// Y = R{R,L}A X, rotate right (left) arithmetically - RRA, RLA, + /// Y = R{R,L}A X, rotate right (left) arithmetically + RRA, + RLA, - /// Y = RRC X, rotate right via carry - RRC, + /// Y = RRC X, rotate right via carry + RRC, - /// Rotate right via carry, carry gets cleared beforehand by clrc - RRCL, + /// Rotate right via carry, carry gets cleared beforehand by clrc + RRCL, - /// CALL - These operations represent an abstract call - /// instruction, which includes a bunch of information. - CALL, + /// CALL - These operations represent an abstract call + /// instruction, which includes a bunch of information. + CALL, - /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, - /// and TargetGlobalAddress. - Wrapper, + /// Wrapper - A wrapper node for TargetConstantPool, TargetExternalSymbol, + /// and TargetGlobalAddress. + Wrapper, - /// CMP - Compare instruction. - CMP, + /// CMP - Compare instruction. + CMP, - /// SetCC - Operand 0 is condition code, and operand 1 is the flag - /// operand produced by a CMP instruction. - SETCC, + /// SetCC - Operand 0 is condition code, and operand 1 is the flag + /// operand produced by a CMP instruction. + SETCC, - /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1 - /// is the block to branch if condition is true, operand 2 is the - /// condition code, and operand 3 is the flag operand produced by a CMP - /// instruction. - BR_CC, + /// MSP430 conditional branches. Operand 0 is the chain operand, operand 1 + /// is the block to branch if condition is true, operand 2 is the + /// condition code, and operand 3 is the flag operand produced by a CMP + /// instruction. + BR_CC, - /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 - /// is condition code and operand 4 is flag operand. - SELECT_CC, + /// SELECT_CC - Operand 0 and operand 1 are selection variable, operand 3 + /// is condition code and operand 4 is flag operand. + SELECT_CC, - /// DADD - Decimal addition with carry - /// TODO Nothing generates a node of this type yet. - DADD, - }; - } + /// DADD - Decimal addition with carry + /// TODO Nothing generates a node of this type yet. + DADD, +}; +} class MSP430Subtarget; class MSP430TargetLowering : public TargetLowering { @@ -185,6 +186,6 @@ ISD::MemIndexedMode &AM, SelectionDAG &DAG) const override; }; -} // namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430InstrInfo.h =================================================================== --- llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "MSP430GenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MSP430Subtarget; @@ -75,6 +75,6 @@ } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430MCInstLower.h =================================================================== --- llvm/lib/Target/MSP430/MSP430MCInstLower.h +++ llvm/lib/Target/MSP430/MSP430MCInstLower.h @@ -11,17 +11,17 @@ #include "llvm/Support/Compiler.h" -namespace llvm { - class AsmPrinter; - class MCContext; - class MCInst; - class MCOperand; - class MCSymbol; - class MachineInstr; - class MachineOperand; - - /// MSP430MCInstLower - This class is used to lower an MachineInstr - /// into an MCInst. +namespace llvm LLVM_LIBRARY_VISIBILITY { +class AsmPrinter; +class MCContext; +class MCInst; +class MCOperand; +class MCSymbol; +class MachineInstr; +class MachineOperand; + +/// MSP430MCInstLower - This class is used to lower an MachineInstr +/// into an MCInst. class LLVM_LIBRARY_VISIBILITY MSP430MCInstLower { MCContext &Ctx; @@ -40,6 +40,6 @@ MCSymbol *GetBlockAddressSymbol(const MachineOperand &MO) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h +++ llvm/lib/Target/MSP430/MSP430MachineFunctionInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// MSP430MachineFunctionInfo - This class is derived from MachineFunction and /// contains private MSP430 target-specific information for each MachineFunction. @@ -56,6 +56,6 @@ void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430RegisterInfo.h =================================================================== --- llvm/lib/Target/MSP430/MSP430RegisterInfo.h +++ llvm/lib/Target/MSP430/MSP430RegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "MSP430GenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct MSP430RegisterInfo : public MSP430GenRegisterInfo { public: @@ -40,6 +40,6 @@ Register getFrameRegister(const MachineFunction &MF) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/MSP430Subtarget.h =================================================================== --- llvm/lib/Target/MSP430/MSP430Subtarget.h +++ llvm/lib/Target/MSP430/MSP430Subtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "MSP430GenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class MSP430Subtarget : public MSP430GenSubtargetInfo { @@ -74,6 +74,6 @@ return &TSInfo; } }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_TARGET_MSP430_SUBTARGET_H Index: llvm/lib/Target/MSP430/MSP430TargetMachine.h =================================================================== --- llvm/lib/Target/MSP430/MSP430TargetMachine.h +++ llvm/lib/Target/MSP430/MSP430TargetMachine.h @@ -17,7 +17,7 @@ #include "MSP430Subtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; /// MSP430TargetMachine @@ -43,6 +43,6 @@ } }; // MSP430TargetMachine. -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.h =================================================================== --- llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.h +++ llvm/lib/Target/MSP430/TargetInfo/MSP430TargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_MSP430_TARGETINFO_MSP430TARGETINFO_H #define LLVM_LIB_TARGET_MSP430_TARGETINFO_MSP430TARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheMSP430Target(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MSP430_TARGETINFO_MSP430TARGETINFO_H Index: llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -61,11 +61,11 @@ #define DEBUG_TYPE "mips-asm-parser" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInstrInfo; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY extern cl::opt EmitJalrReloc; @@ -1745,11 +1745,11 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { extern const MCInstrDesc MipsInsts[]; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static const MCInstrDesc &getInstDesc(unsigned Opcode) { return MipsInsts[Opcode]; Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h @@ -14,7 +14,7 @@ #include "llvm/Support/MipsABIFlags.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCStreamer; @@ -203,6 +203,6 @@ MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp +++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp @@ -53,7 +53,7 @@ return (uint8_t)CPR1Size; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) { // Write out a Elf_Internal_ABIFlags_v0 struct @@ -71,4 +71,4 @@ return OS; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -13,7 +13,7 @@ #include "llvm/IR/CallingConv.h" #include "llvm/MC/MCRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template class ArrayRef; class MCTargetOptions; @@ -75,6 +75,6 @@ unsigned GetEhDataReg(unsigned I) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -18,7 +18,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/MC/MCAsmBackend.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAssembler; struct MCFixupKindInfo; @@ -71,6 +71,6 @@ bool isMicroMips(const MCSymbol *Sym) const override; }; // class MipsAsmBackend -} // namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h @@ -20,7 +20,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// MipsII - This namespace holds all of the target specific flags that /// instruction info tracks. @@ -135,6 +135,6 @@ OPERAND_LAST_MIPS_MEM_IMM = OPERAND_MEM_SIMM9 }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h @@ -19,7 +19,7 @@ #include "llvm/MC/MCELFStreamer.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -77,6 +77,6 @@ std::unique_ptr OW, std::unique_ptr Emitter, bool RelaxAll); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSELFSTREAMER_H Index: llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Mips { // Although most of the current fixup types reflect a unique relocation // one can have multiple fixup types for a given relocation and thus need @@ -227,7 +227,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // namespace Mips -} // namespace llvm - +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsInstPrinter.h @@ -14,7 +14,7 @@ #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // These enumeration declarations were originally in MipsInstrInfo.h but // had to be moved here to avoid circular dependencies between // LLVMMipsCodeGen and LLVMMipsAsmPrinter. @@ -113,6 +113,6 @@ void printSaveRestore(const MCInst *MI, raw_ostream &O); void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class MipsMCAsmInfo : public MCAsmInfoELF { @@ -26,6 +26,6 @@ const MCTargetOptions &Options); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -14,9 +14,11 @@ #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H #include "llvm/MC/MCCodeEmitter.h" +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class MCExpr; @@ -270,6 +272,6 @@ void LowerCompactBranch(MCInst& Inst) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -39,7 +39,7 @@ #include "MipsGenInstrInfo.inc" #undef GET_INSTRMAP_INFO -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, @@ -53,7 +53,7 @@ return new MipsMCCodeEmitter(MCII, Ctx, true); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // If the D instruction has a shift amount that is greater // than 31 (checked in calling routine), lower it to a D32 instruction Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h @@ -13,7 +13,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCValue.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsMCExpr : public MCTargetExpr { public: @@ -88,6 +88,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCEXPR_H Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCELFStreamer.h" #include "llvm/Support/Alignment.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // NaCl MIPS sandbox's instruction bundle size. static const Align MIPS_NACL_BUNDLE_ALIGN = Align(16); @@ -27,6 +27,6 @@ std::unique_ptr OW, std::unique_ptr Emitter, bool RelaxAll); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -13,11 +13,12 @@ #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -48,7 +49,7 @@ StringRef selectMipsCPU(const Triple &TT, StringRef CPU); } -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for Mips registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp =================================================================== --- llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ llvm/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -205,7 +205,7 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, bool *IsStore) { @@ -275,4 +275,4 @@ return S; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/Mips.h =================================================================== --- llvm/lib/Target/Mips/Mips.h +++ llvm/lib/Target/Mips/Mips.h @@ -17,36 +17,36 @@ #include "MCTargetDesc/MipsMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { - class MipsTargetMachine; - class ModulePass; - class FunctionPass; - class MipsRegisterBankInfo; - class MipsSubtarget; - class MipsTargetMachine; - class InstructionSelector; - class PassRegistry; - - ModulePass *createMipsOs16Pass(); - ModulePass *createMips16HardFloatPass(); - - FunctionPass *createMipsModuleISelDagPass(); - FunctionPass *createMipsOptimizePICCallPass(); - FunctionPass *createMipsDelaySlotFillerPass(); - FunctionPass *createMipsBranchExpansion(); - FunctionPass *createMipsConstantIslandPass(); - FunctionPass *createMicroMipsSizeReducePass(); - FunctionPass *createMipsExpandPseudoPass(); - FunctionPass *createMipsPreLegalizeCombiner(); - - InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, - MipsSubtarget &, - MipsRegisterBankInfo &); - - void initializeMipsDelaySlotFillerPass(PassRegistry &); - void initializeMipsBranchExpansionPass(PassRegistry &); - void initializeMicroMipsSizeReducePass(PassRegistry &); - void initializeMipsPreLegalizerCombinerPass(PassRegistry&); -} // end namespace llvm; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MipsTargetMachine; +class ModulePass; +class FunctionPass; +class MipsRegisterBankInfo; +class MipsSubtarget; +class MipsTargetMachine; +class InstructionSelector; +class PassRegistry; + +ModulePass *createMipsOs16Pass(); +ModulePass *createMips16HardFloatPass(); + +FunctionPass *createMipsModuleISelDagPass(); +FunctionPass *createMipsOptimizePICCallPass(); +FunctionPass *createMipsDelaySlotFillerPass(); +FunctionPass *createMipsBranchExpansion(); +FunctionPass *createMipsConstantIslandPass(); +FunctionPass *createMicroMipsSizeReducePass(); +FunctionPass *createMipsExpandPseudoPass(); +FunctionPass *createMipsPreLegalizeCombiner(); + +InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &, + MipsSubtarget &, + MipsRegisterBankInfo &); + +void initializeMipsDelaySlotFillerPass(PassRegistry &); +void initializeMipsBranchExpansionPass(PassRegistry &); +void initializeMicroMipsSizeReducePass(PassRegistry &); +void initializeMipsPreLegalizerCombinerPass(PassRegistry &); +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/Mips16FrameLowering.h =================================================================== --- llvm/lib/Target/Mips/Mips16FrameLowering.h +++ llvm/lib/Target/Mips/Mips16FrameLowering.h @@ -15,7 +15,7 @@ #include "MipsFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Mips16FrameLowering : public MipsFrameLowering { public: explicit Mips16FrameLowering(const MipsSubtarget &STI); @@ -42,6 +42,6 @@ RegScavenger *RS) const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/Mips16HardFloatInfo.h =================================================================== --- llvm/lib/Target/Mips/Mips16HardFloatInfo.h +++ llvm/lib/Target/Mips/Mips16HardFloatInfo.h @@ -15,7 +15,9 @@ #ifndef LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOATINFO_H #define LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOATINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Mips16HardFloatInfo { @@ -44,6 +46,6 @@ extern FuncSignature const *findFuncSignature(const char *name); } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/Mips16HardFloatInfo.cpp =================================================================== --- llvm/lib/Target/Mips/Mips16HardFloatInfo.cpp +++ llvm/lib/Target/Mips/Mips16HardFloatInfo.cpp @@ -14,7 +14,7 @@ #include "Mips16HardFloatInfo.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Mips16HardFloatInfo { @@ -46,4 +46,4 @@ return nullptr; } } -} +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h =================================================================== --- llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h +++ llvm/lib/Target/Mips/Mips16ISelDAGToDAG.h @@ -15,7 +15,7 @@ #include "MipsISelDAGToDAG.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Mips16DAGToDAGISel : public MipsDAGToDAGISel { public: @@ -49,6 +49,6 @@ FunctionPass *createMips16ISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/Mips16ISelLowering.h =================================================================== --- llvm/lib/Target/Mips/Mips16ISelLowering.h +++ llvm/lib/Target/Mips/Mips16ISelLowering.h @@ -15,68 +15,65 @@ #include "MipsISelLowering.h" -namespace llvm { - class Mips16TargetLowering : public MipsTargetLowering { - public: - explicit Mips16TargetLowering(const MipsTargetMachine &TM, - const MipsSubtarget &STI); - - bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, - unsigned Align, - MachineMemOperand::Flags Flags, - bool *Fast) const override; - - MachineBasicBlock * - EmitInstrWithCustomInserter(MachineInstr &MI, - MachineBasicBlock *MBB) const override; - - private: - bool isEligibleForTailCallOptimization( - const CCState &CCInfo, unsigned NextStackOffset, - const MipsFunctionInfo &FI) const override; - - void setMips16HardFloatLibCalls(); - - unsigned int - getMips16HelperFunctionStubNumber(ArgListTy &Args) const; - - const char *getMips16HelperFunction - (Type* RetTy, ArgListTy &Args, bool &needHelper) const; - - void - getOpndList(SmallVectorImpl &Ops, - std::deque< std::pair > &RegsToPass, - bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, - SDValue Chain) const override; - - MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI, - MachineBasicBlock *BB) const; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class Mips16TargetLowering : public MipsTargetLowering { +public: + explicit Mips16TargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); + + bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, + unsigned Align, + MachineMemOperand::Flags Flags, + bool *Fast) const override; + + MachineBasicBlock * + EmitInstrWithCustomInserter(MachineInstr &MI, + MachineBasicBlock *MBB) const override; + +private: + bool + isEligibleForTailCallOptimization(const CCState &CCInfo, + unsigned NextStackOffset, + const MipsFunctionInfo &FI) const override; + + void setMips16HardFloatLibCalls(); - MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, - MachineInstr &MI, - MachineBasicBlock *BB) const; + unsigned int getMips16HelperFunctionStubNumber(ArgListTy &Args) const; + + const char *getMips16HelperFunction(Type *RetTy, ArgListTy &Args, + bool &needHelper) const; + + void getOpndList(SmallVectorImpl &Ops, + std::deque> &RegsToPass, + bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const override; + + MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI, + MachineBasicBlock *BB) const; + + MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, - MachineInstr &MI, - MachineBasicBlock *BB) const; + MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2, MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, - MachineInstr &MI, - MachineBasicBlock *BB) const; + MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc, + MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc, - unsigned CmpiXOpc, bool ImmSigned, - MachineInstr &MI, - MachineBasicBlock *BB) const; + MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc, + unsigned CmpiXOpc, bool ImmSigned, + MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI, - MachineBasicBlock *BB) const; + MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI, + MachineBasicBlock *BB) const; - MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, - MachineInstr &MI, - MachineBasicBlock *BB) const; - }; -} + MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc, + MachineInstr &MI, + MachineBasicBlock *BB) const; +}; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/Mips16InstrInfo.h =================================================================== --- llvm/lib/Target/Mips/Mips16InstrInfo.h +++ llvm/lib/Target/Mips/Mips16InstrInfo.h @@ -19,7 +19,7 @@ #include "llvm/Support/MathExtras.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInstrDesc; class MipsSubtarget; @@ -125,6 +125,6 @@ MachineBasicBlock::iterator I) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H Index: llvm/lib/Target/Mips/Mips16RegisterInfo.h =================================================================== --- llvm/lib/Target/Mips/Mips16RegisterInfo.h +++ llvm/lib/Target/Mips/Mips16RegisterInfo.h @@ -15,7 +15,7 @@ #include "MipsRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Mips16RegisterInfo : public MipsRegisterInfo { public: @@ -41,6 +41,6 @@ int64_t SPOffset) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsAnalyzeImmediate.h =================================================================== --- llvm/lib/Target/Mips/MipsAnalyzeImmediate.h +++ llvm/lib/Target/Mips/MipsAnalyzeImmediate.h @@ -12,55 +12,55 @@ #include "llvm/ADT/SmallVector.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - class MipsAnalyzeImmediate { - public: - struct Inst { - unsigned Opc, ImmOpnd; +class MipsAnalyzeImmediate { +public: + struct Inst { + unsigned Opc, ImmOpnd; - Inst(unsigned Opc, unsigned ImmOpnd); - }; - using InstSeq = SmallVector; + Inst(unsigned Opc, unsigned ImmOpnd); + }; + using InstSeq = SmallVector; - /// Analyze - Get an instruction sequence to load immediate Imm. The last - /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is - /// true; - const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); + /// Analyze - Get an instruction sequence to load immediate Imm. The last + /// instruction in the sequence must be an ADDiu if LastInstrIsADDiu is + /// true; + const InstSeq &Analyze(uint64_t Imm, unsigned Size, bool LastInstrIsADDiu); - private: - using InstSeqLs = SmallVector; +private: + using InstSeqLs = SmallVector; - /// AddInstr - Add I to all instruction sequences in SeqLs. - void AddInstr(InstSeqLs &SeqLs, const Inst &I); + /// AddInstr - Add I to all instruction sequences in SeqLs. + void AddInstr(InstSeqLs &SeqLs, const Inst &I); - /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to - /// load immediate Imm - void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + /// GetInstSeqLsADDiu - Get instruction sequences which end with an ADDiu to + /// load immediate Imm + void GetInstSeqLsADDiu(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLsORi - Get instrutcion sequences which end with an ORi to - /// load immediate Imm - void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + /// GetInstSeqLsORi - Get instrutcion sequences which end with an ORi to + /// load immediate Imm + void GetInstSeqLsORi(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to - /// load immediate Imm - void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to + /// load immediate Imm + void GetInstSeqLsSLL(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// GetInstSeqLs - Get instruction sequences to load immediate Imm. - void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); + /// GetInstSeqLs - Get instruction sequences to load immediate Imm. + void GetInstSeqLs(uint64_t Imm, unsigned RemSize, InstSeqLs &SeqLs); - /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. - void ReplaceADDiuSLLWithLUi(InstSeq &Seq); + /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. + void ReplaceADDiuSLLWithLUi(InstSeq &Seq); - /// GetShortestSeq - Find the shortest instruction sequence in SeqLs and - /// return it in Insts. - void GetShortestSeq(InstSeqLs &SeqLs, InstSeq &Insts); + /// GetShortestSeq - Find the shortest instruction sequence in SeqLs and + /// return it in Insts. + void GetShortestSeq(InstSeqLs &SeqLs, InstSeq &Insts); - unsigned Size; - unsigned ADDiu, ORi, SLL, LUi; - InstSeq Insts; - }; + unsigned Size; + unsigned ADDiu, ORi, SLL, LUi; + InstSeq Insts; +}; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H Index: llvm/lib/Target/Mips/MipsAsmPrinter.h =================================================================== --- llvm/lib/Target/Mips/MipsAsmPrinter.h +++ llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -23,7 +23,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCOperand; class MCSubtargetInfo; @@ -160,6 +160,6 @@ void emitDebugValue(const MCExpr *Value, unsigned Size) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H Index: llvm/lib/Target/Mips/MipsCCState.h =================================================================== --- llvm/lib/Target/Mips/MipsCCState.h +++ llvm/lib/Target/Mips/MipsCCState.h @@ -13,7 +13,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/CallingConvLower.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SDNode; class MipsSubtarget; @@ -161,6 +161,6 @@ bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; } SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsCallLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsCallLowering.h +++ llvm/lib/Target/Mips/MipsCallLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineMemOperand; class MipsTargetLowering; @@ -91,6 +91,6 @@ SmallVectorImpl &SplitArgsOrigIndices) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSCALLLOWERING_H Index: llvm/lib/Target/Mips/MipsFastISel.cpp =================================================================== --- llvm/lib/Target/Mips/MipsFastISel.cpp +++ llvm/lib/Target/Mips/MipsFastISel.cpp @@ -2147,11 +2147,11 @@ Op1IsKill); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) { return new MipsFastISel(funcInfo, libInfo); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/MipsFrameLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsFrameLowering.h +++ llvm/lib/Target/Mips/MipsFrameLowering.h @@ -16,8 +16,8 @@ #include "Mips.h" #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { - class MipsSubtarget; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MipsSubtarget; class MipsFrameLowering : public TargetFrameLowering { protected: @@ -53,6 +53,6 @@ const MipsFrameLowering *createMips16FrameLowering(const MipsSubtarget &ST); const MipsFrameLowering *createMipsSEFrameLowering(const MipsSubtarget &ST); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsISelDAGToDAG.h =================================================================== --- llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -26,7 +26,7 @@ // MipsDAGToDAGISel - MIPS specific code to select MIPS machine // instructions for SelectionDAG operations. //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsDAGToDAGISel : public SelectionDAGISel { public: @@ -145,6 +145,6 @@ unsigned ConstraintID, std::vector &OutOps) override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsISelLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsISelLowering.h +++ llvm/lib/Target/Mips/MipsISelLowering.h @@ -37,7 +37,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Argument; class FastISel; @@ -713,6 +713,6 @@ } // end namespace Mips -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H Index: llvm/lib/Target/Mips/MipsInstrInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsInstrInfo.h +++ llvm/lib/Target/Mips/MipsInstrInfo.h @@ -30,7 +30,7 @@ #define GET_INSTRINFO_HEADER #include "MipsGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstr; class MachineOperand; @@ -192,6 +192,6 @@ const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H Index: llvm/lib/Target/Mips/MipsInstructionSelector.cpp =================================================================== --- llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -931,10 +931,10 @@ return constrainSelectedInstRegOperands(*MI, TII, TRI, RBI); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM, MipsSubtarget &Subtarget, MipsRegisterBankInfo &RBI) { return new MipsInstructionSelector(TM, Subtarget, RBI); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/MipsLegalizerInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsLegalizerInfo.h +++ llvm/lib/Target/Mips/MipsLegalizerInfo.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsSubtarget; @@ -30,5 +30,5 @@ bool legalizeIntrinsic(LegalizerHelper &Helper, MachineInstr &MI) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsMCInstLower.h =================================================================== --- llvm/lib/Target/Mips/MipsMCInstLower.h +++ llvm/lib/Target/Mips/MipsMCInstLower.h @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineInstr; @@ -48,6 +48,6 @@ bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H Index: llvm/lib/Target/Mips/MipsMachineFunction.h =================================================================== --- llvm/lib/Target/Mips/MipsMachineFunction.h +++ llvm/lib/Target/Mips/MipsMachineFunction.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// MipsFunctionInfo - This class is derived from MachineFunction private /// Mips target-specific information for each MachineFunction. @@ -123,6 +123,6 @@ int MoveF64ViaSpillFI = -1; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSMACHINEFUNCTION_H Index: llvm/lib/Target/Mips/MipsOptionRecord.h =================================================================== --- llvm/lib/Target/Mips/MipsOptionRecord.h +++ llvm/lib/Target/Mips/MipsOptionRecord.h @@ -24,7 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsELFStreamer; @@ -77,6 +77,6 @@ int64_t ri_gp_value; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H Index: llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp =================================================================== --- llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp +++ llvm/lib/Target/Mips/MipsPreLegalizerCombiner.cpp @@ -110,8 +110,8 @@ "Combine Mips machine instrs before legalization", false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createMipsPreLegalizeCombiner() { return new MipsPreLegalizerCombiner(); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/Mips/MipsRegisterBankInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsRegisterBankInfo.h +++ llvm/lib/Target/Mips/MipsRegisterBankInfo.h @@ -18,7 +18,7 @@ #define GET_REGBANK_DECLARATIONS #include "MipsGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; @@ -226,5 +226,5 @@ }; }; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp =================================================================== --- llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp +++ llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp @@ -22,7 +22,7 @@ #include "MipsGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Mips { enum PartialMappingIdx { PMI_GPR, @@ -69,7 +69,7 @@ }; } // end namespace Mips -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY using namespace llvm; Index: llvm/lib/Target/Mips/MipsRegisterInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsRegisterInfo.h +++ llvm/lib/Target/Mips/MipsRegisterInfo.h @@ -20,7 +20,7 @@ #define GET_REGINFO_HEADER #include "MipsGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterClass; @@ -78,6 +78,6 @@ int64_t SPOffset) const = 0; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H Index: llvm/lib/Target/Mips/MipsSEFrameLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsSEFrameLowering.h +++ llvm/lib/Target/Mips/MipsSEFrameLowering.h @@ -13,7 +13,7 @@ #include "llvm/Support/TypeSize.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineFunction; @@ -48,6 +48,6 @@ MachineBasicBlock &MBB) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H Index: llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h =================================================================== --- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -15,7 +15,7 @@ #include "MipsISelDAGToDAG.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsSEDAGToDAGISel : public MipsDAGToDAGISel { @@ -141,6 +141,6 @@ FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM, CodeGenOpt::Level OptLevel); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsSEISelLowering.h =================================================================== --- llvm/lib/Target/Mips/MipsSEISelLowering.h +++ llvm/lib/Target/Mips/MipsSEISelLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Support/MachineValueType.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineInstr; @@ -138,6 +138,6 @@ bool IsFGR64) const; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H Index: llvm/lib/Target/Mips/MipsSEInstrInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsSEInstrInfo.h +++ llvm/lib/Target/Mips/MipsSEInstrInfo.h @@ -16,7 +16,7 @@ #include "MipsInstrInfo.h" #include "MipsSERegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsSEInstrInfo : public MipsInstrInfo { const MipsSERegisterInfo RI; @@ -124,6 +124,6 @@ MachineBasicBlock::iterator I) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsSERegisterInfo.h =================================================================== --- llvm/lib/Target/Mips/MipsSERegisterInfo.h +++ llvm/lib/Target/Mips/MipsSERegisterInfo.h @@ -16,7 +16,7 @@ #include "MipsRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsSERegisterInfo : public MipsRegisterInfo { public: @@ -34,6 +34,6 @@ int64_t SPOffset) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsSubtarget.h =================================================================== --- llvm/lib/Target/Mips/MipsSubtarget.h +++ llvm/lib/Target/Mips/MipsSubtarget.h @@ -31,7 +31,7 @@ #define GET_SUBTARGETINFO_HEADER #include "MipsGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class MipsTargetMachine; @@ -406,6 +406,6 @@ const RegisterBankInfo *getRegBankInfo() const override; InstructionSelector *getInstructionSelector() const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsTargetMachine.h =================================================================== --- llvm/lib/Target/Mips/MipsTargetMachine.h +++ llvm/lib/Target/Mips/MipsTargetMachine.h @@ -22,7 +22,7 @@ #include "llvm/Target/TargetMachine.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsTargetMachine : public LLVMTargetMachine { bool isLittle; @@ -99,6 +99,6 @@ CodeGenOpt::Level OL, bool JIT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H Index: llvm/lib/Target/Mips/MipsTargetObjectFile.h =================================================================== --- llvm/lib/Target/Mips/MipsTargetObjectFile.h +++ llvm/lib/Target/Mips/MipsTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsTargetMachine; class MipsTargetObjectFile : public TargetLoweringObjectFileELF { MCSection *SmallDataSection; @@ -44,6 +44,6 @@ /// Describe a TLS variable address within debug info. const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/MipsTargetStreamer.h =================================================================== --- llvm/lib/Target/Mips/MipsTargetStreamer.h +++ llvm/lib/Target/Mips/MipsTargetStreamer.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MipsTargetStreamer : public MCTargetStreamer { public: @@ -357,5 +357,5 @@ void emitMipsAbiFlags(); }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.h =================================================================== --- llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.h +++ llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_MIPS_TARGETINFO_MIPSTARGETINFO_H #define LLVM_LIB_TARGET_MIPS_TARGETINFO_MIPSTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -18,6 +20,6 @@ Target &getTheMips64Target(); Target &getTheMips64elTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_MIPS_TARGETINFO_MIPSTARGETINFO_H Index: llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h =================================================================== --- llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h +++ llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXBaseInfo.h @@ -16,7 +16,9 @@ #ifndef LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXBASEINFO_H #define LLVM_LIB_TARGET_NVPTX_MCTARGETDESC_NVPTXBASEINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { enum AddressSpace { ADDRESS_SPACE_GENERIC = 0, @@ -41,5 +43,5 @@ }; } // namespace NVPTXII -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h =================================================================== --- llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h +++ llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCSubtargetInfo; @@ -49,6 +49,6 @@ raw_ostream &O, const char *Modifier = nullptr); }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h =================================================================== --- llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h +++ llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class NVPTXMCAsmInfo : public MCAsmInfo { @@ -36,6 +36,6 @@ return true; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXTargetStreamer.h =================================================================== --- llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXTargetStreamer.h +++ llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXTargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCSection; /// Implments NVPTX-specific streamer. @@ -50,6 +50,6 @@ void emitRawBytes(StringRef Data) override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/ManagedStringPool.h =================================================================== --- llvm/lib/Target/NVPTX/ManagedStringPool.h +++ llvm/lib/Target/NVPTX/ManagedStringPool.h @@ -17,7 +17,7 @@ #include "llvm/ADT/SmallVector.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// ManagedStringPool - The strings allocated from a managed string pool are /// owned by the string pool and will be deleted together with the managed @@ -43,6 +43,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_NVPTX_MANAGEDSTRINGPOOL_H Index: llvm/lib/Target/NVPTX/NVPTX.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTX.h +++ llvm/lib/Target/NVPTX/NVPTX.h @@ -18,7 +18,7 @@ #include "llvm/Pass.h" #include "llvm/Support/CodeGen.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXTargetMachine; class FunctionPass; class MachineFunctionPass; @@ -172,7 +172,7 @@ }; } } -} // end namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for NVPTX registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.h +++ llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.h @@ -13,10 +13,12 @@ #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXALLOCAHOISTING_H #define LLVM_LIB_TARGET_NVPTX_NVPTXALLOCAHOISTING_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; extern FunctionPass *createAllocaHoisting(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp +++ llvm/lib/Target/NVPTX/NVPTXAllocaHoisting.cpp @@ -57,7 +57,7 @@ char NVPTXAllocaHoisting::ID = 0; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXAllocaHoistingPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h +++ llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h @@ -54,7 +54,7 @@ // A better approach is to clone the MCAsmStreamer to a MCPTXAsmStreamer // (subclass of MCStreamer). -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCOperand; @@ -306,6 +306,6 @@ const MCSymbol *getFunctionFrameSymbol() const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_NVPTX_NVPTXASMPRINTER_H Index: llvm/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp +++ llvm/lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp @@ -42,7 +42,7 @@ char NVPTXAssignValidGlobalNames::ID = 0; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXFrameLowering.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXFrameLowering.h +++ llvm/lib/Target/NVPTX/NVPTXFrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXFrameLowering : public TargetFrameLowering { public: @@ -34,6 +34,6 @@ DwarfFrameBase getDwarfFrameBase(const MachineFunction &MF) const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp +++ llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp @@ -28,7 +28,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeGenericToNVVMPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h +++ llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h @@ -22,7 +22,7 @@ #include "llvm/IR/Intrinsics.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel { const NVPTXTargetMachine &TM; @@ -99,6 +99,6 @@ static unsigned GetConvertOpcode(MVT DestTy, MVT SrcTy, bool IsSigned); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXISelLowering.h +++ llvm/lib/Target/NVPTX/NVPTXISelLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace NVPTXISD { enum NodeType : unsigned { // Start the numbering from where ISD NodeType finishes. @@ -582,6 +582,6 @@ Align getArgumentAlignment(SDValue Callee, const CallBase *CB, Type *Ty, unsigned Idx, const DataLayout &DL) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXInstrInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -20,7 +20,7 @@ #define GET_INSTRINFO_HEADER #include "NVPTXGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXInstrInfo : public NVPTXGenInstrInfo { const NVPTXRegisterInfo RegInfo; @@ -65,6 +65,6 @@ int *BytesAdded = nullptr) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.h +++ llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.h @@ -14,10 +14,12 @@ #ifndef LLVM_LIB_TARGET_NVPTX_NVPTXLOWERAGGRCOPIES_H #define LLVM_LIB_TARGET_NVPTX_NVPTXLOWERAGGRCOPIES_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; FunctionPass *createLowerAggrCopies(); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp +++ llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp @@ -139,7 +139,7 @@ } // namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXLowerAggrCopiesPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp +++ llvm/lib/Target/NVPTX/NVPTXLowerAlloca.cpp @@ -36,7 +36,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXLowerAllocaPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp +++ llvm/lib/Target/NVPTX/NVPTXLowerArgs.cpp @@ -101,7 +101,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXLowerArgsPass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXMCExpr.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXMCExpr.h +++ llvm/lib/Target/NVPTX/NVPTXMCExpr.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCExpr.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXFloatMCExpr : public MCTargetExpr { public: @@ -125,6 +125,6 @@ return E->getKind() == MCExpr::Target; } }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h +++ llvm/lib/Target/NVPTX/NVPTXMachineFunctionInfo.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXMachineFunctionInfo : public MachineFunctionInfo { private: /// Stores a mapping from index to symbol name for removing image handles @@ -45,6 +45,6 @@ return ImageHandleList[Idx].c_str(); } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXPeephole.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXPeephole.cpp +++ llvm/lib/Target/NVPTX/NVPTXPeephole.cpp @@ -42,7 +42,7 @@ #define DEBUG_TYPE "nvptx-peephole" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXPeepholePass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp +++ llvm/lib/Target/NVPTX/NVPTXProxyRegErasure.cpp @@ -27,7 +27,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVPTXProxyRegErasurePass(PassRegistry &); } Index: llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h +++ llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h @@ -20,7 +20,7 @@ #define GET_REGINFO_HEADER #include "NVPTXGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXRegisterInfo : public NVPTXGenRegisterInfo { private: // Hold Strings that can be free'd all together with NVPTXRegisterInfo @@ -59,6 +59,6 @@ std::string getNVPTXRegClassName(const TargetRegisterClass *RC); std::string getNVPTXRegClassStr(const TargetRegisterClass *RC); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp +++ llvm/lib/Target/NVPTX/NVPTXRegisterInfo.cpp @@ -24,7 +24,7 @@ #define DEBUG_TYPE "nvptx-reg-info" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { if (RC == &NVPTX::Float32RegsRegClass) return ".f32"; @@ -90,7 +90,7 @@ return "!Special!"; return "INTERNAL"; } -} +} // namespace LLVM_LIBRARY_VISIBILITY NVPTXRegisterInfo::NVPTXRegisterInfo() : NVPTXGenRegisterInfo(0) {} Index: llvm/lib/Target/NVPTX/NVPTXSubtarget.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXSubtarget.h +++ llvm/lib/Target/NVPTX/NVPTXSubtarget.h @@ -26,7 +26,7 @@ #define GET_SUBTARGETINFO_HEADER #include "NVPTXGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXSubtarget : public NVPTXGenSubtargetInfo { virtual void anchor(); @@ -86,6 +86,6 @@ void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.h +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.h @@ -17,7 +17,7 @@ #include "NVPTXSubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// NVPTXTargetMachine /// @@ -90,6 +90,6 @@ CodeGenOpt::Level OL, bool JIT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp +++ llvm/lib/Target/NVPTX/NVPTXTargetMachine.cpp @@ -59,7 +59,7 @@ "Use 32-bit pointers for accessing const/local/shared address spaces."), cl::init(false), cl::Hidden); -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void initializeNVVMIntrRangePass(PassRegistry&); void initializeNVVMReflectPass(PassRegistry&); @@ -71,7 +71,7 @@ void initializeNVPTXLowerAllocaPass(PassRegistry &); void initializeNVPTXProxyRegErasurePass(PassRegistry &); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeNVPTXTarget() { // Register the target. Index: llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h +++ llvm/lib/Target/NVPTX/NVPTXTargetObjectFile.h @@ -13,7 +13,7 @@ #include "llvm/MC/SectionKind.h" #include "llvm/Target/TargetLoweringObjectFile.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXTargetObjectFile : public TargetLoweringObjectFile { public: @@ -40,6 +40,6 @@ const TargetMachine &TM) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_NVPTX_NVPTXTARGETOBJECTFILE_H Index: llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h +++ llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -22,7 +22,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class NVPTXTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -120,6 +120,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXUtilities.h =================================================================== --- llvm/lib/Target/NVPTX/NVPTXUtilities.h +++ llvm/lib/Target/NVPTX/NVPTXUtilities.h @@ -22,7 +22,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void clearAnnotationCache(const Module *); @@ -59,6 +59,6 @@ bool getAlign(const Function &, unsigned index, unsigned &); bool getAlign(const CallInst &, unsigned index, unsigned &); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/NVPTX/NVPTXUtilities.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVPTXUtilities.cpp +++ llvm/lib/Target/NVPTX/NVPTXUtilities.cpp @@ -27,7 +27,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace { typedef std::map > key_val_pair_t; @@ -315,4 +315,4 @@ return false; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/NVPTX/NVVMIntrRange.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVVMIntrRange.cpp +++ llvm/lib/Target/NVPTX/NVVMIntrRange.cpp @@ -24,7 +24,9 @@ #define DEBUG_TYPE "nvvm-intr-range" -namespace llvm { void initializeNVVMIntrRangePass(PassRegistry &); } +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeNVVMIntrRangePass(PassRegistry &); +} // Add !range metadata based on limits of given SM variant. static cl::opt NVVMIntrRangeSM("nvvm-intr-range-sm", cl::init(20), Index: llvm/lib/Target/NVPTX/NVVMReflect.cpp =================================================================== --- llvm/lib/Target/NVPTX/NVVMReflect.cpp +++ llvm/lib/Target/NVPTX/NVVMReflect.cpp @@ -45,7 +45,9 @@ #define DEBUG_TYPE "nvptx-reflect" -namespace llvm { void initializeNVVMReflectPass(PassRegistry &); } +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeNVVMReflectPass(PassRegistry &); +} namespace { class NVVMReflect : public FunctionPass { Index: llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.h =================================================================== --- llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.h +++ llvm/lib/Target/NVPTX/TargetInfo/NVPTXTargetInfo.h @@ -9,13 +9,15 @@ #ifndef LLVM_LIB_TARGET_NVPTX_TARGETINFO_NVPTXTARGETINFO_H #define LLVM_LIB_TARGET_NVPTX_TARGETINFO_NVPTXTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheNVPTXTarget32(); Target &getTheNVPTXTarget64(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_NVPTX_TARGETINFO_NVPTXTARGETINFO_H Index: llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h =================================================================== --- llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h +++ llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/IR/CallingConv.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCTargetLowering; @@ -35,6 +35,6 @@ bool lowerCall(MachineIRBuilder &MIRBuilder, CallLoweringInfo &Info) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp =================================================================== --- llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp +++ llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp @@ -82,11 +82,11 @@ return false; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { InstructionSelector * createPPCInstructionSelector(const PPCTargetMachine &TM, const PPCSubtarget &Subtarget, const PPCRegisterBankInfo &RBI) { return new PPCInstructionSelector(TM, Subtarget, RBI); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.h =================================================================== --- llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.h +++ llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.h @@ -14,7 +14,7 @@ #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCSubtarget; @@ -24,5 +24,5 @@ public: PPCLegalizerInfo(const PPCSubtarget &ST); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h =================================================================== --- llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h +++ llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.h @@ -21,7 +21,7 @@ #define GET_REGBANK_DECLARATIONS #include "PPCGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; class PPCGenRegisterBankInfo : public RegisterBankInfo { @@ -34,6 +34,6 @@ public: PPCRegisterBankInfo(const TargetRegisterInfo &TRI); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCELFStreamer.h @@ -18,7 +18,7 @@ #include "llvm/MC/MCELFStreamer.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -56,6 +56,6 @@ std::unique_ptr MAB, std::unique_ptr OW, std::unique_ptr Emitter); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_PPC_MCELFSTREAMER_PPCELFSTREAMER_H Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCFixupKinds.h @@ -13,7 +13,7 @@ #undef PPC -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace PPC { enum Fixups { // 24-bit PC relative relocation for direct branches like 'b' and 'bl'. @@ -56,6 +56,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h @@ -16,7 +16,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCInstPrinter : public MCInstPrinter { Triple TT; @@ -104,6 +104,6 @@ void printMemRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCAsmInfoELF.h" #include "llvm/MC/MCAsmInfoXCOFF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class PPCELFMCAsmInfo : public MCAsmInfoELF { @@ -33,6 +33,6 @@ explicit PPCXCOFFMCAsmInfo(bool is64Bit, const Triple &); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h @@ -20,7 +20,7 @@ #include "llvm/MC/MCContext.h" #include "llvm/MC/MCInst.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCMCCodeEmitter : public MCCodeEmitter { const MCInstrInfo &MCII; @@ -126,6 +126,6 @@ const FeatureBitset &AvailableFeatures) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_PPC_MCCODEEMITTER_PPCCODEEMITTER_H Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCExpr.h @@ -13,7 +13,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCValue.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCMCExpr : public MCTargetExpr { public: @@ -88,6 +88,6 @@ return E->getKind() == MCExpr::Target; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -21,7 +21,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -103,7 +103,7 @@ return false; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Generated files will use "namespace PPC". To avoid symbol clash, // undefine PPC here. PPC may be predefined on some hosts. Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h =================================================================== --- llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h +++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCPredicates.h @@ -13,6 +13,8 @@ #ifndef LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H #define LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCPREDICATES_H +#include "llvm/Support/Compiler.h" + // GCC #defines PPC on Linux but we use it as our namespace name #undef PPC @@ -20,7 +22,7 @@ // undefine PPC here. PPC may be predefined on some hosts. #undef PPC -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace PPC { /// Predicate - These are "(BI << 5) | BO" for various predicates. enum Predicate { @@ -89,6 +91,6 @@ (Hint & BR_HINT_MASK)); } } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPC.h =================================================================== --- llvm/lib/Target/PowerPC/PPC.h +++ llvm/lib/Target/PowerPC/PPC.h @@ -15,11 +15,12 @@ #define LLVM_LIB_TARGET_POWERPC_PPC_H #include "llvm/Support/CodeGen.h" +#include "llvm/Support/Compiler.h" // GCC #defines PPC on Linux but we use it as our namespace name #undef PPC -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCRegisterBankInfo; class PPCSubtarget; class PPCTargetMachine; @@ -163,6 +164,6 @@ }; } // end namespace PPCII -} // end namespace llvm; + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCCCState.h =================================================================== --- llvm/lib/Target/PowerPC/PPCCCState.h +++ llvm/lib/Target/PowerPC/PPCCCState.h @@ -13,7 +13,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/CallingConvLower.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCCCState : public CCState { public: @@ -36,6 +36,6 @@ bool WasOriginalArgPPCF128(unsigned ValNo) { return OriginalArgWasPPCF128[ValNo]; } void clearWasPPCF128() { OriginalArgWasPPCF128.clear(); } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCCallingConv.h =================================================================== --- llvm/lib/Target/PowerPC/PPCCallingConv.h +++ llvm/lib/Target/PowerPC/PPCCallingConv.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/IR/CallingConv.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { bool RetCC_PPC(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, @@ -41,7 +41,7 @@ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCFastISel.cpp +++ llvm/lib/Target/PowerPC/PPCFastISel.cpp @@ -2469,14 +2469,14 @@ Op1, Op1IsKill); } -namespace llvm { - // Create the fast instruction selector for PowerPC64 ELF. - FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo, - const TargetLibraryInfo *LibInfo) { - // Only available on 64-bit ELF for now. - const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget(); - if (Subtarget.is64BitELFABI()) - return new PPCFastISel(FuncInfo, LibInfo); - return nullptr; - } +namespace llvm LLVM_LIBRARY_VISIBILITY { +// Create the fast instruction selector for PowerPC64 ELF. +FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo, + const TargetLibraryInfo *LibInfo) { + // Only available on 64-bit ELF for now. + const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget(); + if (Subtarget.is64BitELFABI()) + return new PPCFastISel(FuncInfo, LibInfo); + return nullptr; } +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/PowerPC/PPCFrameLowering.h =================================================================== --- llvm/lib/Target/PowerPC/PPCFrameLowering.h +++ llvm/lib/Target/PowerPC/PPCFrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCSubtarget; class PPCFrameLowering: public TargetFrameLowering { @@ -170,6 +170,6 @@ bool canUseAsPrologue(const MachineBasicBlock &MBB) const override; bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.h =================================================================== --- llvm/lib/Target/PowerPC/PPCHazardRecognizers.h +++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" #include "llvm/CodeGen/SelectionDAGNodes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// PPCDispatchGroupSBHazardRecognizer - This class implements a scoreboard-based /// hazard recognizer for PPC ooo processors with dispatch-group hazards. @@ -95,7 +95,7 @@ const Value *LoadValue) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -78,7 +78,11 @@ } // FIXME: Remove this when we don't need this: -namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } } +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace PPC { +extern int getNonRecordFormOpcode(uint16_t); +} +} // namespace LLVM_LIBRARY_VISIBILITY // FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific. Index: llvm/lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- llvm/lib/Target/PowerPC/PPCISelLowering.h +++ llvm/lib/Target/PowerPC/PPCISelLowering.h @@ -31,546 +31,546 @@ #include "llvm/Support/MachineValueType.h" #include -namespace llvm { - - namespace PPCISD { - - // When adding a NEW PPCISD node please add it to the correct position in - // the enum. The order of elements in this enum matters! - // Values that are added after this entry: - // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE - // are considered memory opcodes and are treated differently than entries - // that come before it. For example, ADD or MUL should be placed before - // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come - // after it. - enum NodeType : unsigned { - // Start the numbering where the builtin ops and target ops leave off. - FIRST_NUMBER = ISD::BUILTIN_OP_END, - - /// FSEL - Traditional three-operand fsel node. - /// - FSEL, - - /// XSMAXCDP, XSMINCDP - C-type min/max instructions. - XSMAXCDP, - XSMINCDP, - - /// FCFID - The FCFID instruction, taking an f64 operand and producing - /// and f64 value containing the FP representation of the integer that - /// was temporarily in the f64 operand. - FCFID, - - /// Newer FCFID[US] integer-to-floating-point conversion instructions for - /// unsigned integers and single-precision outputs. - FCFIDU, - FCFIDS, - FCFIDUS, - - /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 - /// operand, producing an f64 value containing the integer representation - /// of that FP value. - FCTIDZ, - FCTIWZ, - - /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for - /// unsigned integers with round toward zero. - FCTIDUZ, - FCTIWUZ, - - /// Floating-point-to-interger conversion instructions - FP_TO_UINT_IN_VSR, - FP_TO_SINT_IN_VSR, - - /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in - /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. - VEXTS, - - /// Reciprocal estimate instructions (unary FP ops). - FRE, - FRSQRTE, - - /// Test instruction for software square root. - FTSQRT, - - /// Square root instruction. - FSQRT, - - /// VPERM - The PPC VPERM Instruction. - /// - VPERM, - - /// XXSPLT - The PPC VSX splat instructions - /// - XXSPLT, - - /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for - /// converting immediate single precision numbers to double precision - /// vector or scalar. - XXSPLTI_SP_TO_DP, - - /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. - /// - XXSPLTI32DX, - - /// VECINSERT - The PPC vector insert instruction - /// - VECINSERT, - - /// VECSHL - The PPC vector shift left instruction - /// - VECSHL, - - /// XXPERMDI - The PPC XXPERMDI instruction - /// - XXPERMDI, - - /// The CMPB instruction (takes two operands of i32 or i64). - CMPB, - - /// Hi/Lo - These represent the high and low 16-bit parts of a global - /// address respectively. These nodes have two operands, the first of - /// which must be a TargetGlobalAddress, and the second of which must be a - /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', - /// though these are usually folded into other nodes. - Hi, - Lo, - - /// The following two target-specific nodes are used for calls through - /// function pointers in the 64-bit SVR4 ABI. - - /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) - /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to - /// compute an allocation on the stack. - DYNALLOC, - - /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to - /// compute an offset from native SP to the address of the most recent - /// dynamic alloca. - DYNAREAOFFSET, - - /// To avoid stack clash, allocation is performed by block and each block is - /// probed. - PROBED_ALLOCA, - - /// The result of the mflr at function entry, used for PIC code. - GlobalBaseReg, - - /// These nodes represent PPC shifts. - /// - /// For scalar types, only the last `n + 1` bits of the shift amounts - /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. - /// for exact behaviors. - /// - /// For vector types, only the last n bits are used. See vsld. - SRL, - SRA, - SHL, - - /// FNMSUB - Negated multiply-subtract instruction. - FNMSUB, - - /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign - /// word and shift left immediate. - EXTSWSLI, - - /// The combination of sra[wd]i and addze used to implemented signed - /// integer division by a power of 2. The first operand is the dividend, - /// and the second is the constant shift amount (representing the - /// divisor). - SRA_ADDZE, - - /// CALL - A direct function call. - /// CALL_NOP is a call with the special NOP which follows 64-bit - /// CALL_NOTOC the caller does not use the TOC. - /// SVR4 calls and 32-bit/64-bit AIX calls. - CALL, - CALL_NOP, - CALL_NOTOC, - - /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a - /// MTCTR instruction. - MTCTR, - - /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a - /// BCTRL instruction. - BCTRL, - - /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl - /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX - /// and 64-bit AIX. - BCTRL_LOAD_TOC, - - /// Return with a flag operand, matched by 'blr' - RET_FLAG, - - /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. - /// This copies the bits corresponding to the specified CRREG into the - /// resultant GPR. Bits corresponding to other CR regs are undefined. - MFOCRF, - - /// Direct move from a VSX register to a GPR - MFVSR, - - /// Direct move from a GPR to a VSX register (algebraic) - MTVSRA, - - /// Direct move from a GPR to a VSX register (zero) - MTVSRZ, - - /// Direct move of 2 consecutive GPR to a VSX register. - BUILD_FP128, - - /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and - /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is - /// unsupported for this target. - /// Merge 2 GPRs to a single SPE register. - BUILD_SPE64, - - /// Extract SPE register component, second argument is high or low. - EXTRACT_SPE, - - /// Extract a subvector from signed integer vector and convert to FP. - /// It is primarily used to convert a (widened) illegal integer vector - /// type to a legal floating point vector type. - /// For example v2i32 -> widened to v4i32 -> v2f64 - SINT_VEC_TO_FP, - - /// Extract a subvector from unsigned integer vector and convert to FP. - /// As with SINT_VEC_TO_FP, used for converting illegal types. - UINT_VEC_TO_FP, - - /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to - /// place the value into the least significant element of the most - /// significant doubleword in the vector. This is not element zero for - /// anything smaller than a doubleword on either endianness. This node has - /// the same semantics as SCALAR_TO_VECTOR except that the value remains in - /// the aforementioned location in the vector register. - SCALAR_TO_VECTOR_PERMUTED, - - // FIXME: Remove these once the ANDI glue bug is fixed: - /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the - /// eq or gt bit of CR0 after executing andi. x, 1. This is used to - /// implement truncation of i32 or i64 to i1. - ANDI_rec_1_EQ_BIT, - ANDI_rec_1_GT_BIT, - - // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit - // target (returns (Lo, Hi)). It takes a chain operand. - READ_TIME_BASE, - - // EH_SJLJ_SETJMP - SjLj exception handling setjmp. - EH_SJLJ_SETJMP, - - // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. - EH_SJLJ_LONGJMP, - - /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* - /// instructions. For lack of better number, we use the opcode number - /// encoding for the OPC field to identify the compare. For example, 838 - /// is VCMPGTSH. - VCMP, - - /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the - /// altivec VCMP*_rec instructions. For lack of better number, we use the - /// opcode number encoding for the OPC field to identify the compare. For - /// example, 838 is VCMPGTSH. - VCMP_rec, - - /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This - /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the - /// condition register to branch on, OPC is the branch opcode to use (e.g. - /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is - /// an optional input flag argument. - COND_BRANCH, - - /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based - /// loops. - BDNZ, - BDZ, - - /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding - /// towards zero. Used only as part of the long double-to-int - /// conversion sequence. - FADDRTZ, - - /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. - MFFS, - - /// TC_RETURN - A tail call return. - /// operand #0 chain - /// operand #1 callee (register or absolute) - /// operand #2 stack adjustment - /// operand #3 optional in flag - TC_RETURN, - - /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls - CR6SET, - CR6UNSET, - - /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS - /// for non-position independent code on PPC32. - PPC32_GOT, - - /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and - /// local dynamic TLS and position indendepent code on PPC32. - PPC32_PICGOT, - - /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec - /// TLS model, produces an ADDIS8 instruction that adds the GOT - /// base to sym\@got\@tprel\@ha. - ADDIS_GOT_TPREL_HA, - - /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec - /// TLS model, produces a LD instruction with base register G8RReg - /// and offset sym\@got\@tprel\@l. This completes the addition that - /// finds the offset of "sym" relative to the thread pointer. - LD_GOT_TPREL_L, - - /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS - /// model, produces an ADD instruction that adds the contents of - /// G8RReg to the thread pointer. Symbol contains a relocation - /// sym\@tls which is to be replaced by the thread pointer and - /// identifies to the linker that the instruction is part of a - /// TLS sequence. - ADD_TLS, - - /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS - /// model, produces an ADDIS8 instruction that adds the GOT base - /// register to sym\@got\@tlsgd\@ha. - ADDIS_TLSGD_HA, - - /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS - /// model, produces an ADDI8 instruction that adds G8RReg to - /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by - /// ADDIS_TLSGD_L_ADDR until after register assignment. - ADDI_TLSGD_L, - - /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS - /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by - /// ADDIS_TLSGD_L_ADDR until after register assignment. - GET_TLS_ADDR, - - /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that - /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following - /// register assignment. - ADDI_TLSGD_L_ADDR, - - /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS - /// model, produces an ADDIS8 instruction that adds the GOT base - /// register to sym\@got\@tlsld\@ha. - ADDIS_TLSLD_HA, - - /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS - /// model, produces an ADDI8 instruction that adds G8RReg to - /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by - /// ADDIS_TLSLD_L_ADDR until after register assignment. - ADDI_TLSLD_L, - - /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS - /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by - /// ADDIS_TLSLD_L_ADDR until after register assignment. - GET_TLSLD_ADDR, - - /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that - /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion - /// following register assignment. - ADDI_TLSLD_L_ADDR, - - /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS - /// model, produces an ADDIS8 instruction that adds X3 to - /// sym\@dtprel\@ha. - ADDIS_DTPREL_HA, - - /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS - /// model, produces an ADDI8 instruction that adds G8RReg to - /// sym\@got\@dtprel\@l. - ADDI_DTPREL_L, - - /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS - /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. - PADDI_DTPREL, - - /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded - /// during instruction selection to optimize a BUILD_VECTOR into - /// operations on splats. This is necessary to avoid losing these - /// optimizations due to constant folding. - VADD_SPLAT, - - /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned - /// operand identifies the operating system entry point. - SC, - - /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. - CLRBHRB, - - /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch - /// history rolling buffer entry. - MFBHRBE, - - /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. - RFEBB, - - /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little - /// endian. Maps to an xxswapd instruction that corrects an lxvd2x - /// or stxvd2x instruction. The chain is necessary because the - /// sequence replaces a load and needs to provide the same number - /// of outputs. - XXSWAPD, - - /// An SDNode for swaps that are not associated with any loads/stores - /// and thereby have no chain. - SWAP_NO_CHAIN, - - /// An SDNode for Power9 vector absolute value difference. - /// operand #0 vector - /// operand #1 vector - /// operand #2 constant i32 0 or 1, to indicate whether needs to patch - /// the most significant bit for signed i32 - /// - /// Power9 VABSD* instructions are designed to support unsigned integer - /// vectors (byte/halfword/word), if we want to make use of them for signed - /// integer vectors, we have to flip their sign bits first. To flip sign bit - /// for byte/halfword integer vector would become inefficient, but for word - /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: - /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) - /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) - VABSD, - - /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or - /// lower (IDX=1) half of v4f32 to v2f64. - FP_EXTEND_HALF, - - /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done - /// either through an add like PADDI or through a PC Relative load like - /// PLD. - MAT_PCREL_ADDR, - - /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for - /// TLS global address when using dynamic access models. This can be done - /// through an add like PADDI. - TLS_DYNAMIC_MAT_PCREL_ADDR, - - /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address - /// when using local exec access models, and when prefixed instructions are - /// available. This is used with ADD_TLS to produce an add like PADDI. - TLS_LOCAL_EXEC_MAT_ADDR, - - /// ACC_BUILD = Build an accumulator register from 4 VSX registers. - ACC_BUILD, - - /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. - PAIR_BUILD, - - /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of - /// an accumulator or pair register. This node is needed because - /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same - /// element type. - EXTRACT_VSX_REG, - - /// XXMFACC = This corresponds to the xxmfacc instruction. - XXMFACC, - - // Constrained conversion from floating point to int - STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, - STRICT_FCTIWZ, - STRICT_FCTIDUZ, - STRICT_FCTIWUZ, - - /// Constrained integer-to-floating-point conversion instructions. - STRICT_FCFID, - STRICT_FCFIDU, - STRICT_FCFIDS, - STRICT_FCFIDUS, - - /// Constrained floating point add in round-to-zero mode. - STRICT_FADDRTZ, - - /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a - /// byte-swapping store instruction. It byte-swaps the low "Type" bits of - /// the GPRC input, then stores it through Ptr. Type can be either i16 or - /// i32. - STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, - - /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a - /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, - /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 - /// or i32. - LBRX, - - /// STFIWX - The STFIWX instruction. The first operand is an input token - /// chain, then an f64 value to store, then an address to store it to. - STFIWX, - - /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point - /// load which sign-extends from a 32-bit integer value into the - /// destination 64-bit register. - LFIWAX, - - /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point - /// load which zero-extends from a 32-bit integer value into the - /// destination 64-bit register. - LFIWZX, - - /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an - /// integer smaller than 64 bits into a VSR. The integer is zero-extended. - /// This can be used for converting loaded integers to floating point. - LXSIZX, - - /// STXSIX - The STXSI[bh]X instruction. The first operand is an input - /// chain, then an f64 value to store, then an address to store it to, - /// followed by a byte-width for the store. - STXSIX, - - /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. - /// Maps directly to an lxvd2x instruction that will be followed by - /// an xxswapd. - LXVD2X, - - /// LXVRZX - Load VSX Vector Rightmost and Zero Extend - /// This node represents v1i128 BUILD_VECTOR of a zero extending load - /// instruction from to i128. - /// Allows utilization of the Load VSX Vector Rightmost Instructions. - LXVRZX, - - /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. - /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on - /// the vector type to load vector in big-endian element order. - LOAD_VEC_BE, - - /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a - /// v2f32 value into the lower half of a VSR register. - LD_VSX_LH, - - /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory - /// instructions such as LXVDSX, LXVWSX. - LD_SPLAT, - - /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. - /// Maps directly to an stxvd2x instruction that will be preceded by - /// an xxswapd. - STXVD2X, - - /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. - /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on - /// the vector type to store vector in big-endian element order. - STORE_VEC_BE, - - /// Store scalar integers from VSR. - ST_VSR_SCAL_INT, - - /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes - /// except they ensure that the compare input is zero-extended for - /// sub-word versions because the atomic loads zero-extend. - ATOMIC_CMP_SWAP_8, - ATOMIC_CMP_SWAP_16, - - /// GPRC = TOC_ENTRY GA, TOC - /// Loads the entry for GA from the TOC, where the TOC base is given by - /// the last operand. - TOC_ENTRY - }; - - } // end namespace PPCISD +namespace llvm LLVM_LIBRARY_VISIBILITY { + +namespace PPCISD { + +// When adding a NEW PPCISD node please add it to the correct position in +// the enum. The order of elements in this enum matters! +// Values that are added after this entry: +// STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE +// are considered memory opcodes and are treated differently than entries +// that come before it. For example, ADD or MUL should be placed before +// the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come +// after it. +enum NodeType : unsigned { + // Start the numbering where the builtin ops and target ops leave off. + FIRST_NUMBER = ISD::BUILTIN_OP_END, + + /// FSEL - Traditional three-operand fsel node. + /// + FSEL, + + /// XSMAXCDP, XSMINCDP - C-type min/max instructions. + XSMAXCDP, + XSMINCDP, + + /// FCFID - The FCFID instruction, taking an f64 operand and producing + /// and f64 value containing the FP representation of the integer that + /// was temporarily in the f64 operand. + FCFID, + + /// Newer FCFID[US] integer-to-floating-point conversion instructions for + /// unsigned integers and single-precision outputs. + FCFIDU, + FCFIDS, + FCFIDUS, + + /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 + /// operand, producing an f64 value containing the integer representation + /// of that FP value. + FCTIDZ, + FCTIWZ, + + /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for + /// unsigned integers with round toward zero. + FCTIDUZ, + FCTIWUZ, + + /// Floating-point-to-interger conversion instructions + FP_TO_UINT_IN_VSR, + FP_TO_SINT_IN_VSR, + + /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in + /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer. + VEXTS, + + /// Reciprocal estimate instructions (unary FP ops). + FRE, + FRSQRTE, + + /// Test instruction for software square root. + FTSQRT, + + /// Square root instruction. + FSQRT, + + /// VPERM - The PPC VPERM Instruction. + /// + VPERM, + + /// XXSPLT - The PPC VSX splat instructions + /// + XXSPLT, + + /// XXSPLTI_SP_TO_DP - The PPC VSX splat instructions for immediates for + /// converting immediate single precision numbers to double precision + /// vector or scalar. + XXSPLTI_SP_TO_DP, + + /// XXSPLTI32DX - The PPC XXSPLTI32DX instruction. + /// + XXSPLTI32DX, + + /// VECINSERT - The PPC vector insert instruction + /// + VECINSERT, + + /// VECSHL - The PPC vector shift left instruction + /// + VECSHL, + + /// XXPERMDI - The PPC XXPERMDI instruction + /// + XXPERMDI, + + /// The CMPB instruction (takes two operands of i32 or i64). + CMPB, + + /// Hi/Lo - These represent the high and low 16-bit parts of a global + /// address respectively. These nodes have two operands, the first of + /// which must be a TargetGlobalAddress, and the second of which must be a + /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', + /// though these are usually folded into other nodes. + Hi, + Lo, + + /// The following two target-specific nodes are used for calls through + /// function pointers in the 64-bit SVR4 ABI. + + /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX) + /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to + /// compute an allocation on the stack. + DYNALLOC, + + /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to + /// compute an offset from native SP to the address of the most recent + /// dynamic alloca. + DYNAREAOFFSET, + + /// To avoid stack clash, allocation is performed by block and each block is + /// probed. + PROBED_ALLOCA, + + /// The result of the mflr at function entry, used for PIC code. + GlobalBaseReg, + + /// These nodes represent PPC shifts. + /// + /// For scalar types, only the last `n + 1` bits of the shift amounts + /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc. + /// for exact behaviors. + /// + /// For vector types, only the last n bits are used. See vsld. + SRL, + SRA, + SHL, + + /// FNMSUB - Negated multiply-subtract instruction. + FNMSUB, + + /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign + /// word and shift left immediate. + EXTSWSLI, + + /// The combination of sra[wd]i and addze used to implemented signed + /// integer division by a power of 2. The first operand is the dividend, + /// and the second is the constant shift amount (representing the + /// divisor). + SRA_ADDZE, + + /// CALL - A direct function call. + /// CALL_NOP is a call with the special NOP which follows 64-bit + /// CALL_NOTOC the caller does not use the TOC. + /// SVR4 calls and 32-bit/64-bit AIX calls. + CALL, + CALL_NOP, + CALL_NOTOC, + + /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a + /// MTCTR instruction. + MTCTR, + + /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a + /// BCTRL instruction. + BCTRL, + + /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl + /// instruction and the TOC reload required on 64-bit ELF, 32-bit AIX + /// and 64-bit AIX. + BCTRL_LOAD_TOC, + + /// Return with a flag operand, matched by 'blr' + RET_FLAG, + + /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction. + /// This copies the bits corresponding to the specified CRREG into the + /// resultant GPR. Bits corresponding to other CR regs are undefined. + MFOCRF, + + /// Direct move from a VSX register to a GPR + MFVSR, + + /// Direct move from a GPR to a VSX register (algebraic) + MTVSRA, + + /// Direct move from a GPR to a VSX register (zero) + MTVSRZ, + + /// Direct move of 2 consecutive GPR to a VSX register. + BUILD_FP128, + + /// BUILD_SPE64 and EXTRACT_SPE are analogous to BUILD_PAIR and + /// EXTRACT_ELEMENT but take f64 arguments instead of i64, as i64 is + /// unsupported for this target. + /// Merge 2 GPRs to a single SPE register. + BUILD_SPE64, + + /// Extract SPE register component, second argument is high or low. + EXTRACT_SPE, + + /// Extract a subvector from signed integer vector and convert to FP. + /// It is primarily used to convert a (widened) illegal integer vector + /// type to a legal floating point vector type. + /// For example v2i32 -> widened to v4i32 -> v2f64 + SINT_VEC_TO_FP, + + /// Extract a subvector from unsigned integer vector and convert to FP. + /// As with SINT_VEC_TO_FP, used for converting illegal types. + UINT_VEC_TO_FP, + + /// PowerPC instructions that have SCALAR_TO_VECTOR semantics tend to + /// place the value into the least significant element of the most + /// significant doubleword in the vector. This is not element zero for + /// anything smaller than a doubleword on either endianness. This node has + /// the same semantics as SCALAR_TO_VECTOR except that the value remains in + /// the aforementioned location in the vector register. + SCALAR_TO_VECTOR_PERMUTED, + + // FIXME: Remove these once the ANDI glue bug is fixed: + /// i1 = ANDI_rec_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the + /// eq or gt bit of CR0 after executing andi. x, 1. This is used to + /// implement truncation of i32 or i64 to i1. + ANDI_rec_1_EQ_BIT, + ANDI_rec_1_GT_BIT, + + // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit + // target (returns (Lo, Hi)). It takes a chain operand. + READ_TIME_BASE, + + // EH_SJLJ_SETJMP - SjLj exception handling setjmp. + EH_SJLJ_SETJMP, + + // EH_SJLJ_LONGJMP - SjLj exception handling longjmp. + EH_SJLJ_LONGJMP, + + /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP* + /// instructions. For lack of better number, we use the opcode number + /// encoding for the OPC field to identify the compare. For example, 838 + /// is VCMPGTSH. + VCMP, + + /// RESVEC, OUTFLAG = VCMP_rec(LHS, RHS, OPC) - Represents one of the + /// altivec VCMP*_rec instructions. For lack of better number, we use the + /// opcode number encoding for the OPC field to identify the compare. For + /// example, 838 is VCMPGTSH. + VCMP_rec, + + /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This + /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the + /// condition register to branch on, OPC is the branch opcode to use (e.g. + /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is + /// an optional input flag argument. + COND_BRANCH, + + /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based + /// loops. + BDNZ, + BDZ, + + /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding + /// towards zero. Used only as part of the long double-to-int + /// conversion sequence. + FADDRTZ, + + /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register. + MFFS, + + /// TC_RETURN - A tail call return. + /// operand #0 chain + /// operand #1 callee (register or absolute) + /// operand #2 stack adjustment + /// operand #3 optional in flag + TC_RETURN, + + /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls + CR6SET, + CR6UNSET, + + /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS + /// for non-position independent code on PPC32. + PPC32_GOT, + + /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and + /// local dynamic TLS and position indendepent code on PPC32. + PPC32_PICGOT, + + /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec + /// TLS model, produces an ADDIS8 instruction that adds the GOT + /// base to sym\@got\@tprel\@ha. + ADDIS_GOT_TPREL_HA, + + /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec + /// TLS model, produces a LD instruction with base register G8RReg + /// and offset sym\@got\@tprel\@l. This completes the addition that + /// finds the offset of "sym" relative to the thread pointer. + LD_GOT_TPREL_L, + + /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS + /// model, produces an ADD instruction that adds the contents of + /// G8RReg to the thread pointer. Symbol contains a relocation + /// sym\@tls which is to be replaced by the thread pointer and + /// identifies to the linker that the instruction is part of a + /// TLS sequence. + ADD_TLS, + + /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS + /// model, produces an ADDIS8 instruction that adds the GOT base + /// register to sym\@got\@tlsgd\@ha. + ADDIS_TLSGD_HA, + + /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS + /// model, produces an ADDI8 instruction that adds G8RReg to + /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by + /// ADDIS_TLSGD_L_ADDR until after register assignment. + ADDI_TLSGD_L, + + /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS + /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by + /// ADDIS_TLSGD_L_ADDR until after register assignment. + GET_TLS_ADDR, + + /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that + /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following + /// register assignment. + ADDI_TLSGD_L_ADDR, + + /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS + /// model, produces an ADDIS8 instruction that adds the GOT base + /// register to sym\@got\@tlsld\@ha. + ADDIS_TLSLD_HA, + + /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS + /// model, produces an ADDI8 instruction that adds G8RReg to + /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by + /// ADDIS_TLSLD_L_ADDR until after register assignment. + ADDI_TLSLD_L, + + /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS + /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by + /// ADDIS_TLSLD_L_ADDR until after register assignment. + GET_TLSLD_ADDR, + + /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that + /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion + /// following register assignment. + ADDI_TLSLD_L_ADDR, + + /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS + /// model, produces an ADDIS8 instruction that adds X3 to + /// sym\@dtprel\@ha. + ADDIS_DTPREL_HA, + + /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS + /// model, produces an ADDI8 instruction that adds G8RReg to + /// sym\@got\@dtprel\@l. + ADDI_DTPREL_L, + + /// G8RC = PADDI_DTPREL %x3, Symbol - For the pc-rel based local-dynamic TLS + /// model, produces a PADDI8 instruction that adds X3 to sym\@dtprel. + PADDI_DTPREL, + + /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded + /// during instruction selection to optimize a BUILD_VECTOR into + /// operations on splats. This is necessary to avoid losing these + /// optimizations due to constant folding. + VADD_SPLAT, + + /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned + /// operand identifies the operating system entry point. + SC, + + /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer. + CLRBHRB, + + /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch + /// history rolling buffer entry. + MFBHRBE, + + /// CHAIN = RFEBB CHAIN, State - Return from event-based branch. + RFEBB, + + /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little + /// endian. Maps to an xxswapd instruction that corrects an lxvd2x + /// or stxvd2x instruction. The chain is necessary because the + /// sequence replaces a load and needs to provide the same number + /// of outputs. + XXSWAPD, + + /// An SDNode for swaps that are not associated with any loads/stores + /// and thereby have no chain. + SWAP_NO_CHAIN, + + /// An SDNode for Power9 vector absolute value difference. + /// operand #0 vector + /// operand #1 vector + /// operand #2 constant i32 0 or 1, to indicate whether needs to patch + /// the most significant bit for signed i32 + /// + /// Power9 VABSD* instructions are designed to support unsigned integer + /// vectors (byte/halfword/word), if we want to make use of them for signed + /// integer vectors, we have to flip their sign bits first. To flip sign bit + /// for byte/halfword integer vector would become inefficient, but for word + /// integer vector, we can leverage XVNEGSP to make it efficiently. eg: + /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000) + /// => VABSDUW((XVNEGSP a), (XVNEGSP b)) + VABSD, + + /// FP_EXTEND_HALF(VECTOR, IDX) - Custom extend upper (IDX=0) half or + /// lower (IDX=1) half of v4f32 to v2f64. + FP_EXTEND_HALF, + + /// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done + /// either through an add like PADDI or through a PC Relative load like + /// PLD. + MAT_PCREL_ADDR, + + /// TLS_DYNAMIC_MAT_PCREL_ADDR = Materialize a PC Relative address for + /// TLS global address when using dynamic access models. This can be done + /// through an add like PADDI. + TLS_DYNAMIC_MAT_PCREL_ADDR, + + /// TLS_LOCAL_EXEC_MAT_ADDR = Materialize an address for TLS global address + /// when using local exec access models, and when prefixed instructions are + /// available. This is used with ADD_TLS to produce an add like PADDI. + TLS_LOCAL_EXEC_MAT_ADDR, + + /// ACC_BUILD = Build an accumulator register from 4 VSX registers. + ACC_BUILD, + + /// PAIR_BUILD = Build a vector pair register from 2 VSX registers. + PAIR_BUILD, + + /// EXTRACT_VSX_REG = Extract one of the underlying vsx registers of + /// an accumulator or pair register. This node is needed because + /// EXTRACT_SUBVECTOR expects the input and output vectors to have the same + /// element type. + EXTRACT_VSX_REG, + + /// XXMFACC = This corresponds to the xxmfacc instruction. + XXMFACC, + + // Constrained conversion from floating point to int + STRICT_FCTIDZ = ISD::FIRST_TARGET_STRICTFP_OPCODE, + STRICT_FCTIWZ, + STRICT_FCTIDUZ, + STRICT_FCTIWUZ, + + /// Constrained integer-to-floating-point conversion instructions. + STRICT_FCFID, + STRICT_FCFIDU, + STRICT_FCFIDS, + STRICT_FCFIDUS, + + /// Constrained floating point add in round-to-zero mode. + STRICT_FADDRTZ, + + /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a + /// byte-swapping store instruction. It byte-swaps the low "Type" bits of + /// the GPRC input, then stores it through Ptr. Type can be either i16 or + /// i32. + STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE, + + /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a + /// byte-swapping load instruction. It loads "Type" bits, byte swaps it, + /// then puts it in the bottom bits of the GPRC. TYPE can be either i16 + /// or i32. + LBRX, + + /// STFIWX - The STFIWX instruction. The first operand is an input token + /// chain, then an f64 value to store, then an address to store it to. + STFIWX, + + /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point + /// load which sign-extends from a 32-bit integer value into the + /// destination 64-bit register. + LFIWAX, + + /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point + /// load which zero-extends from a 32-bit integer value into the + /// destination 64-bit register. + LFIWZX, + + /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an + /// integer smaller than 64 bits into a VSR. The integer is zero-extended. + /// This can be used for converting loaded integers to floating point. + LXSIZX, + + /// STXSIX - The STXSI[bh]X instruction. The first operand is an input + /// chain, then an f64 value to store, then an address to store it to, + /// followed by a byte-width for the store. + STXSIX, + + /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian. + /// Maps directly to an lxvd2x instruction that will be followed by + /// an xxswapd. + LXVD2X, + + /// LXVRZX - Load VSX Vector Rightmost and Zero Extend + /// This node represents v1i128 BUILD_VECTOR of a zero extending load + /// instruction from to i128. + /// Allows utilization of the Load VSX Vector Rightmost Instructions. + LXVRZX, + + /// VSRC, CHAIN = LOAD_VEC_BE CHAIN, Ptr - Occurs only for little endian. + /// Maps directly to one of lxvd2x/lxvw4x/lxvh8x/lxvb16x depending on + /// the vector type to load vector in big-endian element order. + LOAD_VEC_BE, + + /// VSRC, CHAIN = LD_VSX_LH CHAIN, Ptr - This is a floating-point load of a + /// v2f32 value into the lower half of a VSR register. + LD_VSX_LH, + + /// VSRC, CHAIN = LD_SPLAT, CHAIN, Ptr - a splatting load memory + /// instructions such as LXVDSX, LXVWSX. + LD_SPLAT, + + /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian. + /// Maps directly to an stxvd2x instruction that will be preceded by + /// an xxswapd. + STXVD2X, + + /// CHAIN = STORE_VEC_BE CHAIN, VSRC, Ptr - Occurs only for little endian. + /// Maps directly to one of stxvd2x/stxvw4x/stxvh8x/stxvb16x depending on + /// the vector type to store vector in big-endian element order. + STORE_VEC_BE, + + /// Store scalar integers from VSR. + ST_VSR_SCAL_INT, + + /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes + /// except they ensure that the compare input is zero-extended for + /// sub-word versions because the atomic loads zero-extend. + ATOMIC_CMP_SWAP_8, + ATOMIC_CMP_SWAP_16, + + /// GPRC = TOC_ENTRY GA, TOC + /// Loads the entry for GA from the TOC, where the TOC base is given by + /// the last operand. + TOC_ENTRY +}; + +} // end namespace PPCISD /// Define some predicates that are used for node matching. namespace PPC { @@ -1323,6 +1323,6 @@ bool convertToNonDenormSingle(APInt &ArgAPInt); bool convertToNonDenormSingle(APFloat &ArgAPFloat); -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H Index: llvm/lib/Target/PowerPC/PPCInstrBuilder.h =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrBuilder.h +++ llvm/lib/Target/PowerPC/PPCInstrBuilder.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// addFrameReference - This function is used to add a reference to the base of /// an abstract object on the stack frame of the current function. This @@ -37,6 +37,6 @@ return MIB.addFrameIndex(FI).addImm(Offset); } -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCInstrInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "PPCGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// PPCII - This namespace holds all of the PowerPC target-specific /// per-instruction flags. These must match the corresponding definitions in @@ -694,6 +694,6 @@ analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/TargetCallingConv.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// PPCFunctionInfo - This class is derived from MachineFunction private /// PowerPC target-specific information for each MachineFunction. @@ -254,6 +254,6 @@ MCSymbol *getTOCOffsetSymbol(MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_POWERPC_PPCMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/PowerPC/PPCMachineScheduler.h =================================================================== --- llvm/lib/Target/PowerPC/PPCMachineScheduler.h +++ llvm/lib/Target/PowerPC/PPCMachineScheduler.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A MachineSchedStrategy implementation for PowerPC pre RA scheduling. class PPCPreRASchedStrategy : public GenericScheduler { @@ -47,6 +47,6 @@ bool biasAddiCandidate(SchedCandidate &Cand, SchedCandidate &TryCand) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_POWERPC_POWERPCMACHINESCHEDULER_H Index: llvm/lib/Target/PowerPC/PPCMacroFusion.h =================================================================== --- llvm/lib/Target/PowerPC/PPCMacroFusion.h +++ llvm/lib/Target/PowerPC/PPCMacroFusion.h @@ -13,10 +13,10 @@ #include "llvm/CodeGen/MachineScheduler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Note that you have to add: /// DAG.addMutation(createPowerPCMacroFusionDAGMutation()); /// to PPCPassConfig::createMachineScheduler() to have an effect. std::unique_ptr createPowerPCMacroFusionDAGMutation(); -} // llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/PowerPC/PPCMacroFusion.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCMacroFusion.cpp +++ llvm/lib/Target/PowerPC/PPCMacroFusion.cpp @@ -194,10 +194,10 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createPowerPCMacroFusionDAGMutation () { return createMacroFusionDAGMutation(shouldScheduleAdjacent); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -20,7 +20,7 @@ #define GET_REGINFO_HEADER #include "PPCGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCTargetMachine; inline static unsigned getCRFromCRBit(unsigned SrcReg) { @@ -174,6 +174,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -32,7 +32,7 @@ // GCC #defines PPC on Linux but we use it as our namespace name #undef PPC -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; namespace PPC { @@ -413,6 +413,6 @@ const LegalizerInfo *getLegalizerInfo() const override; InstructionSelector *getInstructionSelector() const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCTargetMachine.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetMachine.h +++ llvm/lib/Target/PowerPC/PPCTargetMachine.h @@ -18,7 +18,7 @@ #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Common code between 32-bit and 64-bit PowerPC targets. /// @@ -64,6 +64,6 @@ return true; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCTargetObjectFile.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetObjectFile.h +++ llvm/lib/Target/PowerPC/PPCTargetObjectFile.h @@ -13,21 +13,21 @@ #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - /// PPC64LinuxTargetObjectFile - This implementation is used for - /// 64-bit PowerPC Linux. - class PPC64LinuxTargetObjectFile : public TargetLoweringObjectFileELF { +/// PPC64LinuxTargetObjectFile - This implementation is used for +/// 64-bit PowerPC Linux. +class PPC64LinuxTargetObjectFile : public TargetLoweringObjectFileELF { - void Initialize(MCContext &Ctx, const TargetMachine &TM) override; + void Initialize(MCContext &Ctx, const TargetMachine &TM) override; - MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, - const TargetMachine &TM) const override; + MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, + const TargetMachine &TM) const override; - /// Describe a TLS variable address within debug info. - const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; - }; + /// Describe a TLS variable address within debug info. + const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; +}; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCTargetStreamer.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetStreamer.h +++ llvm/lib/Target/PowerPC/PPCTargetStreamer.h @@ -12,7 +12,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCExpr; class MCSymbol; @@ -29,6 +29,6 @@ virtual void emitLocalEntry(MCSymbolELF *S, const MCExpr *LocalOffset) = 0; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_POWERPC_PPCTARGETSTREAMER_H Index: llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h =================================================================== --- llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class PPCTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -135,6 +135,6 @@ /// @} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp =================================================================== --- llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp +++ llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp @@ -50,9 +50,11 @@ #define DEBUG_TYPE "ppc-vsx-fma-mutate" -namespace llvm { namespace PPC { - int getAltVSXFMAOpcode(uint16_t Opcode); -} } +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace PPC { +int getAltVSXFMAOpcode(uint16_t Opcode); +} +} // namespace LLVM_LIBRARY_VISIBILITY namespace { // PPCVSXFMAMutate pass - For copies between VSX registers and non-VSX registers Index: llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.h =================================================================== --- llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.h +++ llvm/lib/Target/PowerPC/TargetInfo/PowerPCTargetInfo.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_POWERPC_TARGETINFO_POWERPCTARGETINFO_H #define LLVM_LIB_TARGET_POWERPC_TARGETINFO_POWERPCTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -18,6 +20,6 @@ Target &getThePPC64Target(); Target &getThePPC64LETarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_POWERPC_TARGETINFO_POWERPCTARGETINFO_H Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAssembler; class MCObjectTargetWriter; class raw_ostream; @@ -113,6 +113,6 @@ const MCTargetOptions &getTargetOptions() const { return TargetOptions; } RISCVABI::ABI getTargetABI() const { return TargetABI; } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -20,7 +20,7 @@ #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/MachineValueType.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // RISCVII - This namespace holds all of the target specific flags that // instruction info tracks. All definitions must match RISCVInstrFormats.td. @@ -401,6 +401,6 @@ } // end namespace RISCVVPseudosTable -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -16,7 +16,7 @@ #include "llvm/ADT/Triple.h" #include "llvm/Support/raw_ostream.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace RISCVSysReg { #define GET_SysRegsList_IMPL #include "RISCVGenSearchableTables.inc" @@ -139,4 +139,4 @@ OS << ",mu"; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h @@ -12,7 +12,7 @@ #include "RISCVTargetStreamer.h" #include "llvm/MC/MCELFStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVTargetELFStreamer : public RISCVTargetStreamer { private: @@ -104,5 +104,5 @@ void emitDirectiveOptionRelax() override; void emitDirectiveOptionNoRelax() override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h @@ -13,7 +13,7 @@ #undef RISCV -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace RISCV { enum Fixups { // fixup_riscv_hi20 - 20-bit fixup corresponding to hi(foo) for @@ -87,6 +87,6 @@ NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind }; } // end namespace RISCV -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -16,7 +16,7 @@ #include "MCTargetDesc/RISCVMCTargetDesc.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVInstPrinter : public MCInstPrinter { public: @@ -59,6 +59,6 @@ static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo, unsigned AltIdx); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class RISCVMCAsmInfo : public MCAsmInfoELF { @@ -28,6 +28,6 @@ MCStreamer &Streamer) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; @@ -86,6 +86,6 @@ static StringRef getVariantKindName(VariantKind Kind); }; -} // end namespace llvm. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h @@ -18,7 +18,7 @@ #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -38,7 +38,7 @@ std::unique_ptr createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit); -} +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for RISC-V registers. #define GET_REGINFO_ENUM Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h @@ -12,7 +12,7 @@ #include "llvm/ADT/SmallVector.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class APInt; namespace RISCVMatInt { @@ -39,5 +39,5 @@ // `Size`-bit immediate. `IsRV64` should match the target architecture. int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64); } // namespace RISCVMatInt -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp @@ -11,7 +11,7 @@ #include "llvm/ADT/APInt.h" #include "llvm/Support/MathExtras.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace RISCVMatInt { void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) { @@ -88,4 +88,4 @@ return std::max(1, Cost); } } // namespace RISCVMatInt -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVTargetStreamer : public MCTargetStreamer { public: @@ -59,5 +59,5 @@ void emitDirectiveOptionNoRelax() override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCV.h =================================================================== --- llvm/lib/Target/RISCV/RISCV.h +++ llvm/lib/Target/RISCV/RISCV.h @@ -17,7 +17,7 @@ #include "MCTargetDesc/RISCVBaseInfo.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVRegisterBankInfo; class RISCVSubtarget; class RISCVTargetMachine; @@ -52,6 +52,6 @@ InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &, RISCVSubtarget &, RISCVRegisterBankInfo &); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVCallLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVCallLowering.h +++ llvm/lib/Target/RISCV/RISCVCallLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/ValueTypes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVTargetLowering; @@ -39,6 +39,6 @@ CallLoweringInfo &Info) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_RISCV_RISCVCALLLOWERING_H Index: llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp +++ llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp @@ -609,10 +609,10 @@ INITIALIZE_PASS(RISCVExpandAtomicPseudo, "riscv-expand-atomic-pseudo", RISCV_EXPAND_ATOMIC_PSEUDO_NAME, false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createRISCVExpandAtomicPseudoPass() { return new RISCVExpandAtomicPseudo(); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp +++ llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp @@ -257,8 +257,8 @@ INITIALIZE_PASS(RISCVExpandPseudo, "riscv-expand-pseudo", RISCV_EXPAND_PSEUDO_NAME, false, false) -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { FunctionPass *createRISCVExpandPseudoPass() { return new RISCVExpandPseudo(); } -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/RISCVFrameLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVSubtarget; class RISCVFrameLowering : public TargetFrameLowering { @@ -74,5 +74,5 @@ const DebugLoc &DL, Register DestReg, Register SrcReg, int64_t Val, MachineInstr::MIFlag Flag) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -19,7 +19,7 @@ // RISCV-specific code to select RISCV machine instructions for // SelectionDAG operations. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVDAGToDAGISel : public SelectionDAGISel { const RISCVSubtarget *Subtarget = nullptr; @@ -71,6 +71,6 @@ private: void doPeepholeLoadStoreADDI(); }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVISelLowering.h =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.h +++ llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVSubtarget; namespace RISCVISD { enum NodeType : unsigned { @@ -354,6 +354,6 @@ #include "RISCVGenSearchableTables.inc" } // namespace RISCVZvlssegTable -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -4564,7 +4564,7 @@ return Reg; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace RISCVVIntrinsicsTable { #define GET_RISCVVIntrinsicsTable_IMPL @@ -4578,4 +4578,4 @@ #include "RISCVGenSearchableTables.inc" } // namespace RISCVZvlssegTable -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "RISCVGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVSubtarget; @@ -137,5 +137,5 @@ const RISCVSubtarget &STI; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp +++ llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp @@ -94,11 +94,11 @@ return false; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { InstructionSelector * createRISCVInstructionSelector(const RISCVTargetMachine &TM, RISCVSubtarget &Subtarget, RISCVRegisterBankInfo &RBI) { return new RISCVInstructionSelector(TM, Subtarget, RBI); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/RISCV/RISCVLegalizerInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVLegalizerInfo.h +++ llvm/lib/Target/RISCV/RISCVLegalizerInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVSubtarget; @@ -24,5 +24,5 @@ public: RISCVLegalizerInfo(const RISCVSubtarget &ST); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h +++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// RISCVMachineFunctionInfo - This class is derived from MachineFunctionInfo /// and contains private RISCV-specific information for each MachineFunction. @@ -60,6 +60,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h +++ llvm/lib/Target/RISCV/RISCVRegisterBankInfo.h @@ -18,7 +18,7 @@ #define GET_REGBANK_DECLARATIONS #include "RISCVGenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class TargetRegisterInfo; @@ -33,5 +33,5 @@ public: RISCVRegisterBankInfo(const TargetRegisterInfo &TRI); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.h +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "RISCVGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct RISCVRegisterInfo : public RISCVGenRegisterInfo { @@ -60,6 +60,6 @@ return &RISCV::GPRRegClass; } }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVSubtarget.h =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.h +++ llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -29,7 +29,7 @@ #define GET_SUBTARGETINFO_HEADER #include "RISCVGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class RISCVSubtarget : public RISCVGenSubtargetInfo { @@ -148,6 +148,6 @@ const LegalizerInfo *getLegalizerInfo() const override; const RegisterBankInfo *getRegBankInfo() const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.h +++ llvm/lib/Target/RISCV/RISCVTargetMachine.h @@ -19,7 +19,7 @@ #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; mutable StringMap> SubtargetMap; @@ -47,6 +47,6 @@ virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVTargetObjectFile.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetObjectFile.h +++ llvm/lib/Target/RISCV/RISCVTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// This implementation is used for RISCV ELF targets. class RISCVELFTargetObjectFile : public TargetLoweringObjectFileELF { @@ -42,6 +42,6 @@ bool isInSmallSection(uint64_t Size) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -22,7 +22,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/IR/Function.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class RISCVTTIImpl : public BasicTTIImplBase { using BaseT = BasicTTIImplBase; @@ -49,6 +49,6 @@ Type *Ty, TTI::TargetCostKind CostKind); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h =================================================================== --- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h +++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h @@ -9,13 +9,15 @@ #ifndef LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H #define LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheRISCV32Target(); Target &getTheRISCV64Target(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H Index: llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp =================================================================== --- llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -39,13 +39,13 @@ // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target // namespace. But SPARC backend uses "SP" as its namespace. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Sparc { using namespace SP; } // end namespace Sparc -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY namespace { Index: llvm/lib/Target/Sparc/LeonPasses.h =================================================================== --- llvm/lib/Target/Sparc/LeonPasses.h +++ llvm/lib/Target/Sparc/LeonPasses.h @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcSubtarget; class LLVM_LIBRARY_VISIBILITY LEONMachineFunctionPass @@ -77,6 +77,6 @@ "instructions with NOPs and floating-point store"; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SPARC_LEON_PASSES_H Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h @@ -11,92 +11,92 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { - namespace Sparc { - enum Fixups { - // fixup_sparc_call30 - 30-bit PC relative relocation for call - fixup_sparc_call30 = FirstTargetFixupKind, - - /// fixup_sparc_br22 - 22-bit PC relative relocation for - /// branches - fixup_sparc_br22, - - /// fixup_sparc_br19 - 19-bit PC relative relocation for - /// branches on icc/xcc - fixup_sparc_br19, - - /// fixup_sparc_bpr - 16-bit fixup for bpr - fixup_sparc_br16_2, - fixup_sparc_br16_14, - - /// fixup_sparc_13 - 13-bit fixup - fixup_sparc_13, - - /// fixup_sparc_hi22 - 22-bit fixup corresponding to %hi(foo) - /// for sethi - fixup_sparc_hi22, - - /// fixup_sparc_lo10 - 10-bit fixup corresponding to %lo(foo) - fixup_sparc_lo10, - - /// fixup_sparc_h44 - 22-bit fixup corresponding to %h44(foo) - fixup_sparc_h44, - - /// fixup_sparc_m44 - 10-bit fixup corresponding to %m44(foo) - fixup_sparc_m44, - - /// fixup_sparc_l44 - 12-bit fixup corresponding to %l44(foo) - fixup_sparc_l44, - - /// fixup_sparc_hh - 22-bit fixup corresponding to %hh(foo) - fixup_sparc_hh, - - /// fixup_sparc_hm - 10-bit fixup corresponding to %hm(foo) - fixup_sparc_hm, - - /// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo) - fixup_sparc_pc22, - - /// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo) - fixup_sparc_pc10, - - /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo) - fixup_sparc_got22, - - /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo) - fixup_sparc_got10, - - /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo) - fixup_sparc_got13, - - /// fixup_sparc_wplt30 - fixup_sparc_wplt30, - - /// fixups for Thread Local Storage - fixup_sparc_tls_gd_hi22, - fixup_sparc_tls_gd_lo10, - fixup_sparc_tls_gd_add, - fixup_sparc_tls_gd_call, - fixup_sparc_tls_ldm_hi22, - fixup_sparc_tls_ldm_lo10, - fixup_sparc_tls_ldm_add, - fixup_sparc_tls_ldm_call, - fixup_sparc_tls_ldo_hix22, - fixup_sparc_tls_ldo_lox10, - fixup_sparc_tls_ldo_add, - fixup_sparc_tls_ie_hi22, - fixup_sparc_tls_ie_lo10, - fixup_sparc_tls_ie_ld, - fixup_sparc_tls_ie_ldx, - fixup_sparc_tls_ie_add, - fixup_sparc_tls_le_hix22, - fixup_sparc_tls_le_lox10, - - // Marker - LastTargetFixupKind, - NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind - }; - } +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace Sparc { +enum Fixups { + // fixup_sparc_call30 - 30-bit PC relative relocation for call + fixup_sparc_call30 = FirstTargetFixupKind, + + /// fixup_sparc_br22 - 22-bit PC relative relocation for + /// branches + fixup_sparc_br22, + + /// fixup_sparc_br19 - 19-bit PC relative relocation for + /// branches on icc/xcc + fixup_sparc_br19, + + /// fixup_sparc_bpr - 16-bit fixup for bpr + fixup_sparc_br16_2, + fixup_sparc_br16_14, + + /// fixup_sparc_13 - 13-bit fixup + fixup_sparc_13, + + /// fixup_sparc_hi22 - 22-bit fixup corresponding to %hi(foo) + /// for sethi + fixup_sparc_hi22, + + /// fixup_sparc_lo10 - 10-bit fixup corresponding to %lo(foo) + fixup_sparc_lo10, + + /// fixup_sparc_h44 - 22-bit fixup corresponding to %h44(foo) + fixup_sparc_h44, + + /// fixup_sparc_m44 - 10-bit fixup corresponding to %m44(foo) + fixup_sparc_m44, + + /// fixup_sparc_l44 - 12-bit fixup corresponding to %l44(foo) + fixup_sparc_l44, + + /// fixup_sparc_hh - 22-bit fixup corresponding to %hh(foo) + fixup_sparc_hh, + + /// fixup_sparc_hm - 10-bit fixup corresponding to %hm(foo) + fixup_sparc_hm, + + /// fixup_sparc_pc22 - 22-bit fixup corresponding to %pc22(foo) + fixup_sparc_pc22, + + /// fixup_sparc_pc10 - 10-bit fixup corresponding to %pc10(foo) + fixup_sparc_pc10, + + /// fixup_sparc_got22 - 22-bit fixup corresponding to %got22(foo) + fixup_sparc_got22, + + /// fixup_sparc_got10 - 10-bit fixup corresponding to %got10(foo) + fixup_sparc_got10, + + /// fixup_sparc_got13 - 13-bit fixup corresponding to %got13(foo) + fixup_sparc_got13, + + /// fixup_sparc_wplt30 + fixup_sparc_wplt30, + + /// fixups for Thread Local Storage + fixup_sparc_tls_gd_hi22, + fixup_sparc_tls_gd_lo10, + fixup_sparc_tls_gd_add, + fixup_sparc_tls_gd_call, + fixup_sparc_tls_ldm_hi22, + fixup_sparc_tls_ldm_lo10, + fixup_sparc_tls_ldm_add, + fixup_sparc_tls_ldm_call, + fixup_sparc_tls_ldo_hix22, + fixup_sparc_tls_ldo_lox10, + fixup_sparc_tls_ldo_add, + fixup_sparc_tls_ie_hi22, + fixup_sparc_tls_ie_lo10, + fixup_sparc_tls_ie_ld, + fixup_sparc_tls_ie_ldx, + fixup_sparc_tls_ie_add, + fixup_sparc_tls_le_hix22, + fixup_sparc_tls_le_lox10, + + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind +}; } +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcInstPrinter : public MCInstPrinter { public: @@ -52,6 +52,6 @@ void printMembarTag(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp @@ -24,11 +24,11 @@ // The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target // namespace. But SPARC backend uses "SP" as its namespace. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace Sparc { using namespace SP; } -} +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -34,6 +34,6 @@ }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -17,7 +17,7 @@ #include "SparcFixupKinds.h" #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class SparcMCExpr : public MCTargetExpr { @@ -109,6 +109,6 @@ static Sparc::Fixups getFixupKind(VariantKind Kind); }; -} // end namespace llvm. +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -13,11 +13,12 @@ #ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H #define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -36,7 +37,7 @@ const MCTargetOptions &Options); std::unique_ptr createSparcELFObjectWriter(bool Is64Bit, uint8_t OSABI); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for Sparc registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.h =================================================================== --- llvm/lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.h +++ llvm/lib/Target/Sparc/MCTargetDesc/SparcTargetStreamer.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcTargetStreamer : public MCTargetStreamer { virtual void anchor(); @@ -42,6 +42,6 @@ void emitSparcRegisterIgnore(unsigned reg) override {} void emitSparcRegisterScratch(unsigned reg) override {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/Sparc.h =================================================================== --- llvm/lib/Target/Sparc/Sparc.h +++ llvm/lib/Target/Sparc/Sparc.h @@ -18,78 +18,77 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { - class FunctionPass; - class SparcTargetMachine; - class AsmPrinter; - class MCInst; - class MachineInstr; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class FunctionPass; +class SparcTargetMachine; +class AsmPrinter; +class MCInst; +class MachineInstr; - FunctionPass *createSparcISelDag(SparcTargetMachine &TM); - FunctionPass *createSparcDelaySlotFillerPass(); +FunctionPass *createSparcISelDag(SparcTargetMachine &TM); +FunctionPass *createSparcDelaySlotFillerPass(); - void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, - MCInst &OutMI, - AsmPrinter &AP); -} // end namespace llvm; +void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, + AsmPrinter &AP); +} // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { - // Enums corresponding to Sparc condition codes, both icc's and fcc's. These - // values must be kept in sync with the ones in the .td file. - namespace SPCC { - enum CondCodes { - ICC_A = 8 , // Always - ICC_N = 0 , // Never - ICC_NE = 9 , // Not Equal - ICC_E = 1 , // Equal - ICC_G = 10 , // Greater - ICC_LE = 2 , // Less or Equal - ICC_GE = 11 , // Greater or Equal - ICC_L = 3 , // Less - ICC_GU = 12 , // Greater Unsigned - ICC_LEU = 4 , // Less or Equal Unsigned - ICC_CC = 13 , // Carry Clear/Great or Equal Unsigned - ICC_CS = 5 , // Carry Set/Less Unsigned - ICC_POS = 14 , // Positive - ICC_NEG = 6 , // Negative - ICC_VC = 15 , // Overflow Clear - ICC_VS = 7 , // Overflow Set +namespace llvm LLVM_LIBRARY_VISIBILITY { +// Enums corresponding to Sparc condition codes, both icc's and fcc's. These +// values must be kept in sync with the ones in the .td file. +namespace SPCC { +enum CondCodes { + ICC_A = 8, // Always + ICC_N = 0, // Never + ICC_NE = 9, // Not Equal + ICC_E = 1, // Equal + ICC_G = 10, // Greater + ICC_LE = 2, // Less or Equal + ICC_GE = 11, // Greater or Equal + ICC_L = 3, // Less + ICC_GU = 12, // Greater Unsigned + ICC_LEU = 4, // Less or Equal Unsigned + ICC_CC = 13, // Carry Clear/Great or Equal Unsigned + ICC_CS = 5, // Carry Set/Less Unsigned + ICC_POS = 14, // Positive + ICC_NEG = 6, // Negative + ICC_VC = 15, // Overflow Clear + ICC_VS = 7, // Overflow Set - FCC_A = 8+16, // Always - FCC_N = 0+16, // Never - FCC_U = 7+16, // Unordered - FCC_G = 6+16, // Greater - FCC_UG = 5+16, // Unordered or Greater - FCC_L = 4+16, // Less - FCC_UL = 3+16, // Unordered or Less - FCC_LG = 2+16, // Less or Greater - FCC_NE = 1+16, // Not Equal - FCC_E = 9+16, // Equal - FCC_UE = 10+16, // Unordered or Equal - FCC_GE = 11+16, // Greater or Equal - FCC_UGE = 12+16, // Unordered or Greater or Equal - FCC_LE = 13+16, // Less or Equal - FCC_ULE = 14+16, // Unordered or Less or Equal - FCC_O = 15+16, // Ordered + FCC_A = 8 + 16, // Always + FCC_N = 0 + 16, // Never + FCC_U = 7 + 16, // Unordered + FCC_G = 6 + 16, // Greater + FCC_UG = 5 + 16, // Unordered or Greater + FCC_L = 4 + 16, // Less + FCC_UL = 3 + 16, // Unordered or Less + FCC_LG = 2 + 16, // Less or Greater + FCC_NE = 1 + 16, // Not Equal + FCC_E = 9 + 16, // Equal + FCC_UE = 10 + 16, // Unordered or Equal + FCC_GE = 11 + 16, // Greater or Equal + FCC_UGE = 12 + 16, // Unordered or Greater or Equal + FCC_LE = 13 + 16, // Less or Equal + FCC_ULE = 14 + 16, // Unordered or Less or Equal + FCC_O = 15 + 16, // Ordered - CPCC_A = 8+32, // Always - CPCC_N = 0+32, // Never - CPCC_3 = 7+32, - CPCC_2 = 6+32, - CPCC_23 = 5+32, - CPCC_1 = 4+32, - CPCC_13 = 3+32, - CPCC_12 = 2+32, - CPCC_123 = 1+32, - CPCC_0 = 9+32, - CPCC_03 = 10+32, - CPCC_02 = 11+32, - CPCC_023 = 12+32, - CPCC_01 = 13+32, - CPCC_013 = 14+32, - CPCC_012 = 15+32 - }; - } + CPCC_A = 8 + 32, // Always + CPCC_N = 0 + 32, // Never + CPCC_3 = 7 + 32, + CPCC_2 = 6 + 32, + CPCC_23 = 5 + 32, + CPCC_1 = 4 + 32, + CPCC_13 = 3 + 32, + CPCC_12 = 2 + 32, + CPCC_123 = 1 + 32, + CPCC_0 = 9 + 32, + CPCC_03 = 10 + 32, + CPCC_02 = 11 + 32, + CPCC_023 = 12 + 32, + CPCC_01 = 13 + 32, + CPCC_013 = 14 + 32, + CPCC_012 = 15 + 32 +}; +} inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) { switch (CC) { @@ -161,5 +160,5 @@ return ~LO10(~imm); } -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcFrameLowering.h =================================================================== --- llvm/lib/Target/Sparc/SparcFrameLowering.h +++ llvm/lib/Target/Sparc/SparcFrameLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcSubtarget; class SparcFrameLowering : public TargetFrameLowering { @@ -63,6 +63,6 @@ }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcISelLowering.h =================================================================== --- llvm/lib/Target/Sparc/SparcISelLowering.h +++ llvm/lib/Target/Sparc/SparcISelLowering.h @@ -17,38 +17,39 @@ #include "Sparc.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { - class SparcSubtarget; - - namespace SPISD { - enum NodeType : unsigned { - FIRST_NUMBER = ISD::BUILTIN_OP_END, - CMPICC, // Compare two GPR operands, set icc+xcc. - CMPFCC, // Compare two FP operands, set fcc. - BRICC, // Branch to dest on icc condition - BRXCC, // Branch to dest on xcc condition (64-bit only). - BRFCC, // Branch to dest on fcc condition - SELECT_ICC, // Select between two values using the current ICC flags. - SELECT_XCC, // Select between two values using the current XCC flags. - SELECT_FCC, // Select between two values using the current FCC flags. - - Hi, Lo, // Hi/Lo operations, typically on a global address. - - FTOI, // FP to Int within a FP register. - ITOF, // Int to FP within a FP register. - FTOX, // FP to Int64 within a FP register. - XTOF, // Int64 to FP within a FP register. - - CALL, // A call instruction. - RET_FLAG, // Return with a flag operand. - GLOBAL_BASE_REG, // Global base reg for PIC. - FLUSHW, // FLUSH register windows to stack. - - TLS_ADD, // For Thread Local Storage (TLS). - TLS_LD, - TLS_CALL - }; - } +namespace llvm LLVM_LIBRARY_VISIBILITY { +class SparcSubtarget; + +namespace SPISD { +enum NodeType : unsigned { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + CMPICC, // Compare two GPR operands, set icc+xcc. + CMPFCC, // Compare two FP operands, set fcc. + BRICC, // Branch to dest on icc condition + BRXCC, // Branch to dest on xcc condition (64-bit only). + BRFCC, // Branch to dest on fcc condition + SELECT_ICC, // Select between two values using the current ICC flags. + SELECT_XCC, // Select between two values using the current XCC flags. + SELECT_FCC, // Select between two values using the current FCC flags. + + Hi, + Lo, // Hi/Lo operations, typically on a global address. + + FTOI, // FP to Int within a FP register. + ITOF, // Int to FP within a FP register. + FTOX, // FP to Int64 within a FP register. + XTOF, // Int64 to FP within a FP register. + + CALL, // A call instruction. + RET_FLAG, // Return with a flag operand. + GLOBAL_BASE_REG, // Global base reg for PIC. + FLUSHW, // FLUSH register windows to stack. + + TLS_ADD, // For Thread Local Storage (TLS). + TLS_LD, + TLS_CALL +}; +} class SparcTargetLowering : public TargetLowering { const SparcSubtarget *Subtarget; @@ -211,6 +212,6 @@ MachineBasicBlock *expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB, unsigned BROpcode) const; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // SPARC_ISELLOWERING_H Index: llvm/lib/Target/Sparc/SparcInstrInfo.h =================================================================== --- llvm/lib/Target/Sparc/SparcInstrInfo.h +++ llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "SparcGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcSubtarget; @@ -102,6 +102,6 @@ bool expandPostRAPseudo(MachineInstr &MI) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ llvm/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -14,42 +14,44 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - class SparcMachineFunctionInfo : public MachineFunctionInfo { - virtual void anchor(); - private: - Register GlobalBaseReg; +class SparcMachineFunctionInfo : public MachineFunctionInfo { + virtual void anchor(); - /// VarArgsFrameOffset - Frame offset to start of varargs area. - int VarArgsFrameOffset; +private: + Register GlobalBaseReg; - /// SRetReturnReg - Holds the virtual register into which the sret - /// argument is passed. - Register SRetReturnReg; + /// VarArgsFrameOffset - Frame offset to start of varargs area. + int VarArgsFrameOffset; - /// IsLeafProc - True if the function is a leaf procedure. - bool IsLeafProc; - public: - SparcMachineFunctionInfo() + /// SRetReturnReg - Holds the virtual register into which the sret + /// argument is passed. + Register SRetReturnReg; + + /// IsLeafProc - True if the function is a leaf procedure. + bool IsLeafProc; + +public: + SparcMachineFunctionInfo() : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} - explicit SparcMachineFunctionInfo(MachineFunction &MF) + explicit SparcMachineFunctionInfo(MachineFunction &MF) : GlobalBaseReg(0), VarArgsFrameOffset(0), SRetReturnReg(0), IsLeafProc(false) {} - Register getGlobalBaseReg() const { return GlobalBaseReg; } - void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } + Register getGlobalBaseReg() const { return GlobalBaseReg; } + void setGlobalBaseReg(Register Reg) { GlobalBaseReg = Reg; } - int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } - void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; } + int getVarArgsFrameOffset() const { return VarArgsFrameOffset; } + void setVarArgsFrameOffset(int Offset) { VarArgsFrameOffset = Offset; } - Register getSRetReturnReg() const { return SRetReturnReg; } - void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } + Register getSRetReturnReg() const { return SRetReturnReg; } + void setSRetReturnReg(Register Reg) { SRetReturnReg = Reg; } - void setLeafProc(bool rhs) { IsLeafProc = rhs; } - bool isLeafProc() const { return IsLeafProc; } - }; -} + void setLeafProc(bool rhs) { IsLeafProc = rhs; } + bool isLeafProc() const { return IsLeafProc; } +}; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcRegisterInfo.h =================================================================== --- llvm/lib/Target/Sparc/SparcRegisterInfo.h +++ llvm/lib/Target/Sparc/SparcRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "SparcGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct SparcRegisterInfo : public SparcGenRegisterInfo { SparcRegisterInfo(); @@ -44,6 +44,6 @@ }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcSubtarget.h =================================================================== --- llvm/lib/Target/Sparc/SparcSubtarget.h +++ llvm/lib/Target/Sparc/SparcSubtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "SparcGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class SparcSubtarget : public SparcGenSubtargetInfo { @@ -120,6 +120,6 @@ bool isTargetLinux() const { return TargetTriple.isOSLinux(); } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcTargetMachine.h =================================================================== --- llvm/lib/Target/Sparc/SparcTargetMachine.h +++ llvm/lib/Target/Sparc/SparcTargetMachine.h @@ -17,7 +17,7 @@ #include "SparcSubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SparcTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -73,6 +73,6 @@ CodeGenOpt::Level OL, bool JIT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/SparcTargetObjectFile.h =================================================================== --- llvm/lib/Target/Sparc/SparcTargetObjectFile.h +++ llvm/lib/Target/Sparc/SparcTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCContext; class TargetMachine; @@ -31,6 +31,6 @@ MCStreamer &Streamer) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.h =================================================================== --- llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.h +++ llvm/lib/Target/Sparc/TargetInfo/SparcTargetInfo.h @@ -9,7 +9,9 @@ #ifndef LLVM_LIB_TARGET_SPARC_TARGETINFO_SPARCTARGETINFO_H #define LLVM_LIB_TARGET_SPARC_TARGETINFO_SPARCTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -17,6 +19,6 @@ Target &getTheSparcV9Target(); Target &getTheSparcelTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SPARC_TARGETINFO_SPARCTARGETINFO_H Index: llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h =================================================================== --- llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h +++ llvm/lib/Target/SystemZ/MCTargetDesc/SystemZInstPrinter.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCInstPrinter.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCOperand; @@ -82,6 +82,6 @@ void printCond4Operand(const MCInst *MI, int OpNum, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZINSTPRINTER_H Index: llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h =================================================================== --- llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h +++ llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCAsmInfoELF.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class SystemZMCAsmInfo : public MCAsmInfoELF { @@ -20,6 +20,6 @@ explicit SystemZMCAsmInfo(const Triple &TT); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h =================================================================== --- llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h +++ llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCFixups.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SystemZ { enum FixupKind { // These correspond directly to R_390_* relocations. @@ -26,6 +26,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // end namespace SystemZ -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h =================================================================== --- llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h +++ llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -91,7 +92,7 @@ const MCTargetOptions &Options); std::unique_ptr createSystemZObjectWriter(uint8_t OSABI); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. Index: llvm/lib/Target/SystemZ/SystemZ.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZ.h +++ llvm/lib/Target/SystemZ/SystemZ.h @@ -17,7 +17,7 @@ #include "MCTargetDesc/SystemZMCTargetDesc.h" #include "llvm/Support/CodeGen.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZTargetMachine; class FunctionPass; @@ -196,6 +196,6 @@ FunctionPass *createSystemZCopyPhysRegsPass(SystemZTargetMachine &TM); FunctionPass *createSystemZPostRewritePass(SystemZTargetMachine &TM); FunctionPass *createSystemZTDCPass(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZAsmPrinter.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZAsmPrinter.h +++ llvm/lib/Target/SystemZ/SystemZAsmPrinter.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/StackMaps.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCStreamer; class MachineBasicBlock; class MachineInstr; @@ -50,6 +50,6 @@ void LowerSTACKMAP(const MachineInstr &MI); void LowerPATCHPOINT(const MachineInstr &MI, SystemZMCInstLower &Lower); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZCallingConv.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZCallingConv.h +++ llvm/lib/Target/SystemZ/SystemZCallingConv.h @@ -13,7 +13,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/MC/MCRegisterInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SystemZ { const unsigned NumArgGPRs = 5; extern const MCPhysReg ArgGPRs[NumArgGPRs]; @@ -131,6 +131,6 @@ return false; } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZConstantPoolValue.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZConstantPoolValue.h +++ llvm/lib/Target/SystemZ/SystemZConstantPoolValue.h @@ -12,7 +12,7 @@ #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GlobalValue; @@ -52,6 +52,6 @@ SystemZCP::SystemZCPModifier getModifier() const { return Modifier; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp +++ llvm/lib/Target/SystemZ/SystemZCopyPhysRegs.cpp @@ -27,8 +27,8 @@ #define SYSTEMZ_COPYPHYSREGS_NAME "SystemZ Copy Physregs" -namespace llvm { - void initializeSystemZCopyPhysRegsPass(PassRegistry&); +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeSystemZCopyPhysRegsPass(PassRegistry &); } namespace { Index: llvm/lib/Target/SystemZ/SystemZFrameLowering.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZFrameLowering.h +++ llvm/lib/Target/SystemZ/SystemZFrameLowering.h @@ -14,7 +14,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZTargetMachine; class SystemZSubtarget; @@ -71,6 +71,6 @@ return usePackedStack(MF) ? SystemZMC::CallFrameSize - 8 : 0; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZHazardRecognizer.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZHazardRecognizer.h +++ llvm/lib/Target/SystemZ/SystemZHazardRecognizer.h @@ -39,7 +39,7 @@ #include "llvm/Support/raw_ostream.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// SystemZHazardRecognizer maintains the state for one MBB during scheduling. class SystemZHazardRecognizer : public ScheduleHazardRecognizer { @@ -156,6 +156,6 @@ void copyState(SystemZHazardRecognizer *Incoming); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif /* LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZHAZARDRECOGNIZER_H */ Index: llvm/lib/Target/SystemZ/SystemZISelLowering.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZISelLowering.h +++ llvm/lib/Target/SystemZ/SystemZISelLowering.h @@ -20,7 +20,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SystemZISD { enum NodeType : unsigned { FIRST_NUMBER = ISD::BUILTIN_OP_END, @@ -722,6 +722,6 @@ bool isVectorConstantLegal(const SystemZSubtarget &Subtarget); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZInstrBuilder.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZInstrBuilder.h +++ llvm/lib/Target/SystemZ/SystemZInstrBuilder.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// Add a BDX memory reference for frame object FI to MIB. static inline const MachineInstrBuilder & @@ -39,6 +39,6 @@ return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZInstrInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -25,7 +25,7 @@ #define GET_INSTRINFO_HEADER #include "SystemZGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZSubtarget; @@ -357,6 +357,6 @@ const MachineInstr &MIb) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZINSTRINFO_H Index: llvm/lib/Target/SystemZ/SystemZMCInstLower.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZMCInstLower.h +++ llvm/lib/Target/SystemZ/SystemZMCInstLower.h @@ -13,7 +13,7 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCInst; class MCOperand; class MachineInstr; @@ -38,6 +38,6 @@ const MCExpr *getExpr(const MachineOperand &MO, MCSymbolRefExpr::VariantKind Kind) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h +++ llvm/lib/Target/SystemZ/SystemZMachineFunctionInfo.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace SystemZ { // A struct to hold the low and high GPR registers to be saved/restored as @@ -95,6 +95,6 @@ void incNumLocalDynamicTLSAccesses() { ++NumLocalDynamics; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZMachineScheduler.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZMachineScheduler.h +++ llvm/lib/Target/SystemZ/SystemZMachineScheduler.h @@ -24,7 +24,7 @@ using namespace llvm; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// A MachineSchedStrategy implementation for SystemZ post RA scheduling. class SystemZPostRASchedStrategy : public MachineSchedStrategy { @@ -150,6 +150,6 @@ void releaseBottomNode(SUnit *SU) override {}; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZMACHINESCHEDULER_H Index: llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp +++ llvm/lib/Target/SystemZ/SystemZPostRewrite.cpp @@ -27,8 +27,8 @@ STATISTIC(MemFoldCopies, "Number of copies inserted before folded mem ops."); STATISTIC(LOCRMuxJumps, "Number of LOCRMux jump-sequences (lower is better)"); -namespace llvm { - void initializeSystemZPostRewritePass(PassRegistry&); +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeSystemZPostRewritePass(PassRegistry &); } namespace { Index: llvm/lib/Target/SystemZ/SystemZRegisterInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZRegisterInfo.h +++ llvm/lib/Target/SystemZ/SystemZRegisterInfo.h @@ -15,7 +15,7 @@ #define GET_REGINFO_HEADER #include "SystemZGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LiveIntervals; @@ -90,6 +90,6 @@ Register getFrameRegister(const MachineFunction &MF) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h +++ llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZTargetMachine; @@ -69,6 +69,6 @@ MachinePointerInfo SrcPtrInfo) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZSubtarget.h +++ llvm/lib/Target/SystemZ/SystemZSubtarget.h @@ -26,7 +26,7 @@ #define GET_SUBTARGETINFO_HEADER #include "SystemZGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class GlobalValue; class StringRef; @@ -249,6 +249,6 @@ bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/SystemZTDC.cpp =================================================================== --- llvm/lib/Target/SystemZ/SystemZTDC.cpp +++ llvm/lib/Target/SystemZ/SystemZTDC.cpp @@ -61,8 +61,8 @@ using namespace llvm; -namespace llvm { - void initializeSystemZTDCPassPass(PassRegistry&); +namespace llvm LLVM_LIBRARY_VISIBILITY { +void initializeSystemZTDCPassPass(PassRegistry &); } namespace { Index: llvm/lib/Target/SystemZ/SystemZTargetMachine.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetMachine.h +++ llvm/lib/Target/SystemZ/SystemZTargetMachine.h @@ -22,7 +22,7 @@ #include "llvm/Target/TargetMachine.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -53,6 +53,6 @@ bool targetSchedulesPostRAScheduling() const override { return true; }; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZTARGETMACHINE_H Index: llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h =================================================================== --- llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -13,7 +13,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class SystemZTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -117,6 +117,6 @@ /// @} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.h =================================================================== --- llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.h +++ llvm/lib/Target/SystemZ/TargetInfo/SystemZTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_SYSTEMZ_TARGETINFO_SYSTEMZTARGETINFO_H #define LLVM_LIB_TARGET_SYSTEMZ_TARGETINFO_SYSTEMZTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheSystemZTarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_SYSTEMZ_TARGETINFO_SYSTEMZTARGETINFO_H Index: llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h +++ llvm/lib/Target/VE/MCTargetDesc/VEFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace VE { enum Fixups { /// fixup_ve_reflong - 32-bit fixup corresponding to foo @@ -56,6 +56,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // namespace VE -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h +++ llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.h @@ -16,7 +16,7 @@ #include "VEMCTargetDesc.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VEInstPrinter : public MCInstPrinter { public: @@ -58,6 +58,6 @@ void printRDOperand(const MCInst *MI, int OpNum, const MCSubtargetInfo &STI, raw_ostream &OS); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp +++ llvm/lib/Target/VE/MCTargetDesc/VEInstPrinter.cpp @@ -25,11 +25,11 @@ // The generated AsmMatcher VEGenAsmWriter uses "VE" as the target // namespace. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace VE { using namespace VE; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR Index: llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.h +++ llvm/lib/Target/VE/MCTargetDesc/VEMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -26,6 +26,6 @@ explicit VEELFMCAsmInfo(const Triple &TheTriple); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_VE_MCTARGETDESC_VEMCASMINFO_H Index: llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h +++ llvm/lib/Target/VE/MCTargetDesc/VEMCExpr.h @@ -17,7 +17,7 @@ #include "VEFixupKinds.h" #include "llvm/MC/MCExpr.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class VEMCExpr : public MCTargetExpr { @@ -90,6 +90,6 @@ static VE::Fixups getFixupKind(VariantKind Kind); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h +++ llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.h @@ -13,11 +13,12 @@ #ifndef LLVM_LIB_TARGET_VE_MCTARGETDESC_VEMCTARGETDESC_H #define LLVM_LIB_TARGET_VE_MCTARGETDESC_VEMCTARGETDESC_H +#include "llvm/Support/Compiler.h" #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; class MCContext; @@ -38,7 +39,7 @@ const MCRegisterInfo &MRI, const MCTargetOptions &Options); std::unique_ptr createVEELFObjectWriter(uint8_t OSABI); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for VE registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.h =================================================================== --- llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.h +++ llvm/lib/Target/VE/MCTargetDesc/VETargetStreamer.h @@ -12,7 +12,7 @@ #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VETargetStreamer : public MCTargetStreamer { virtual void anchor(); @@ -42,6 +42,6 @@ void emitVERegisterIgnore(unsigned reg) override {} void emitVERegisterScratch(unsigned reg) override {} }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/TargetInfo/VETargetInfo.h =================================================================== --- llvm/lib/Target/VE/TargetInfo/VETargetInfo.h +++ llvm/lib/Target/VE/TargetInfo/VETargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_VE_TARGETINFO_VETARGETINFO_H #define LLVM_LIB_TARGET_VE_TARGETINFO_VETARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheVETarget(); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_VE_TARGETINFO_VETARGETINFO_H Index: llvm/lib/Target/VE/VE.h =================================================================== --- llvm/lib/Target/VE/VE.h +++ llvm/lib/Target/VE/VE.h @@ -19,7 +19,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; class VETargetMachine; class formatted_raw_ostream; @@ -33,9 +33,9 @@ void LowerVEMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, AsmPrinter &AP); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Enums corresponding to VE condition codes, both icc's and fcc's. These // values must be kept in sync with the ones in the .td file. namespace VECC { @@ -371,5 +371,5 @@ inline unsigned M0(unsigned Val) { return Val + 64; } inline unsigned M1(unsigned Val) { return Val; } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VEFrameLowering.h =================================================================== --- llvm/lib/Target/VE/VEFrameLowering.h +++ llvm/lib/Target/VE/VEFrameLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VESubtarget; class VEFrameLowering : public TargetFrameLowering { @@ -83,6 +83,6 @@ MachineBasicBlock::iterator MBBI) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VEISelLowering.h =================================================================== --- llvm/lib/Target/VE/VEISelLowering.h +++ llvm/lib/Target/VE/VEISelLowering.h @@ -17,7 +17,7 @@ #include "VE.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VESubtarget; namespace VEISD { @@ -214,6 +214,6 @@ /// } Target Optimization }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // VE_ISELLOWERING_H Index: llvm/lib/Target/VE/VEInstrBuilder.h =================================================================== --- llvm/lib/Target/VE/VEInstrBuilder.h +++ llvm/lib/Target/VE/VEInstrBuilder.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// addFrameReference - This function is used to add a reference to the base of /// an abstract object on the stack frame of the current function. This @@ -36,6 +36,6 @@ return MIB.addFrameIndex(FI).addImm(Offset); } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VEInstrInfo.h =================================================================== --- llvm/lib/Target/VE/VEInstrInfo.h +++ llvm/lib/Target/VE/VEInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "VEGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VESubtarget; @@ -116,6 +116,6 @@ bool expandGetStackTopPseudo(MachineInstr &MI) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VEMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/VE/VEMachineFunctionInfo.h +++ llvm/lib/Target/VE/VEMachineFunctionInfo.h @@ -14,7 +14,7 @@ #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VEMachineFunctionInfo : public MachineFunctionInfo { virtual void anchor(); @@ -43,6 +43,6 @@ void setLeafProc(bool rhs) { IsLeafProc = rhs; } bool isLeafProc() const { return IsLeafProc; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VERegisterInfo.h =================================================================== --- llvm/lib/Target/VE/VERegisterInfo.h +++ llvm/lib/Target/VE/VERegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "VEGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct VERegisterInfo : public VEGenRegisterInfo { public: VERegisterInfo(); @@ -42,6 +42,6 @@ Register getFrameRegister(const MachineFunction &MF) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VESubtarget.h =================================================================== --- llvm/lib/Target/VE/VESubtarget.h +++ llvm/lib/Target/VE/VESubtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "VEGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class VESubtarget : public VEGenSubtargetInfo { @@ -81,6 +81,6 @@ bool isTargetLinux() const { return TargetTriple.isOSLinux(); } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VETargetMachine.h =================================================================== --- llvm/lib/Target/VE/VETargetMachine.h +++ llvm/lib/Target/VE/VETargetMachine.h @@ -17,7 +17,7 @@ #include "VESubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VETargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -54,6 +54,6 @@ unsigned getSjLjDataSize() const override { return 64; } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/VE/VETargetTransformInfo.h =================================================================== --- llvm/lib/Target/VE/VETargetTransformInfo.h +++ llvm/lib/Target/VE/VETargetTransformInfo.h @@ -21,7 +21,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class VETTIImpl : public BasicTTIImplBase { using BaseT = BasicTTIImplBase; @@ -64,6 +64,6 @@ } }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_VE_VETARGETTRANSFORMINFO_H Index: llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h =================================================================== --- llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h +++ llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyFixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace WebAssembly { enum Fixups { fixup_sleb128_i32 = FirstTargetFixupKind, // 32-bit signed @@ -24,6 +24,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h =================================================================== --- llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h +++ llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h @@ -19,7 +19,7 @@ #include "llvm/MC/MCInstPrinter.h" #include "llvm/Support/MachineValueType.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCSubtargetInfo; @@ -63,6 +63,6 @@ } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h +++ llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCAsmInfoWasm.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; @@ -27,6 +27,6 @@ ~WebAssemblyMCAsmInfo() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h =================================================================== --- llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h +++ llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.h @@ -20,7 +20,7 @@ #include "llvm/Support/DataTypes.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCAsmBackend; class MCCodeEmitter; @@ -113,7 +113,7 @@ } // end namespace WebAssemblyII -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for WebAssembly registers. This defines a mapping from // register name to register number. @@ -126,7 +126,7 @@ #define GET_INSTRINFO_ENUM #include "WebAssemblyGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace WebAssembly { /// Used as immediate MachineOperands for block signatures @@ -446,6 +446,6 @@ } } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h =================================================================== --- llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h +++ llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h @@ -19,7 +19,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/Support/MachineValueType.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCSymbolWasm; @@ -114,6 +114,6 @@ void emitExportName(const MCSymbolWasm *, StringRef) override {} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h +++ llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h @@ -14,7 +14,9 @@ #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_TARGETINFO_WEBASSEMBLYTARGETINFO_H #define LLVM_LIB_TARGET_WEBASSEMBLY_TARGETINFO_WEBASSEMBLYTARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; @@ -28,6 +30,6 @@ } // namespace WebAssembly -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_WEBASSEMBLY_TARGETINFO_WEBASSEMBLYTARGETINFO_H Index: llvm/lib/Target/WebAssembly/WebAssembly.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssembly.h +++ llvm/lib/Target/WebAssembly/WebAssembly.h @@ -18,7 +18,7 @@ #include "llvm/PassRegistry.h" #include "llvm/Support/CodeGen.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyTargetMachine; class ModulePass; @@ -94,6 +94,6 @@ }; } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h +++ llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyTargetStreamer; class LLVM_LIBRARY_VISIBILITY WebAssemblyAsmPrinter final : public AsmPrinter { @@ -82,6 +82,6 @@ bool &InvokeDetected); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h +++ llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.h @@ -17,7 +17,7 @@ #include "llvm/ADT/SmallVector.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstr; @@ -33,6 +33,6 @@ void replaceWithLocal(unsigned LocalId); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyExceptionInfo.h @@ -18,7 +18,7 @@ #include "llvm/ADT/SetVector.h" #include "llvm/CodeGen/MachineFunctionPass.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineDominatorTree; class MachineDominanceFrontier; @@ -165,6 +165,6 @@ void print(raw_ostream &OS, const Module *M = nullptr) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h +++ llvm/lib/Target/WebAssembly/WebAssemblyFrameLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyFrameLowering final : public TargetFrameLowering { public: @@ -69,6 +69,6 @@ bool needsSPWriteback(const MachineFunction &MF) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h +++ llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace WebAssemblyISD { @@ -131,6 +131,6 @@ const TargetLibraryInfo *libInfo); } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.h @@ -25,7 +25,7 @@ #define GET_INSTRINFO_OPERAND_ENUM #include "WebAssemblyGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace WebAssembly { @@ -70,6 +70,6 @@ getSerializableTargetIndices() const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h +++ llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.h @@ -19,7 +19,7 @@ #include "llvm/MC/MCInst.h" #include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyAsmPrinter; class MCContext; class MCSymbol; @@ -42,6 +42,6 @@ : Ctx(ctx), Printer(printer) {} void lower(const MachineInstr *MI, MCInst &OutMI) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h @@ -21,7 +21,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCSymbolWasm.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace yaml { struct WebAssemblyFunctionInfo; @@ -190,6 +190,6 @@ } // end namespace yaml -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "WebAssemblyGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineFunction; class RegScavenger; @@ -48,6 +48,6 @@ const uint32_t *getNoPreservedMask() const override { return nullptr; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.h +++ llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.h @@ -18,7 +18,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/RuntimeLibcalls.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblySubtarget; @@ -32,6 +32,6 @@ SmallVectorImpl &Rets, SmallVectorImpl &Params); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblySelectionDAGInfo.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblySelectionDAGInfo final : public SelectionDAGTargetInfo { public: @@ -40,6 +40,6 @@ MachinePointerInfo DstPtrInfo) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblySortRegion.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblySortRegion.h +++ llvm/lib/Target/WebAssembly/WebAssemblySortRegion.h @@ -18,7 +18,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/iterator_range.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineLoop; @@ -86,6 +86,6 @@ } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblySortRegion.cpp =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblySortRegion.cpp +++ llvm/lib/Target/WebAssembly/WebAssemblySortRegion.cpp @@ -5,14 +5,14 @@ using namespace llvm; using namespace WebAssembly; -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace WebAssembly { template <> bool ConcreteSortRegion::isLoop() const { return true; } } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY const SortRegion *SortRegionInfo::getRegionFor(const MachineBasicBlock *MBB) { const auto *ML = MLI.getLoopFor(MBB); Index: llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h +++ llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -26,7 +26,7 @@ #define GET_SUBTARGETINFO_HEADER #include "WebAssemblyGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Defined in WebAssemblyGenSubtargetInfo.inc. extern const SubtargetFeatureKV @@ -108,6 +108,6 @@ void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.h @@ -18,7 +18,7 @@ #include "WebAssemblySubtarget.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyTargetMachine final : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -59,6 +59,6 @@ SMRange &SourceRange) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.h +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.h @@ -17,13 +17,13 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyTargetObjectFile final : public TargetLoweringObjectFileWasm { public: void Initialize(MCContext &Ctx, const TargetMachine &TM) override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -23,7 +23,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class WebAssemblyTTIImpl final : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -72,6 +72,6 @@ const Function *Callee) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h =================================================================== --- llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h +++ llvm/lib/Target/WebAssembly/WebAssemblyUtilities.h @@ -15,7 +15,9 @@ #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYUTILITIES_H #define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYUTILITIES_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineBasicBlock; class MachineInstr; @@ -52,6 +54,6 @@ } // end namespace WebAssembly -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/AsmParser/X86AsmParserCommon.h =================================================================== --- llvm/lib/Target/X86/AsmParser/X86AsmParserCommon.h +++ llvm/lib/Target/X86/AsmParser/X86AsmParserCommon.h @@ -11,7 +11,7 @@ #include "llvm/Support/MathExtras.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { inline bool isImmSExti16i8Value(uint64_t Value) { return isInt<8>(Value) || @@ -39,6 +39,6 @@ return isUInt<4>(Value); } -} // End of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/AsmParser/X86Operand.h =================================================================== --- llvm/lib/Target/X86/AsmParser/X86Operand.h +++ llvm/lib/Target/X86/AsmParser/X86Operand.h @@ -22,7 +22,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// X86Operand - Instances of this class represent a parsed X86 machine /// instruction. @@ -713,6 +713,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H Index: llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp =================================================================== --- llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -1649,7 +1649,7 @@ return 0; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { // Fill-ins to make the compiler happy. These constants are never actually // assigned; they are just filler to make an automatically-generated switch @@ -1665,7 +1665,7 @@ }; } // namespace X86 -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static bool translateInstruction(MCInst &target, InternalInstruction &source, Index: llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h =================================================================== --- llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h +++ llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h @@ -18,7 +18,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/Support/X86DisassemblerDecoderCommon.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace X86Disassembler { // Accessor functions for various fields of an Intel instruction @@ -642,6 +642,6 @@ }; } // namespace X86Disassembler -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/ImmutableGraph.h =================================================================== --- llvm/lib/Target/X86/ImmutableGraph.h +++ llvm/lib/Target/X86/ImmutableGraph.h @@ -33,7 +33,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template class ImmutableGraph { using Traits = GraphTraits *>; @@ -440,6 +440,6 @@ static typename GraphT::size_type size(GraphT *G) { return G->nodes_size(); } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_IMMUTABLEGRAPH_H Index: llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h +++ llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.h @@ -15,7 +15,7 @@ #include "X86InstPrinterCommon.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86ATTInstPrinter final : public X86InstPrinterCommon { public: @@ -114,6 +114,6 @@ bool HasCustomInstComment; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H Index: llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -21,7 +21,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace X86 { // Enums for memory operand decoding. Each memory operand is represented with @@ -1221,6 +1221,6 @@ } } -} // end namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h +++ llvm/lib/Target/X86/MCTargetDesc/X86FixupKinds.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCFixup.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace X86 { enum Fixups { reloc_riprel_4byte = FirstTargetFixupKind, // 32-bit rip-relative @@ -35,6 +35,6 @@ NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86InstComments.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86InstComments.h +++ llvm/lib/Target/X86/MCTargetDesc/X86InstComments.h @@ -14,13 +14,15 @@ #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86INSTCOMMENTS_H #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86INSTCOMMENTS_H -namespace llvm { +#include "llvm/Support/Compiler.h" - class MCInst; - class MCInstrInfo; - class raw_ostream; - bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, - const MCInstrInfo &MCII); -} +namespace llvm LLVM_LIBRARY_VISIBILITY { + +class MCInst; +class MCInstrInfo; +class raw_ostream; +bool EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, + const MCInstrInfo &MCII); +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h +++ llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h @@ -16,7 +16,7 @@ #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86InstPrinterCommon : public MCInstPrinter { public: @@ -38,6 +38,6 @@ void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86ATTINSTPRINTER_H Index: llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h +++ llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.h @@ -16,7 +16,7 @@ #include "X86InstPrinterCommon.h" #include "llvm/Support/raw_ostream.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86IntelInstPrinter final : public X86InstPrinterCommon { public: @@ -133,6 +133,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_MCTARGETDESC_X86INTELINSTPRINTER_H Index: llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h +++ llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h @@ -17,7 +17,7 @@ #include "llvm/MC/MCAsmInfoDarwin.h" #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class X86MCAsmInfoDarwin : public MCAsmInfoDarwin { @@ -61,6 +61,6 @@ public: explicit X86MCAsmInfoGNUCOFF(const Triple &Triple); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86MCExpr.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86MCExpr.h +++ llvm/lib/Target/X86/MCTargetDesc/X86MCExpr.h @@ -20,7 +20,7 @@ #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86MCExpr : public MCTargetExpr { @@ -74,6 +74,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h +++ llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h @@ -13,10 +13,12 @@ #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H +#include "llvm/Support/Compiler.h" + #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class formatted_raw_ostream; class MCAsmBackend; class MCCodeEmitter; @@ -124,8 +126,7 @@ MCRegister getX86SubSuperRegisterOrZero(MCRegister, unsigned, bool High = false); -} // End llvm namespace - +} // namespace LLVM_LIBRARY_VISIBILITY // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. Index: llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -381,7 +381,7 @@ return llvm::createMCRelocationInfo(TheTriple, Ctx); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace X86_MC { class X86MCInstrAnalysis : public MCInstrAnalysis { @@ -557,7 +557,7 @@ } // end of namespace X86_MC -} // end of namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static MCInstrAnalysis *createX86MCInstrAnalysis(const MCInstrInfo *Info) { return new X86_MC::X86MCInstrAnalysis(Info); Index: llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.h +++ llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.h @@ -14,13 +14,15 @@ #ifndef LLVM_LIB_TARGET_X86_UTILS_X86SHUFFLEDECODE_H #define LLVM_LIB_TARGET_X86_UTILS_X86SHUFFLEDECODE_H +#include "llvm/Support/Compiler.h" + #include //===----------------------------------------------------------------------===// // Vector Mask Decoding //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class APInt; template class ArrayRef; template class SmallVectorImpl; @@ -161,6 +163,6 @@ /// Decode a VPERMT2 W/D/Q/PS/PD mask from a raw array of constants. void DecodeVPERMV3Mask(ArrayRef RawMask, const APInt &UndefElts, SmallVectorImpl &ShuffleMask); -} // llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.cpp =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.cpp +++ llvm/lib/Target/X86/MCTargetDesc/X86ShuffleDecode.cpp @@ -20,7 +20,7 @@ // Vector Mask Decoding //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { void DecodeINSERTPSMask(unsigned Imm, SmallVectorImpl &ShuffleMask) { // Defaults the copying the dest value. @@ -568,4 +568,4 @@ } } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/X86/MCTargetDesc/X86TargetStreamer.h =================================================================== --- llvm/lib/Target/X86/MCTargetDesc/X86TargetStreamer.h +++ llvm/lib/Target/X86/MCTargetDesc/X86TargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// X86 target streamer implementing x86-only assembly directives. class X86TargetStreamer : public MCTargetStreamer { @@ -29,6 +29,6 @@ virtual bool emitFPOSetFrame(unsigned Reg, SMLoc L = {}) = 0; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/TargetInfo/X86TargetInfo.h =================================================================== --- llvm/lib/Target/X86/TargetInfo/X86TargetInfo.h +++ llvm/lib/Target/X86/TargetInfo/X86TargetInfo.h @@ -9,13 +9,15 @@ #ifndef LLVM_LIB_TARGET_X86_TARGETINFO_X86TARGETINFO_H #define LLVM_LIB_TARGET_X86_TARGETINFO_X86TARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheX86_32Target(); Target &getTheX86_64Target(); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_TARGETINFO_X86TARGETINFO_H Index: llvm/lib/Target/X86/X86.h =================================================================== --- llvm/lib/Target/X86/X86.h +++ llvm/lib/Target/X86/X86.h @@ -15,8 +15,9 @@ #define LLVM_LIB_TARGET_X86_X86_H #include "llvm/Support/CodeGen.h" +#include "llvm/Support/Compiler.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class FunctionPass; class InstructionSelector; @@ -181,6 +182,6 @@ }; } // End X86AS namespace -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86AsmPrinter.h =================================================================== --- llvm/lib/Target/X86/X86AsmPrinter.h +++ llvm/lib/Target/X86/X86AsmPrinter.h @@ -18,7 +18,7 @@ class X86MCInstLower; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MCCodeEmitter; class MCStreamer; class X86Subtarget; @@ -150,6 +150,6 @@ void emitFunctionBodyEnd() override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86CallLowering.h =================================================================== --- llvm/lib/Target/X86/X86CallLowering.h +++ llvm/lib/Target/X86/X86CallLowering.h @@ -17,7 +17,7 @@ #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template class ArrayRef; class DataLayout; @@ -49,6 +49,6 @@ SplitArgTy SplitArg) const; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_X86CALLLOWERING_H Index: llvm/lib/Target/X86/X86CallingConv.h =================================================================== --- llvm/lib/Target/X86/X86CallingConv.h +++ llvm/lib/Target/X86/X86CallingConv.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/IR/CallingConv.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { bool RetCC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, @@ -27,7 +27,7 @@ bool CC_X86(unsigned ValNo, MVT ValVT, MVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State); -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86FastISel.cpp =================================================================== --- llvm/lib/Target/X86/X86FastISel.cpp +++ llvm/lib/Target/X86/X86FastISel.cpp @@ -4027,10 +4027,9 @@ return ResultReg; } - -namespace llvm { - FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo, - const TargetLibraryInfo *libInfo) { - return new X86FastISel(funcInfo, libInfo); - } +namespace llvm LLVM_LIBRARY_VISIBILITY { +FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo, + const TargetLibraryInfo *libInfo) { + return new X86FastISel(funcInfo, libInfo); } +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/X86/X86FrameLowering.h =================================================================== --- llvm/lib/Target/X86/X86FrameLowering.h +++ llvm/lib/Target/X86/X86FrameLowering.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Support/TypeSize.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class MachineInstrBuilder; class MCCFIInstruction; @@ -252,6 +252,6 @@ MachineInstr *CatchRet) const; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86ISelLowering.h =================================================================== --- llvm/lib/Target/X86/X86ISelLowering.h +++ llvm/lib/Target/X86/X86ISelLowering.h @@ -16,836 +16,836 @@ #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { - class X86Subtarget; - class X86TargetMachine; - - namespace X86ISD { - // X86 Specific DAG Nodes - enum NodeType : unsigned { - // Start the numbering where the builtin ops leave off. - FIRST_NUMBER = ISD::BUILTIN_OP_END, - - /// Bit scan forward. - BSF, - /// Bit scan reverse. - BSR, - - /// X86 funnel/double shift i16 instructions. These correspond to - /// X86::SHLDW and X86::SHRDW instructions which have different amt - /// modulo rules to generic funnel shifts. - /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD. - FSHL, - FSHR, - - /// Bitwise logical AND of floating point values. This corresponds - /// to X86::ANDPS or X86::ANDPD. - FAND, - - /// Bitwise logical OR of floating point values. This corresponds - /// to X86::ORPS or X86::ORPD. - FOR, - - /// Bitwise logical XOR of floating point values. This corresponds - /// to X86::XORPS or X86::XORPD. - FXOR, - - /// Bitwise logical ANDNOT of floating point values. This - /// corresponds to X86::ANDNPS or X86::ANDNPD. - FANDN, - - /// These operations represent an abstract X86 call - /// instruction, which includes a bunch of information. In particular the - /// operands of these node are: - /// - /// #0 - The incoming token chain - /// #1 - The callee - /// #2 - The number of arg bytes the caller pushes on the stack. - /// #3 - The number of arg bytes the callee pops off the stack. - /// #4 - The value to pass in AL/AX/EAX (optional) - /// #5 - The value to pass in DL/DX/EDX (optional) - /// - /// The result values of these nodes are: - /// - /// #0 - The outgoing token chain - /// #1 - The first register result value (optional) - /// #2 - The second register result value (optional) - /// - CALL, - - /// Same as call except it adds the NoTrack prefix. - NT_CALL, - - /// X86 compare and logical compare instructions. - CMP, - FCMP, - COMI, - UCOMI, - - /// X86 bit-test instructions. - BT, - - /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS - /// operand, usually produced by a CMP instruction. - SETCC, - - /// X86 Select - SELECTS, - - // Same as SETCC except it's materialized with a sbb and the value is all - // one's or all zero's. - SETCC_CARRY, // R = carry_bit ? ~0 : 0 - - /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. - /// Operands are two FP values to compare; result is a mask of - /// 0s or 1s. Generally DTRT for C/C++ with NaNs. - FSETCC, - - /// X86 FP SETCC, similar to above, but with output as an i1 mask and - /// and a version with SAE. - FSETCCM, - FSETCCM_SAE, - - /// X86 conditional moves. Operand 0 and operand 1 are the two values - /// to select from. Operand 2 is the condition code, and operand 3 is the - /// flag operand produced by a CMP or TEST instruction. - CMOV, - - /// X86 conditional branches. Operand 0 is the chain operand, operand 1 - /// is the block to branch if condition is true, operand 2 is the - /// condition code, and operand 3 is the flag operand produced by a CMP - /// or TEST instruction. - BRCOND, - - /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and - /// operand 1 is the target address. - NT_BRIND, - - /// Return with a flag operand. Operand 0 is the chain operand, operand - /// 1 is the number of bytes of stack to pop. - RET_FLAG, - - /// Return from interrupt. Operand 0 is the number of bytes to pop. - IRET, - - /// Repeat fill, corresponds to X86::REP_STOSx. - REP_STOS, - - /// Repeat move, corresponds to X86::REP_MOVSx. - REP_MOVS, - - /// On Darwin, this node represents the result of the popl - /// at function entry, used for PIC code. - GlobalBaseReg, - - /// A wrapper node for TargetConstantPool, TargetJumpTable, - /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, - /// MCSymbol and TargetBlockAddress. - Wrapper, - - /// Special wrapper used under X86-64 PIC mode for RIP - /// relative displacements. - WrapperRIP, - - /// Copies a 64-bit value from an MMX vector to the low word - /// of an XMM vector, with the high word zero filled. - MOVQ2DQ, - - /// Copies a 64-bit value from the low word of an XMM vector - /// to an MMX vector. - MOVDQ2Q, - - /// Copies a 32-bit value from the low word of a MMX - /// vector to a GPR. - MMX_MOVD2W, - - /// Copies a GPR into the low 32-bit word of a MMX vector - /// and zero out the high word. - MMX_MOVW2D, - - /// Extract an 8-bit value from a vector and zero extend it to - /// i32, corresponds to X86::PEXTRB. - PEXTRB, - - /// Extract a 16-bit value from a vector and zero extend it to - /// i32, corresponds to X86::PEXTRW. - PEXTRW, - - /// Insert any element of a 4 x float vector into any element - /// of a destination 4 x floatvector. - INSERTPS, - - /// Insert the lower 8-bits of a 32-bit value to a vector, - /// corresponds to X86::PINSRB. - PINSRB, - - /// Insert the lower 16-bits of a 32-bit value to a vector, - /// corresponds to X86::PINSRW. - PINSRW, - - /// Shuffle 16 8-bit values within a vector. - PSHUFB, - - /// Compute Sum of Absolute Differences. - PSADBW, - /// Compute Double Block Packed Sum-Absolute-Differences - DBPSADBW, - - /// Bitwise Logical AND NOT of Packed FP values. - ANDNP, - - /// Blend where the selector is an immediate. - BLENDI, - - /// Dynamic (non-constant condition) vector blend where only the sign bits - /// of the condition elements are used. This is used to enforce that the - /// condition mask is not valid for generic VSELECT optimizations. This - /// is also used to implement the intrinsics. - /// Operands are in VSELECT order: MASK, TRUE, FALSE - BLENDV, - - /// Combined add and sub on an FP vector. - ADDSUB, - - // FP vector ops with rounding mode. - FADD_RND, - FADDS, - FADDS_RND, - FSUB_RND, - FSUBS, - FSUBS_RND, - FMUL_RND, - FMULS, - FMULS_RND, - FDIV_RND, - FDIVS, - FDIVS_RND, - FMAX_SAE, - FMAXS_SAE, - FMIN_SAE, - FMINS_SAE, - FSQRT_RND, - FSQRTS, - FSQRTS_RND, - - // FP vector get exponent. - FGETEXP, - FGETEXP_SAE, - FGETEXPS, - FGETEXPS_SAE, - // Extract Normalized Mantissas. - VGETMANT, - VGETMANT_SAE, - VGETMANTS, - VGETMANTS_SAE, - // FP Scale. - SCALEF, - SCALEF_RND, - SCALEFS, - SCALEFS_RND, - - // Unsigned Integer average. - AVG, - - /// Integer horizontal add/sub. - HADD, - HSUB, - - /// Floating point horizontal add/sub. - FHADD, - FHSUB, - - // Detect Conflicts Within a Vector - CONFLICT, - - /// Floating point max and min. - FMAX, - FMIN, - - /// Commutative FMIN and FMAX. - FMAXC, - FMINC, - - /// Scalar intrinsic floating point max and min. - FMAXS, - FMINS, - - /// Floating point reciprocal-sqrt and reciprocal approximation. - /// Note that these typically require refinement - /// in order to obtain suitable precision. - FRSQRT, - FRCP, - - // AVX-512 reciprocal approximations with a little more precision. - RSQRT14, - RSQRT14S, - RCP14, - RCP14S, - - // Thread Local Storage. - TLSADDR, - - // Thread Local Storage. A call to get the start address - // of the TLS block for the current module. - TLSBASEADDR, - - // Thread Local Storage. When calling to an OS provided - // thunk at the address from an earlier relocation. - TLSCALL, - - // Exception Handling helpers. - EH_RETURN, - - // SjLj exception handling setjmp. - EH_SJLJ_SETJMP, - - // SjLj exception handling longjmp. - EH_SJLJ_LONGJMP, - - // SjLj exception handling dispatch. - EH_SJLJ_SETUP_DISPATCH, - - /// Tail call return. See X86TargetLowering::LowerCall for - /// the list of operands. - TC_RETURN, - - // Vector move to low scalar and zero higher vector elements. - VZEXT_MOVL, - - // Vector integer truncate. - VTRUNC, - // Vector integer truncate with unsigned/signed saturation. - VTRUNCUS, - VTRUNCS, - - // Masked version of the above. Used when less than a 128-bit result is - // produced since the mask only applies to the lower elements and can't - // be represented by a select. - // SRC, PASSTHRU, MASK - VMTRUNC, - VMTRUNCUS, - VMTRUNCS, - - // Vector FP extend. - VFPEXT, - VFPEXT_SAE, - VFPEXTS, - VFPEXTS_SAE, - - // Vector FP round. - VFPROUND, - VFPROUND_RND, - VFPROUNDS, - VFPROUNDS_RND, - - // Masked version of above. Used for v2f64->v4f32. - // SRC, PASSTHRU, MASK - VMFPROUND, - - // 128-bit vector logical left / right shift - VSHLDQ, - VSRLDQ, - - // Vector shift elements - VSHL, - VSRL, - VSRA, - - // Vector variable shift - VSHLV, - VSRLV, - VSRAV, - - // Vector shift elements by immediate - VSHLI, - VSRLI, - VSRAI, - - // Shifts of mask registers. - KSHIFTL, - KSHIFTR, - - // Bit rotate by immediate - VROTLI, - VROTRI, - - // Vector packed double/float comparison. - CMPP, - - // Vector integer comparisons. - PCMPEQ, - PCMPGT, - - // v8i16 Horizontal minimum and position. - PHMINPOS, - - MULTISHIFT, - - /// Vector comparison generating mask bits for fp and - /// integer signed and unsigned data types. - CMPM, - // Vector mask comparison generating mask bits for FP values. - CMPMM, - // Vector mask comparison with SAE for FP values. - CMPMM_SAE, - - // Arithmetic operations with FLAGS results. - ADD, - SUB, - ADC, - SBB, - SMUL, - UMUL, - OR, - XOR, - AND, - - // Bit field extract. - BEXTR, - BEXTRI, - - // Zero High Bits Starting with Specified Bit Position. - BZHI, - - // Parallel extract and deposit. - PDEP, - PEXT, - - // X86-specific multiply by immediate. - MUL_IMM, - - // Vector sign bit extraction. - MOVMSK, - - // Vector bitwise comparisons. - PTEST, - - // Vector packed fp sign bitwise comparisons. - TESTP, - - // OR/AND test for masks. - KORTEST, - KTEST, - - // ADD for masks. - KADD, - - // Several flavors of instructions with vector shuffle behaviors. - // Saturated signed/unnsigned packing. - PACKSS, - PACKUS, - // Intra-lane alignr. - PALIGNR, - // AVX512 inter-lane alignr. - VALIGN, - PSHUFD, - PSHUFHW, - PSHUFLW, - SHUFP, - // VBMI2 Concat & Shift. - VSHLD, - VSHRD, - VSHLDV, - VSHRDV, - // Shuffle Packed Values at 128-bit granularity. - SHUF128, - MOVDDUP, - MOVSHDUP, - MOVSLDUP, - MOVLHPS, - MOVHLPS, - MOVSD, - MOVSS, - UNPCKL, - UNPCKH, - VPERMILPV, - VPERMILPI, - VPERMI, - VPERM2X128, - - // Variable Permute (VPERM). - // Res = VPERMV MaskV, V0 - VPERMV, - - // 3-op Variable Permute (VPERMT2). - // Res = VPERMV3 V0, MaskV, V1 - VPERMV3, - - // Bitwise ternary logic. - VPTERNLOG, - // Fix Up Special Packed Float32/64 values. - VFIXUPIMM, - VFIXUPIMM_SAE, - VFIXUPIMMS, - VFIXUPIMMS_SAE, - // Range Restriction Calculation For Packed Pairs of Float32/64 values. - VRANGE, - VRANGE_SAE, - VRANGES, - VRANGES_SAE, - // Reduce - Perform Reduction Transformation on scalar\packed FP. - VREDUCE, - VREDUCE_SAE, - VREDUCES, - VREDUCES_SAE, - // RndScale - Round FP Values To Include A Given Number Of Fraction Bits. - // Also used by the legacy (V)ROUND intrinsics where we mask out the - // scaling part of the immediate. - VRNDSCALE, - VRNDSCALE_SAE, - VRNDSCALES, - VRNDSCALES_SAE, - // Tests Types Of a FP Values for packed types. - VFPCLASS, - // Tests Types Of a FP Values for scalar types. - VFPCLASSS, - - // Broadcast (splat) scalar or element 0 of a vector. If the operand is - // a vector, this node may change the vector length as part of the splat. - VBROADCAST, - // Broadcast mask to vector. - VBROADCASTM, - - /// SSE4A Extraction and Insertion. - EXTRQI, - INSERTQI, - - // XOP arithmetic/logical shifts. - VPSHA, - VPSHL, - // XOP signed/unsigned integer comparisons. - VPCOM, - VPCOMU, - // XOP packed permute bytes. - VPPERM, - // XOP two source permutation. - VPERMIL2, - - // Vector multiply packed unsigned doubleword integers. - PMULUDQ, - // Vector multiply packed signed doubleword integers. - PMULDQ, - // Vector Multiply Packed UnsignedIntegers with Round and Scale. - MULHRS, - - // Multiply and Add Packed Integers. - VPMADDUBSW, - VPMADDWD, - - // AVX512IFMA multiply and add. - // NOTE: These are different than the instruction and perform - // op0 x op1 + op2. - VPMADD52L, - VPMADD52H, - - // VNNI - VPDPBUSD, - VPDPBUSDS, - VPDPWSSD, - VPDPWSSDS, - - // FMA nodes. - // We use the target independent ISD::FMA for the non-inverted case. - FNMADD, - FMSUB, - FNMSUB, - FMADDSUB, - FMSUBADD, - - // FMA with rounding mode. - FMADD_RND, - FNMADD_RND, - FMSUB_RND, - FNMSUB_RND, - FMADDSUB_RND, - FMSUBADD_RND, - - // Compress and expand. - COMPRESS, - EXPAND, - - // Bits shuffle - VPSHUFBITQMB, - - // Convert Unsigned/Integer to Floating-Point Value with rounding mode. - SINT_TO_FP_RND, - UINT_TO_FP_RND, - SCALAR_SINT_TO_FP, - SCALAR_UINT_TO_FP, - SCALAR_SINT_TO_FP_RND, - SCALAR_UINT_TO_FP_RND, - - // Vector float/double to signed/unsigned integer. - CVTP2SI, - CVTP2UI, - CVTP2SI_RND, - CVTP2UI_RND, - // Scalar float/double to signed/unsigned integer. - CVTS2SI, - CVTS2UI, - CVTS2SI_RND, - CVTS2UI_RND, - - // Vector float/double to signed/unsigned integer with truncation. - CVTTP2SI, - CVTTP2UI, - CVTTP2SI_SAE, - CVTTP2UI_SAE, - // Scalar float/double to signed/unsigned integer with truncation. - CVTTS2SI, - CVTTS2UI, - CVTTS2SI_SAE, - CVTTS2UI_SAE, - - // Vector signed/unsigned integer to float/double. - CVTSI2P, - CVTUI2P, - - // Masked versions of above. Used for v2f64->v4f32. - // SRC, PASSTHRU, MASK - MCVTP2SI, - MCVTP2UI, - MCVTTP2SI, - MCVTTP2UI, - MCVTSI2P, - MCVTUI2P, - - // Vector float to bfloat16. - // Convert TWO packed single data to one packed BF16 data - CVTNE2PS2BF16, - // Convert packed single data to packed BF16 data - CVTNEPS2BF16, - // Masked version of above. - // SRC, PASSTHRU, MASK - MCVTNEPS2BF16, - - // Dot product of BF16 pairs to accumulated into - // packed single precision. - DPBF16PS, - - // Save xmm argument registers to the stack, according to %al. An operator - // is needed so that this can be expanded with control flow. - VASTART_SAVE_XMM_REGS, - - // Windows's _chkstk call to do stack probing. - WIN_ALLOCA, - - // For allocating variable amounts of stack space when using - // segmented stacks. Check if the current stacklet has enough space, and - // falls back to heap allocation if not. - SEG_ALLOCA, - - // For allocating stack space when using stack clash protector. - // Allocation is performed by block, and each block is probed. - PROBED_ALLOCA, - - // Memory barriers. - MEMBARRIER, - MFENCE, - - // Get a random integer and indicate whether it is valid in CF. - RDRAND, - - // Get a NIST SP800-90B & C compliant random integer and - // indicate whether it is valid in CF. - RDSEED, - - // Protection keys - // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX. - // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is - // value for ECX. - RDPKRU, - WRPKRU, - - // SSE42 string comparisons. - // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG - // will emit one or two instructions based on which results are used. If - // flags and index/mask this allows us to use a single instruction since - // we won't have to pick and opcode for flags. Instead we can rely on the - // DAG to CSE everything and decide at isel. - PCMPISTR, - PCMPESTR, - - // Test if in transactional execution. - XTEST, - - // ERI instructions. - RSQRT28, - RSQRT28_SAE, - RSQRT28S, - RSQRT28S_SAE, - RCP28, - RCP28_SAE, - RCP28S, - RCP28S_SAE, - EXP2, - EXP2_SAE, - - // Conversions between float and half-float. - CVTPS2PH, - CVTPH2PS, - CVTPH2PS_SAE, - - // Masked version of above. - // SRC, RND, PASSTHRU, MASK - MCVTPS2PH, - - // Galois Field Arithmetic Instructions - GF2P8AFFINEINVQB, - GF2P8AFFINEQB, - GF2P8MULB, - - // LWP insert record. - LWPINS, - - // User level wait - UMWAIT, - TPAUSE, - - // Enqueue Stores Instructions - ENQCMD, - ENQCMDS, - - // For avx512-vp2intersect - VP2INTERSECT, - - // User level interrupts - testui - TESTUI, - - /// X86 strict FP compare instructions. - STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, - STRICT_FCMPS, - - // Vector packed double/float comparison. - STRICT_CMPP, - - /// Vector comparison generating mask bits for fp and - /// integer signed and unsigned data types. - STRICT_CMPM, - - // Vector float/double to signed/unsigned integer with truncation. - STRICT_CVTTP2SI, - STRICT_CVTTP2UI, - - // Vector FP extend. - STRICT_VFPEXT, - - // Vector FP round. - STRICT_VFPROUND, - - // RndScale - Round FP Values To Include A Given Number Of Fraction Bits. - // Also used by the legacy (V)ROUND intrinsics where we mask out the - // scaling part of the immediate. - STRICT_VRNDSCALE, - - // Vector signed/unsigned integer to float/double. - STRICT_CVTSI2P, - STRICT_CVTUI2P, - - // Strict FMA nodes. - STRICT_FNMADD, - STRICT_FMSUB, - STRICT_FNMSUB, - - // Conversions between float and half-float. - STRICT_CVTPS2PH, - STRICT_CVTPH2PS, - - // WARNING: Only add nodes here if they are stric FP nodes. Non-memory and - // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE. - - // Compare and swap. - LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, - LCMPXCHG8_DAG, - LCMPXCHG16_DAG, - LCMPXCHG16_SAVE_RBX_DAG, - - /// LOCK-prefixed arithmetic read-modify-write instructions. - /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS) - LADD, - LSUB, - LOR, - LXOR, - LAND, - - // Load, scalar_to_vector, and zero extend. - VZEXT_LOAD, - - // extract_vector_elt, store. - VEXTRACT_STORE, - - // scalar broadcast from memory. - VBROADCAST_LOAD, - - // subvector broadcast from memory. - SUBV_BROADCAST_LOAD, - - // Store FP control world into i16 memory. - FNSTCW16m, - - /// This instruction implements FP_TO_SINT with the - /// integer destination in memory and a FP reg source. This corresponds - /// to the X86::FIST*m instructions and the rounding mode change stuff. It - /// has two inputs (token chain and address) and two outputs (int value - /// and token chain). Memory VT specifies the type to store to. - FP_TO_INT_IN_MEM, - - /// This instruction implements SINT_TO_FP with the - /// integer source in memory and FP reg result. This corresponds to the - /// X86::FILD*m instructions. It has two inputs (token chain and address) - /// and two outputs (FP value and token chain). The integer source type is - /// specified by the memory VT. - FILD, - - /// This instruction implements a fp->int store from FP stack - /// slots. This corresponds to the fist instruction. It takes a - /// chain operand, value to store, address, and glue. The memory VT - /// specifies the type to store as. - FIST, - - /// This instruction implements an extending load to FP stack slots. - /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain - /// operand, and ptr to load from. The memory VT specifies the type to - /// load from. - FLD, - - /// This instruction implements a truncating store from FP stack - /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a - /// chain operand, value to store, address, and glue. The memory VT - /// specifies the type to store as. - FST, - - /// These instructions grab the address of the next argument - /// from a va_list. (reads and modifies the va_list in memory) - VAARG_64, - VAARG_X32, - - // Vector truncating store with unsigned/signed saturation - VTRUNCSTOREUS, - VTRUNCSTORES, - // Vector truncating masked store with unsigned/signed saturation - VMTRUNCSTOREUS, - VMTRUNCSTORES, - - // X86 specific gather and scatter - MGATHER, - MSCATTER, - - // Key locker nodes that produce flags. - AESENC128KL, - AESDEC128KL, - AESENC256KL, - AESDEC256KL, - AESENCWIDE128KL, - AESDECWIDE128KL, - AESENCWIDE256KL, - AESDECWIDE256KL, - - // WARNING: Do not add anything in the end unless you want the node to - // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all - // opcodes will be thought as target memory ops! - }; - } // end namespace X86ISD +namespace llvm LLVM_LIBRARY_VISIBILITY { +class X86Subtarget; +class X86TargetMachine; + +namespace X86ISD { +// X86 Specific DAG Nodes +enum NodeType : unsigned { + // Start the numbering where the builtin ops leave off. + FIRST_NUMBER = ISD::BUILTIN_OP_END, + + /// Bit scan forward. + BSF, + /// Bit scan reverse. + BSR, + + /// X86 funnel/double shift i16 instructions. These correspond to + /// X86::SHLDW and X86::SHRDW instructions which have different amt + /// modulo rules to generic funnel shifts. + /// NOTE: The operand order matches ISD::FSHL/FSHR not SHLD/SHRD. + FSHL, + FSHR, + + /// Bitwise logical AND of floating point values. This corresponds + /// to X86::ANDPS or X86::ANDPD. + FAND, + + /// Bitwise logical OR of floating point values. This corresponds + /// to X86::ORPS or X86::ORPD. + FOR, + + /// Bitwise logical XOR of floating point values. This corresponds + /// to X86::XORPS or X86::XORPD. + FXOR, + + /// Bitwise logical ANDNOT of floating point values. This + /// corresponds to X86::ANDNPS or X86::ANDNPD. + FANDN, + + /// These operations represent an abstract X86 call + /// instruction, which includes a bunch of information. In particular the + /// operands of these node are: + /// + /// #0 - The incoming token chain + /// #1 - The callee + /// #2 - The number of arg bytes the caller pushes on the stack. + /// #3 - The number of arg bytes the callee pops off the stack. + /// #4 - The value to pass in AL/AX/EAX (optional) + /// #5 - The value to pass in DL/DX/EDX (optional) + /// + /// The result values of these nodes are: + /// + /// #0 - The outgoing token chain + /// #1 - The first register result value (optional) + /// #2 - The second register result value (optional) + /// + CALL, + + /// Same as call except it adds the NoTrack prefix. + NT_CALL, + + /// X86 compare and logical compare instructions. + CMP, + FCMP, + COMI, + UCOMI, + + /// X86 bit-test instructions. + BT, + + /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS + /// operand, usually produced by a CMP instruction. + SETCC, + + /// X86 Select + SELECTS, + + // Same as SETCC except it's materialized with a sbb and the value is all + // one's or all zero's. + SETCC_CARRY, // R = carry_bit ? ~0 : 0 + + /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. + /// Operands are two FP values to compare; result is a mask of + /// 0s or 1s. Generally DTRT for C/C++ with NaNs. + FSETCC, + + /// X86 FP SETCC, similar to above, but with output as an i1 mask and + /// and a version with SAE. + FSETCCM, + FSETCCM_SAE, + + /// X86 conditional moves. Operand 0 and operand 1 are the two values + /// to select from. Operand 2 is the condition code, and operand 3 is the + /// flag operand produced by a CMP or TEST instruction. + CMOV, + + /// X86 conditional branches. Operand 0 is the chain operand, operand 1 + /// is the block to branch if condition is true, operand 2 is the + /// condition code, and operand 3 is the flag operand produced by a CMP + /// or TEST instruction. + BRCOND, + + /// BRIND node with NoTrack prefix. Operand 0 is the chain operand and + /// operand 1 is the target address. + NT_BRIND, + + /// Return with a flag operand. Operand 0 is the chain operand, operand + /// 1 is the number of bytes of stack to pop. + RET_FLAG, + + /// Return from interrupt. Operand 0 is the number of bytes to pop. + IRET, + + /// Repeat fill, corresponds to X86::REP_STOSx. + REP_STOS, + + /// Repeat move, corresponds to X86::REP_MOVSx. + REP_MOVS, + + /// On Darwin, this node represents the result of the popl + /// at function entry, used for PIC code. + GlobalBaseReg, + + /// A wrapper node for TargetConstantPool, TargetJumpTable, + /// TargetExternalSymbol, TargetGlobalAddress, TargetGlobalTLSAddress, + /// MCSymbol and TargetBlockAddress. + Wrapper, + + /// Special wrapper used under X86-64 PIC mode for RIP + /// relative displacements. + WrapperRIP, + + /// Copies a 64-bit value from an MMX vector to the low word + /// of an XMM vector, with the high word zero filled. + MOVQ2DQ, + + /// Copies a 64-bit value from the low word of an XMM vector + /// to an MMX vector. + MOVDQ2Q, + + /// Copies a 32-bit value from the low word of a MMX + /// vector to a GPR. + MMX_MOVD2W, + + /// Copies a GPR into the low 32-bit word of a MMX vector + /// and zero out the high word. + MMX_MOVW2D, + + /// Extract an 8-bit value from a vector and zero extend it to + /// i32, corresponds to X86::PEXTRB. + PEXTRB, + + /// Extract a 16-bit value from a vector and zero extend it to + /// i32, corresponds to X86::PEXTRW. + PEXTRW, + + /// Insert any element of a 4 x float vector into any element + /// of a destination 4 x floatvector. + INSERTPS, + + /// Insert the lower 8-bits of a 32-bit value to a vector, + /// corresponds to X86::PINSRB. + PINSRB, + + /// Insert the lower 16-bits of a 32-bit value to a vector, + /// corresponds to X86::PINSRW. + PINSRW, + + /// Shuffle 16 8-bit values within a vector. + PSHUFB, + + /// Compute Sum of Absolute Differences. + PSADBW, + /// Compute Double Block Packed Sum-Absolute-Differences + DBPSADBW, + + /// Bitwise Logical AND NOT of Packed FP values. + ANDNP, + + /// Blend where the selector is an immediate. + BLENDI, + + /// Dynamic (non-constant condition) vector blend where only the sign bits + /// of the condition elements are used. This is used to enforce that the + /// condition mask is not valid for generic VSELECT optimizations. This + /// is also used to implement the intrinsics. + /// Operands are in VSELECT order: MASK, TRUE, FALSE + BLENDV, + + /// Combined add and sub on an FP vector. + ADDSUB, + + // FP vector ops with rounding mode. + FADD_RND, + FADDS, + FADDS_RND, + FSUB_RND, + FSUBS, + FSUBS_RND, + FMUL_RND, + FMULS, + FMULS_RND, + FDIV_RND, + FDIVS, + FDIVS_RND, + FMAX_SAE, + FMAXS_SAE, + FMIN_SAE, + FMINS_SAE, + FSQRT_RND, + FSQRTS, + FSQRTS_RND, + + // FP vector get exponent. + FGETEXP, + FGETEXP_SAE, + FGETEXPS, + FGETEXPS_SAE, + // Extract Normalized Mantissas. + VGETMANT, + VGETMANT_SAE, + VGETMANTS, + VGETMANTS_SAE, + // FP Scale. + SCALEF, + SCALEF_RND, + SCALEFS, + SCALEFS_RND, + + // Unsigned Integer average. + AVG, + + /// Integer horizontal add/sub. + HADD, + HSUB, + + /// Floating point horizontal add/sub. + FHADD, + FHSUB, + + // Detect Conflicts Within a Vector + CONFLICT, + + /// Floating point max and min. + FMAX, + FMIN, + + /// Commutative FMIN and FMAX. + FMAXC, + FMINC, + + /// Scalar intrinsic floating point max and min. + FMAXS, + FMINS, + + /// Floating point reciprocal-sqrt and reciprocal approximation. + /// Note that these typically require refinement + /// in order to obtain suitable precision. + FRSQRT, + FRCP, + + // AVX-512 reciprocal approximations with a little more precision. + RSQRT14, + RSQRT14S, + RCP14, + RCP14S, + + // Thread Local Storage. + TLSADDR, + + // Thread Local Storage. A call to get the start address + // of the TLS block for the current module. + TLSBASEADDR, + + // Thread Local Storage. When calling to an OS provided + // thunk at the address from an earlier relocation. + TLSCALL, + + // Exception Handling helpers. + EH_RETURN, + + // SjLj exception handling setjmp. + EH_SJLJ_SETJMP, + + // SjLj exception handling longjmp. + EH_SJLJ_LONGJMP, + + // SjLj exception handling dispatch. + EH_SJLJ_SETUP_DISPATCH, + + /// Tail call return. See X86TargetLowering::LowerCall for + /// the list of operands. + TC_RETURN, + + // Vector move to low scalar and zero higher vector elements. + VZEXT_MOVL, + + // Vector integer truncate. + VTRUNC, + // Vector integer truncate with unsigned/signed saturation. + VTRUNCUS, + VTRUNCS, + + // Masked version of the above. Used when less than a 128-bit result is + // produced since the mask only applies to the lower elements and can't + // be represented by a select. + // SRC, PASSTHRU, MASK + VMTRUNC, + VMTRUNCUS, + VMTRUNCS, + + // Vector FP extend. + VFPEXT, + VFPEXT_SAE, + VFPEXTS, + VFPEXTS_SAE, + + // Vector FP round. + VFPROUND, + VFPROUND_RND, + VFPROUNDS, + VFPROUNDS_RND, + + // Masked version of above. Used for v2f64->v4f32. + // SRC, PASSTHRU, MASK + VMFPROUND, + + // 128-bit vector logical left / right shift + VSHLDQ, + VSRLDQ, + + // Vector shift elements + VSHL, + VSRL, + VSRA, + + // Vector variable shift + VSHLV, + VSRLV, + VSRAV, + + // Vector shift elements by immediate + VSHLI, + VSRLI, + VSRAI, + + // Shifts of mask registers. + KSHIFTL, + KSHIFTR, + + // Bit rotate by immediate + VROTLI, + VROTRI, + + // Vector packed double/float comparison. + CMPP, + + // Vector integer comparisons. + PCMPEQ, + PCMPGT, + + // v8i16 Horizontal minimum and position. + PHMINPOS, + + MULTISHIFT, + + /// Vector comparison generating mask bits for fp and + /// integer signed and unsigned data types. + CMPM, + // Vector mask comparison generating mask bits for FP values. + CMPMM, + // Vector mask comparison with SAE for FP values. + CMPMM_SAE, + + // Arithmetic operations with FLAGS results. + ADD, + SUB, + ADC, + SBB, + SMUL, + UMUL, + OR, + XOR, + AND, + + // Bit field extract. + BEXTR, + BEXTRI, + + // Zero High Bits Starting with Specified Bit Position. + BZHI, + + // Parallel extract and deposit. + PDEP, + PEXT, + + // X86-specific multiply by immediate. + MUL_IMM, + + // Vector sign bit extraction. + MOVMSK, + + // Vector bitwise comparisons. + PTEST, + + // Vector packed fp sign bitwise comparisons. + TESTP, + + // OR/AND test for masks. + KORTEST, + KTEST, + + // ADD for masks. + KADD, + + // Several flavors of instructions with vector shuffle behaviors. + // Saturated signed/unnsigned packing. + PACKSS, + PACKUS, + // Intra-lane alignr. + PALIGNR, + // AVX512 inter-lane alignr. + VALIGN, + PSHUFD, + PSHUFHW, + PSHUFLW, + SHUFP, + // VBMI2 Concat & Shift. + VSHLD, + VSHRD, + VSHLDV, + VSHRDV, + // Shuffle Packed Values at 128-bit granularity. + SHUF128, + MOVDDUP, + MOVSHDUP, + MOVSLDUP, + MOVLHPS, + MOVHLPS, + MOVSD, + MOVSS, + UNPCKL, + UNPCKH, + VPERMILPV, + VPERMILPI, + VPERMI, + VPERM2X128, + + // Variable Permute (VPERM). + // Res = VPERMV MaskV, V0 + VPERMV, + + // 3-op Variable Permute (VPERMT2). + // Res = VPERMV3 V0, MaskV, V1 + VPERMV3, + + // Bitwise ternary logic. + VPTERNLOG, + // Fix Up Special Packed Float32/64 values. + VFIXUPIMM, + VFIXUPIMM_SAE, + VFIXUPIMMS, + VFIXUPIMMS_SAE, + // Range Restriction Calculation For Packed Pairs of Float32/64 values. + VRANGE, + VRANGE_SAE, + VRANGES, + VRANGES_SAE, + // Reduce - Perform Reduction Transformation on scalar\packed FP. + VREDUCE, + VREDUCE_SAE, + VREDUCES, + VREDUCES_SAE, + // RndScale - Round FP Values To Include A Given Number Of Fraction Bits. + // Also used by the legacy (V)ROUND intrinsics where we mask out the + // scaling part of the immediate. + VRNDSCALE, + VRNDSCALE_SAE, + VRNDSCALES, + VRNDSCALES_SAE, + // Tests Types Of a FP Values for packed types. + VFPCLASS, + // Tests Types Of a FP Values for scalar types. + VFPCLASSS, + + // Broadcast (splat) scalar or element 0 of a vector. If the operand is + // a vector, this node may change the vector length as part of the splat. + VBROADCAST, + // Broadcast mask to vector. + VBROADCASTM, + + /// SSE4A Extraction and Insertion. + EXTRQI, + INSERTQI, + + // XOP arithmetic/logical shifts. + VPSHA, + VPSHL, + // XOP signed/unsigned integer comparisons. + VPCOM, + VPCOMU, + // XOP packed permute bytes. + VPPERM, + // XOP two source permutation. + VPERMIL2, + + // Vector multiply packed unsigned doubleword integers. + PMULUDQ, + // Vector multiply packed signed doubleword integers. + PMULDQ, + // Vector Multiply Packed UnsignedIntegers with Round and Scale. + MULHRS, + + // Multiply and Add Packed Integers. + VPMADDUBSW, + VPMADDWD, + + // AVX512IFMA multiply and add. + // NOTE: These are different than the instruction and perform + // op0 x op1 + op2. + VPMADD52L, + VPMADD52H, + + // VNNI + VPDPBUSD, + VPDPBUSDS, + VPDPWSSD, + VPDPWSSDS, + + // FMA nodes. + // We use the target independent ISD::FMA for the non-inverted case. + FNMADD, + FMSUB, + FNMSUB, + FMADDSUB, + FMSUBADD, + + // FMA with rounding mode. + FMADD_RND, + FNMADD_RND, + FMSUB_RND, + FNMSUB_RND, + FMADDSUB_RND, + FMSUBADD_RND, + + // Compress and expand. + COMPRESS, + EXPAND, + + // Bits shuffle + VPSHUFBITQMB, + + // Convert Unsigned/Integer to Floating-Point Value with rounding mode. + SINT_TO_FP_RND, + UINT_TO_FP_RND, + SCALAR_SINT_TO_FP, + SCALAR_UINT_TO_FP, + SCALAR_SINT_TO_FP_RND, + SCALAR_UINT_TO_FP_RND, + + // Vector float/double to signed/unsigned integer. + CVTP2SI, + CVTP2UI, + CVTP2SI_RND, + CVTP2UI_RND, + // Scalar float/double to signed/unsigned integer. + CVTS2SI, + CVTS2UI, + CVTS2SI_RND, + CVTS2UI_RND, + + // Vector float/double to signed/unsigned integer with truncation. + CVTTP2SI, + CVTTP2UI, + CVTTP2SI_SAE, + CVTTP2UI_SAE, + // Scalar float/double to signed/unsigned integer with truncation. + CVTTS2SI, + CVTTS2UI, + CVTTS2SI_SAE, + CVTTS2UI_SAE, + + // Vector signed/unsigned integer to float/double. + CVTSI2P, + CVTUI2P, + + // Masked versions of above. Used for v2f64->v4f32. + // SRC, PASSTHRU, MASK + MCVTP2SI, + MCVTP2UI, + MCVTTP2SI, + MCVTTP2UI, + MCVTSI2P, + MCVTUI2P, + + // Vector float to bfloat16. + // Convert TWO packed single data to one packed BF16 data + CVTNE2PS2BF16, + // Convert packed single data to packed BF16 data + CVTNEPS2BF16, + // Masked version of above. + // SRC, PASSTHRU, MASK + MCVTNEPS2BF16, + + // Dot product of BF16 pairs to accumulated into + // packed single precision. + DPBF16PS, + + // Save xmm argument registers to the stack, according to %al. An operator + // is needed so that this can be expanded with control flow. + VASTART_SAVE_XMM_REGS, + + // Windows's _chkstk call to do stack probing. + WIN_ALLOCA, + + // For allocating variable amounts of stack space when using + // segmented stacks. Check if the current stacklet has enough space, and + // falls back to heap allocation if not. + SEG_ALLOCA, + + // For allocating stack space when using stack clash protector. + // Allocation is performed by block, and each block is probed. + PROBED_ALLOCA, + + // Memory barriers. + MEMBARRIER, + MFENCE, + + // Get a random integer and indicate whether it is valid in CF. + RDRAND, + + // Get a NIST SP800-90B & C compliant random integer and + // indicate whether it is valid in CF. + RDSEED, + + // Protection keys + // RDPKRU - Operand 0 is chain. Operand 1 is value for ECX. + // WRPKRU - Operand 0 is chain. Operand 1 is value for EDX. Operand 2 is + // value for ECX. + RDPKRU, + WRPKRU, + + // SSE42 string comparisons. + // These nodes produce 3 results, index, mask, and flags. X86ISelDAGToDAG + // will emit one or two instructions based on which results are used. If + // flags and index/mask this allows us to use a single instruction since + // we won't have to pick and opcode for flags. Instead we can rely on the + // DAG to CSE everything and decide at isel. + PCMPISTR, + PCMPESTR, + + // Test if in transactional execution. + XTEST, + + // ERI instructions. + RSQRT28, + RSQRT28_SAE, + RSQRT28S, + RSQRT28S_SAE, + RCP28, + RCP28_SAE, + RCP28S, + RCP28S_SAE, + EXP2, + EXP2_SAE, + + // Conversions between float and half-float. + CVTPS2PH, + CVTPH2PS, + CVTPH2PS_SAE, + + // Masked version of above. + // SRC, RND, PASSTHRU, MASK + MCVTPS2PH, + + // Galois Field Arithmetic Instructions + GF2P8AFFINEINVQB, + GF2P8AFFINEQB, + GF2P8MULB, + + // LWP insert record. + LWPINS, + + // User level wait + UMWAIT, + TPAUSE, + + // Enqueue Stores Instructions + ENQCMD, + ENQCMDS, + + // For avx512-vp2intersect + VP2INTERSECT, + + // User level interrupts - testui + TESTUI, + + /// X86 strict FP compare instructions. + STRICT_FCMP = ISD::FIRST_TARGET_STRICTFP_OPCODE, + STRICT_FCMPS, + + // Vector packed double/float comparison. + STRICT_CMPP, + + /// Vector comparison generating mask bits for fp and + /// integer signed and unsigned data types. + STRICT_CMPM, + + // Vector float/double to signed/unsigned integer with truncation. + STRICT_CVTTP2SI, + STRICT_CVTTP2UI, + + // Vector FP extend. + STRICT_VFPEXT, + + // Vector FP round. + STRICT_VFPROUND, + + // RndScale - Round FP Values To Include A Given Number Of Fraction Bits. + // Also used by the legacy (V)ROUND intrinsics where we mask out the + // scaling part of the immediate. + STRICT_VRNDSCALE, + + // Vector signed/unsigned integer to float/double. + STRICT_CVTSI2P, + STRICT_CVTUI2P, + + // Strict FMA nodes. + STRICT_FNMADD, + STRICT_FMSUB, + STRICT_FNMSUB, + + // Conversions between float and half-float. + STRICT_CVTPS2PH, + STRICT_CVTPH2PS, + + // WARNING: Only add nodes here if they are stric FP nodes. Non-memory and + // non-strict FP nodes should be above FIRST_TARGET_STRICTFP_OPCODE. + + // Compare and swap. + LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, + LCMPXCHG8_DAG, + LCMPXCHG16_DAG, + LCMPXCHG16_SAVE_RBX_DAG, + + /// LOCK-prefixed arithmetic read-modify-write instructions. + /// EFLAGS, OUTCHAIN = LADD(INCHAIN, PTR, RHS) + LADD, + LSUB, + LOR, + LXOR, + LAND, + + // Load, scalar_to_vector, and zero extend. + VZEXT_LOAD, + + // extract_vector_elt, store. + VEXTRACT_STORE, + + // scalar broadcast from memory. + VBROADCAST_LOAD, + + // subvector broadcast from memory. + SUBV_BROADCAST_LOAD, + + // Store FP control world into i16 memory. + FNSTCW16m, + + /// This instruction implements FP_TO_SINT with the + /// integer destination in memory and a FP reg source. This corresponds + /// to the X86::FIST*m instructions and the rounding mode change stuff. It + /// has two inputs (token chain and address) and two outputs (int value + /// and token chain). Memory VT specifies the type to store to. + FP_TO_INT_IN_MEM, + + /// This instruction implements SINT_TO_FP with the + /// integer source in memory and FP reg result. This corresponds to the + /// X86::FILD*m instructions. It has two inputs (token chain and address) + /// and two outputs (FP value and token chain). The integer source type is + /// specified by the memory VT. + FILD, + + /// This instruction implements a fp->int store from FP stack + /// slots. This corresponds to the fist instruction. It takes a + /// chain operand, value to store, address, and glue. The memory VT + /// specifies the type to store as. + FIST, + + /// This instruction implements an extending load to FP stack slots. + /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain + /// operand, and ptr to load from. The memory VT specifies the type to + /// load from. + FLD, + + /// This instruction implements a truncating store from FP stack + /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a + /// chain operand, value to store, address, and glue. The memory VT + /// specifies the type to store as. + FST, + + /// These instructions grab the address of the next argument + /// from a va_list. (reads and modifies the va_list in memory) + VAARG_64, + VAARG_X32, + + // Vector truncating store with unsigned/signed saturation + VTRUNCSTOREUS, + VTRUNCSTORES, + // Vector truncating masked store with unsigned/signed saturation + VMTRUNCSTOREUS, + VMTRUNCSTORES, + + // X86 specific gather and scatter + MGATHER, + MSCATTER, + + // Key locker nodes that produce flags. + AESENC128KL, + AESDEC128KL, + AESENC256KL, + AESDEC256KL, + AESENCWIDE128KL, + AESDECWIDE128KL, + AESENCWIDE256KL, + AESDECWIDE256KL, + + // WARNING: Do not add anything in the end unless you want the node to + // have memop! In fact, starting from FIRST_TARGET_MEMORY_OPCODE all + // opcodes will be thought as target memory ops! +}; +} // end namespace X86ISD /// Define some predicates that are used for node matching. namespace X86 { @@ -1708,6 +1708,6 @@ /// v8iX Hi --> <4, 4, 5, 5, 6, 6, 7, 7> void createSplat2ShuffleMask(MVT VT, SmallVectorImpl &Mask, bool Lo); -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_X86ISELLOWERING_H Index: llvm/lib/Target/X86/X86ISelLowering.cpp =================================================================== --- llvm/lib/Target/X86/X86ISelLowering.cpp +++ llvm/lib/Target/X86/X86ISelLowering.cpp @@ -6795,7 +6795,7 @@ return false; } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace X86 { bool isConstantSplat(SDValue Op, APInt &SplatVal, bool AllowPartialUndefs) { APInt UndefElts; @@ -6822,7 +6822,7 @@ return false; } } // namespace X86 -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY static bool getTargetShuffleMaskIndices(SDValue MaskNode, unsigned MaskEltSizeInBits, @@ -36316,13 +36316,11 @@ return DAG.getBitcast(VT, CstOp); } -namespace llvm { - namespace X86 { - enum { - MaxShuffleCombineDepth = 8 - }; - } -} // namespace llvm +namespace llvm LLVM_LIBRARY_VISIBILITY { +namespace X86 { +enum { MaxShuffleCombineDepth = 8 }; +} +} // namespace LLVM_LIBRARY_VISIBILITY /// Fully generic combining of x86 shuffle instructions. /// Index: llvm/lib/Target/X86/X86InstrBuilder.h =================================================================== --- llvm/lib/Target/X86/X86InstrBuilder.h +++ llvm/lib/Target/X86/X86InstrBuilder.h @@ -33,7 +33,7 @@ #include "llvm/MC/MCInstrDesc.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// X86AddressMode - This struct holds a generalized full x86 address mode. /// The base register can be a frame index, which will eventually be replaced @@ -227,6 +227,6 @@ .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H Index: llvm/lib/Target/X86/X86InstrFMA3Info.h =================================================================== --- llvm/lib/Target/X86/X86InstrFMA3Info.h +++ llvm/lib/Target/X86/X86InstrFMA3Info.h @@ -14,9 +14,11 @@ #ifndef LLVM_LIB_TARGET_X86_UTILS_X86INSTRFMA3INFO_H #define LLVM_LIB_TARGET_X86_UTILS_X86INSTRFMA3INFO_H +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// This class is used to group {132, 213, 231} forms of FMA opcodes together. /// Each of the groups has either 3 opcodes, Also, each group has an attributes @@ -92,6 +94,6 @@ /// and not included into any FMA3 group, then nullptr is returned. const X86InstrFMA3Group *getFMA3Group(unsigned Opcode, uint64_t TSFlags); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_UTILS_X86INSTRFMA3INFO_H Index: llvm/lib/Target/X86/X86InstrFoldTables.h =================================================================== --- llvm/lib/Target/X86/X86InstrFoldTables.h +++ llvm/lib/Target/X86/X86InstrFoldTables.h @@ -13,9 +13,11 @@ #ifndef LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H #define LLVM_LIB_TARGET_X86_X86INSTRFOLDTABLES_H +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { enum { // Select which memory operand is being unfolded. @@ -92,6 +94,6 @@ // Look up the memory unfolding table entry for this instruction. const X86MemoryFoldTableEntry *lookupUnfoldTable(unsigned MemOp); -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86InstrInfo.h =================================================================== --- llvm/lib/Target/X86/X86InstrInfo.h +++ llvm/lib/Target/X86/X86InstrInfo.h @@ -23,7 +23,7 @@ #define GET_INSTRINFO_HEADER #include "X86GenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86Subtarget; namespace X86 { @@ -629,6 +629,6 @@ bool IsIntrinsic = false) const; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86IntrinsicsInfo.h =================================================================== --- llvm/lib/Target/X86/X86IntrinsicsInfo.h +++ llvm/lib/Target/X86/X86IntrinsicsInfo.h @@ -17,7 +17,7 @@ #include "X86InstrInfo.h" #include "llvm/IR/IntrinsicsX86.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { enum IntrinsicType : uint16_t { CVTNEPS2BF16_MASK, @@ -1172,6 +1172,6 @@ std::end(IntrinsicsWithChain)) && "Intrinsic data tables should have unique entries"); } -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86LegalizerInfo.h =================================================================== --- llvm/lib/Target/X86/X86LegalizerInfo.h +++ llvm/lib/Target/X86/X86LegalizerInfo.h @@ -16,7 +16,7 @@ #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86Subtarget; class X86TargetMachine; @@ -47,5 +47,5 @@ void setLegalizerInfoAVX512DQ(); void setLegalizerInfoAVX512BW(); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp =================================================================== --- llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp +++ llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp @@ -183,7 +183,7 @@ } // end anonymous namespace -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template <> struct GraphTraits @@ -227,7 +227,7 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY constexpr MachineInstr *MachineGadgetGraph::ArgNodeSentinel; constexpr int MachineGadgetGraph::GadgetEdgeSentinel; Index: llvm/lib/Target/X86/X86MachineFunctionInfo.h =================================================================== --- llvm/lib/Target/X86/X86MachineFunctionInfo.h +++ llvm/lib/Target/X86/X86MachineFunctionInfo.h @@ -18,7 +18,7 @@ #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFunction.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// X86MachineFunctionInfo - This class is derived from MachineFunction and /// contains private X86 target-specific information for each MachineFunction. @@ -225,6 +225,6 @@ } }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86MacroFusion.h =================================================================== --- llvm/lib/Target/X86/X86MacroFusion.h +++ llvm/lib/Target/X86/X86MacroFusion.h @@ -14,9 +14,11 @@ #ifndef LLVM_LIB_TARGET_X86_X86MACROFUSION_H #define LLVM_LIB_TARGET_X86_X86MACROFUSION_H +#include "llvm/Support/Compiler.h" + #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class ScheduleDAGMutation; @@ -26,6 +28,6 @@ std::unique_ptr createX86MacroFusionDAGMutation(); -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86MacroFusion.cpp =================================================================== --- llvm/lib/Target/X86/X86MacroFusion.cpp +++ llvm/lib/Target/X86/X86MacroFusion.cpp @@ -64,11 +64,11 @@ llvm_unreachable("unknown fusion type"); } -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { std::unique_ptr createX86MacroFusionDAGMutation () { return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent); } -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/X86/X86OptimizeLEAs.cpp =================================================================== --- llvm/lib/Target/X86/X86OptimizeLEAs.cpp +++ llvm/lib/Target/X86/X86OptimizeLEAs.cpp @@ -113,7 +113,7 @@ } // end anonymous namespace /// Provide DenseMapInfo for MemOpKey. -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { template <> struct DenseMapInfo { using PtrInfo = DenseMapInfo; @@ -184,7 +184,7 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY /// Returns a hash table key based on memory operands of \p MI. The /// number of the first memory operand of \p MI is specified through \p N. Index: llvm/lib/Target/X86/X86RegisterBankInfo.h =================================================================== --- llvm/lib/Target/X86/X86RegisterBankInfo.h +++ llvm/lib/Target/X86/X86RegisterBankInfo.h @@ -18,7 +18,7 @@ #define GET_REGBANK_DECLARATIONS #include "X86GenRegisterBank.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class LLT; @@ -77,5 +77,5 @@ getInstrMapping(const MachineInstr &MI) const override; }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86RegisterInfo.h =================================================================== --- llvm/lib/Target/X86/X86RegisterInfo.h +++ llvm/lib/Target/X86/X86RegisterInfo.h @@ -18,8 +18,8 @@ #define GET_REGINFO_HEADER #include "X86GenRegisterInfo.inc" -namespace llvm { - class Triple; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class Triple; class X86RegisterInfo final : public X86GenRegisterInfo { private: @@ -151,6 +151,6 @@ const LiveRegMatrix *Matrix) const override; }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86SelectionDAGInfo.h =================================================================== --- llvm/lib/Target/X86/X86SelectionDAGInfo.h +++ llvm/lib/Target/X86/X86SelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class X86SelectionDAGInfo : public SelectionDAGTargetInfo { /// Returns true if it is possible for the base register to conflict with the @@ -40,6 +40,6 @@ MachinePointerInfo SrcPtrInfo) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.h =================================================================== --- llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.h +++ llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.h @@ -14,11 +14,13 @@ #ifndef LLVM_LIB_TARGET_X86_X86SHUFFLEDECODECONSTANTPOOL_H #define LLVM_LIB_TARGET_X86_X86SHUFFLEDECODECONSTANTPOOL_H +#include "llvm/Support/Compiler.h" + //===----------------------------------------------------------------------===// // Vector Mask Decoding //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Constant; template class SmallVectorImpl; @@ -38,6 +40,6 @@ void DecodeVPPERMMask(const Constant *C, unsigned Width, SmallVectorImpl &ShuffleMask); -} // llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp =================================================================== --- llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp +++ llvm/lib/Target/X86/X86ShuffleDecodeConstantPool.cpp @@ -21,7 +21,7 @@ // Vector Mask Decoding //===----------------------------------------------------------------------===// -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static bool extractConstantMask(const Constant *C, unsigned MaskEltSizeInBits, APInt &UndefElts, @@ -293,4 +293,4 @@ } } -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY Index: llvm/lib/Target/X86/X86Subtarget.h =================================================================== --- llvm/lib/Target/X86/X86Subtarget.h +++ llvm/lib/Target/X86/X86Subtarget.h @@ -26,7 +26,7 @@ #define GET_SUBTARGETINFO_HEADER #include "X86GenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class CallLowering; class GlobalValue; @@ -944,6 +944,6 @@ bool enableAdvancedRASplitCost() const override { return true; } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H Index: llvm/lib/Target/X86/X86TargetMachine.h =================================================================== --- llvm/lib/Target/X86/X86TargetMachine.h +++ llvm/lib/Target/X86/X86TargetMachine.h @@ -20,7 +20,7 @@ #include "llvm/Target/TargetMachine.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class TargetTransformInfo; @@ -58,6 +58,6 @@ bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_X86_X86TARGETMACHINE_H Index: llvm/lib/Target/X86/X86TargetObjectFile.h =================================================================== --- llvm/lib/Target/X86/X86TargetObjectFile.h +++ llvm/lib/Target/X86/X86TargetObjectFile.h @@ -11,30 +11,30 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { - - /// X86_64MachoTargetObjectFile - This TLOF implementation is used for Darwin - /// x86-64. - class X86_64MachoTargetObjectFile : public TargetLoweringObjectFileMachO { - public: - const MCExpr *getTTypeGlobalReference(const GlobalValue *GV, - unsigned Encoding, - const TargetMachine &TM, +namespace llvm LLVM_LIBRARY_VISIBILITY { + +/// X86_64MachoTargetObjectFile - This TLOF implementation is used for Darwin +/// x86-64. +class X86_64MachoTargetObjectFile : public TargetLoweringObjectFileMachO { +public: + const MCExpr *getTTypeGlobalReference(const GlobalValue *GV, + unsigned Encoding, + const TargetMachine &TM, + MachineModuleInfo *MMI, + MCStreamer &Streamer) const override; + + // getCFIPersonalitySymbol - The symbol that gets passed to + // .cfi_personality. + MCSymbol *getCFIPersonalitySymbol(const GlobalValue *GV, + const TargetMachine &TM, + MachineModuleInfo *MMI) const override; + + const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV, + const MCSymbol *Sym, + const MCValue &MV, int64_t Offset, MachineModuleInfo *MMI, MCStreamer &Streamer) const override; - - // getCFIPersonalitySymbol - The symbol that gets passed to - // .cfi_personality. - MCSymbol *getCFIPersonalitySymbol(const GlobalValue *GV, - const TargetMachine &TM, - MachineModuleInfo *MMI) const override; - - const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV, - const MCSymbol *Sym, - const MCValue &MV, int64_t Offset, - MachineModuleInfo *MMI, - MCStreamer &Streamer) const override; - }; +}; /// This implementation is used for X86 ELF targets that don't /// have a further specialization. @@ -47,6 +47,6 @@ const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/X86/X86TargetTransformInfo.h =================================================================== --- llvm/lib/Target/X86/X86TargetTransformInfo.h +++ llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -20,7 +20,7 @@ #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/BasicTTIImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class InstCombiner; @@ -251,6 +251,6 @@ /// @} }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h =================================================================== --- llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h +++ llvm/lib/Target/XCore/MCTargetDesc/XCoreInstPrinter.h @@ -18,7 +18,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/MC/MCInstPrinter.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreInstPrinter : public MCInstPrinter { public: @@ -42,6 +42,6 @@ void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_XCORE_MCTARGETDESC_XCOREINSTPRINTER_H Index: llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h =================================================================== --- llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ llvm/lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -15,7 +15,7 @@ #include "llvm/MC/MCAsmInfoELF.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class Triple; class XCoreMCAsmInfo : public MCAsmInfoELF { @@ -25,6 +25,6 @@ explicit XCoreMCAsmInfo(const Triple &TT); }; -} // namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.h =================================================================== --- llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.h +++ llvm/lib/Target/XCore/TargetInfo/XCoreTargetInfo.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIB_TARGET_XCORE_TARGETINFO_XCORETARGETINFO_H #define LLVM_LIB_TARGET_XCORE_TARGETINFO_XCORETARGETINFO_H -namespace llvm { +#include "llvm/Support/Compiler.h" + +namespace llvm LLVM_LIBRARY_VISIBILITY { class Target; Target &getTheXCoreTarget(); -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_XCORE_TARGETINFO_XCORETARGETINFO_H Index: llvm/lib/Target/XCore/XCore.h =================================================================== --- llvm/lib/Target/XCore/XCore.h +++ llvm/lib/Target/XCore/XCore.h @@ -17,19 +17,19 @@ #include "MCTargetDesc/XCoreMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { - class FunctionPass; - class ModulePass; - class TargetMachine; - class XCoreTargetMachine; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class FunctionPass; +class ModulePass; +class TargetMachine; +class XCoreTargetMachine; - void initializeXCoreLowerThreadLocalPass(PassRegistry &p); +void initializeXCoreLowerThreadLocalPass(PassRegistry &p); - FunctionPass *createXCoreFrameToArgsOffsetEliminationPass(); - FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, - CodeGenOpt::Level OptLevel); - ModulePass *createXCoreLowerThreadLocalPass(); +FunctionPass *createXCoreFrameToArgsOffsetEliminationPass(); +FunctionPass *createXCoreISelDag(XCoreTargetMachine &TM, + CodeGenOpt::Level OptLevel); +ModulePass *createXCoreLowerThreadLocalPass(); -} // end namespace llvm; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreFrameLowering.h =================================================================== --- llvm/lib/Target/XCore/XCoreFrameLowering.h +++ llvm/lib/Target/XCore/XCoreFrameLowering.h @@ -17,48 +17,43 @@ #include "llvm/CodeGen/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" -namespace llvm { - class XCoreSubtarget; - - class XCoreFrameLowering: public TargetFrameLowering { - public: - XCoreFrameLowering(const XCoreSubtarget &STI); - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF, - MachineBasicBlock &MBB) const override; - void emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const override; - - bool - spillCalleeSavedRegisters(MachineBasicBlock &MBB, +namespace llvm LLVM_LIBRARY_VISIBILITY { +class XCoreSubtarget; + +class XCoreFrameLowering : public TargetFrameLowering { +public: + XCoreFrameLowering(const XCoreSubtarget &STI); + + /// emitProlog/emitEpilog - These methods insert prolog and epilog code into + /// the function. + void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + + bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, + ArrayRef CSI, + const TargetRegisterInfo *TRI) const override; + bool + restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - ArrayRef CSI, + MutableArrayRef CSI, const TargetRegisterInfo *TRI) const override; - bool - restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - MutableArrayRef CSI, - const TargetRegisterInfo *TRI) const override; - MachineBasicBlock::iterator - eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const override; + MachineBasicBlock::iterator + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; - bool hasFP(const MachineFunction &MF) const override; + bool hasFP(const MachineFunction &MF) const override; - void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, - RegScavenger *RS = nullptr) const override; + void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs, + RegScavenger *RS = nullptr) const override; - void processFunctionBeforeFrameFinalized(MachineFunction &MF, - RegScavenger *RS = nullptr) const override; + void processFunctionBeforeFrameFinalized( + MachineFunction &MF, RegScavenger *RS = nullptr) const override; - //! Stack slot size (4 bytes) - static int stackSlotSize() { - return 4; - } - }; -} + //! Stack slot size (4 bytes) + static int stackSlotSize() { return 4; } +}; +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreISelLowering.h =================================================================== --- llvm/lib/Target/XCore/XCoreISelLowering.h +++ llvm/lib/Target/XCore/XCoreISelLowering.h @@ -18,72 +18,72 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { - // Forward delcarations - class XCoreSubtarget; +// Forward delcarations +class XCoreSubtarget; - namespace XCoreISD { - enum NodeType : unsigned { - // Start the numbering where the builtin ops and target ops leave off. - FIRST_NUMBER = ISD::BUILTIN_OP_END, +namespace XCoreISD { +enum NodeType : unsigned { + // Start the numbering where the builtin ops and target ops leave off. + FIRST_NUMBER = ISD::BUILTIN_OP_END, - // Branch and link (call) - BL, + // Branch and link (call) + BL, - // pc relative address - PCRelativeWrapper, + // pc relative address + PCRelativeWrapper, - // dp relative address - DPRelativeWrapper, + // dp relative address + DPRelativeWrapper, - // cp relative address - CPRelativeWrapper, + // cp relative address + CPRelativeWrapper, - // Load word from stack - LDWSP, + // Load word from stack + LDWSP, - // Store word to stack - STWSP, + // Store word to stack + STWSP, - // Corresponds to retsp instruction - RETSP, + // Corresponds to retsp instruction + RETSP, - // Corresponds to LADD instruction - LADD, + // Corresponds to LADD instruction + LADD, - // Corresponds to LSUB instruction - LSUB, + // Corresponds to LSUB instruction + LSUB, - // Corresponds to LMUL instruction - LMUL, + // Corresponds to LMUL instruction + LMUL, - // Corresponds to MACCU instruction - MACCU, + // Corresponds to MACCU instruction + MACCU, - // Corresponds to MACCS instruction - MACCS, + // Corresponds to MACCS instruction + MACCS, - // Corresponds to CRC8 instruction - CRC8, + // Corresponds to CRC8 instruction + CRC8, - // Jumptable branch. - BR_JT, + // Jumptable branch. + BR_JT, - // Jumptable branch using long branches for each entry. - BR_JT32, + // Jumptable branch using long branches for each entry. + BR_JT32, - // Offset from frame pointer to the first (possible) on-stack argument - FRAME_TO_ARGS_OFFSET, + // Offset from frame pointer to the first (possible) on-stack argument + FRAME_TO_ARGS_OFFSET, - // Exception handler return. The stack is restored to the first - // followed by a jump to the second argument. - EH_RETURN, + // Exception handler return. The stack is restored to the first + // followed by a jump to the second argument. + EH_RETURN, - // Memory barrier. - MEMBARRIER - }; - } + // Memory barrier. + MEMBARRIER +}; +} //===--------------------------------------------------------------------===// // TargetLowering Implementation @@ -231,6 +231,6 @@ return true; } }; -} + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreInstrInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreInstrInfo.h +++ llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -19,7 +19,7 @@ #define GET_INSTRINFO_HEADER #include "XCoreGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreInstrInfo : public XCoreGenInstrInfo { const XCoreRegisterInfo RI; @@ -88,6 +88,6 @@ unsigned Reg, uint64_t Value) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreInstrInfo.cpp =================================================================== --- llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -30,7 +30,7 @@ #define GET_INSTRINFO_CTOR_DTOR #include "XCoreGenInstrInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { namespace XCore { // XCore Condition Codes @@ -40,7 +40,7 @@ COND_INVALID }; } -} +} // namespace LLVM_LIBRARY_VISIBILITY // Pin the vtable to this file. void XCoreInstrInfo::anchor() {} Index: llvm/lib/Target/XCore/XCoreMCInstLower.h =================================================================== --- llvm/lib/Target/XCore/XCoreMCInstLower.h +++ llvm/lib/Target/XCore/XCoreMCInstLower.h @@ -12,12 +12,12 @@ #include "llvm/CodeGen/MachineOperand.h" #include "llvm/Support/Compiler.h" -namespace llvm { - class MCContext; - class MCInst; - class MCOperand; - class MachineInstr; - class AsmPrinter; +namespace llvm LLVM_LIBRARY_VISIBILITY { +class MCContext; +class MCInst; +class MCOperand; +class MachineInstr; +class AsmPrinter; /// This class is used to lower an MachineInstr into an MCInst. class LLVM_LIBRARY_VISIBILITY XCoreMCInstLower { @@ -34,6 +34,6 @@ MCOperand LowerSymbolOperand(const MachineOperand &MO, MachineOperandType MOTy, unsigned Offset) const; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h +++ llvm/lib/Target/XCore/XCoreMachineFunctionInfo.h @@ -20,7 +20,7 @@ #include #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { /// XCoreFunctionInfo - This class is derived from MachineFunction private /// XCore target-specific information for each MachineFunction. @@ -90,6 +90,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_XCORE_XCOREMACHINEFUNCTIONINFO_H Index: llvm/lib/Target/XCore/XCoreRegisterInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreRegisterInfo.h +++ llvm/lib/Target/XCore/XCoreRegisterInfo.h @@ -18,7 +18,7 @@ #define GET_REGINFO_HEADER #include "XCoreGenRegisterInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { struct XCoreRegisterInfo : public XCoreGenRegisterInfo { public: @@ -45,6 +45,6 @@ static bool needsFrameMoves(const MachineFunction &MF); }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h +++ llvm/lib/Target/XCore/XCoreSelectionDAGInfo.h @@ -15,7 +15,7 @@ #include "llvm/CodeGen/SelectionDAGTargetInfo.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreSelectionDAGInfo : public SelectionDAGTargetInfo { public: @@ -27,6 +27,6 @@ MachinePointerInfo SrcPtrInfo) const override; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreSubtarget.h =================================================================== --- llvm/lib/Target/XCore/XCoreSubtarget.h +++ llvm/lib/Target/XCore/XCoreSubtarget.h @@ -25,7 +25,7 @@ #define GET_SUBTARGETINFO_HEADER #include "XCoreGenSubtargetInfo.inc" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class StringRef; class XCoreSubtarget : public XCoreGenSubtargetInfo { @@ -60,6 +60,6 @@ return &InstrInfo.getRegisterInfo(); } }; -} // End llvm namespace +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreTargetMachine.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetMachine.h +++ llvm/lib/Target/XCore/XCoreTargetMachine.h @@ -21,7 +21,7 @@ #include "llvm/Target/TargetMachine.h" #include -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreTargetMachine : public LLVMTargetMachine { std::unique_ptr TLOF; @@ -49,6 +49,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif // LLVM_LIB_TARGET_XCORE_XCORETARGETMACHINE_H Index: llvm/lib/Target/XCore/XCoreTargetObjectFile.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetObjectFile.h +++ llvm/lib/Target/XCore/XCoreTargetObjectFile.h @@ -11,7 +11,7 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { static const unsigned CodeModelLargeSize = 256; @@ -34,6 +34,6 @@ const Constant *C, Align &Alignment) const override; }; -} // end namespace llvm + } // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreTargetStreamer.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetStreamer.h +++ llvm/lib/Target/XCore/XCoreTargetStreamer.h @@ -11,7 +11,7 @@ #include "llvm/MC/MCStreamer.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreTargetStreamer : public MCTargetStreamer { public: XCoreTargetStreamer(MCStreamer &S); @@ -21,6 +21,6 @@ virtual void emitCCBottomData(StringRef Name) = 0; virtual void emitCCBottomFunction(StringRef Name) = 0; }; -} +} // namespace LLVM_LIBRARY_VISIBILITY #endif Index: llvm/lib/Target/XCore/XCoreTargetTransformInfo.h =================================================================== --- llvm/lib/Target/XCore/XCoreTargetTransformInfo.h +++ llvm/lib/Target/XCore/XCoreTargetTransformInfo.h @@ -22,7 +22,7 @@ #include "llvm/CodeGen/BasicTTIImpl.h" #include "llvm/CodeGen/TargetLowering.h" -namespace llvm { +namespace llvm LLVM_LIBRARY_VISIBILITY { class XCoreTTIImpl : public BasicTTIImplBase { typedef BasicTTIImplBase BaseT; @@ -49,6 +49,6 @@ } }; -} // end namespace llvm +} // namespace LLVM_LIBRARY_VISIBILITY #endif