diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -194,7 +194,8 @@
       .widenScalarToNextPow2(0);
 
   getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
-      .legalFor({s32, s64, v2s64, v4s32, v2s32})
+      .legalFor({MinFPScalar, s32, s64, v2s64, v4s32, v2s32})
+      .clampScalar(0, MinFPScalar, s64)
       .clampNumElements(0, v2s32, v4s32)
       .clampNumElements(0, v2s64, v2s64);
 
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fp-arith-fp16.mir
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=NO-FP16
+# RUN: llc -mtriple aarch64-unknown-unknown -verify-machineinstrs -mattr=+fullfp16 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=FP16
+
+...
+---
+name:            fadd
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+
+    ; NO-FP16-LABEL: name: fadd
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16: %x:_(s16) = COPY $h0
+    ; NO-FP16: %y:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
+    ; NO-FP16: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FADD]](s32)
+    ; NO-FP16: $h0 = COPY %op(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    ; FP16-LABEL: name: fadd
+    ; FP16: liveins: $h0, $h1
+    ; FP16: %x:_(s16) = COPY $h0
+    ; FP16: %y:_(s16) = COPY $h1
+    ; FP16: %op:_(s16) = G_FADD %x, %y
+    ; FP16: $h0 = COPY %op(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    %x:_(s16) = COPY $h0
+    %y:_(s16) = COPY $h1
+    %op:_(s16) = G_FADD %x, %y
+    $h0 = COPY %op(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            fsub
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+
+    ; NO-FP16-LABEL: name: fsub
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16: %x:_(s16) = COPY $h0
+    ; NO-FP16: %y:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
+    ; NO-FP16: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FSUB]](s32)
+    ; NO-FP16: $h0 = COPY %op(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    ; FP16-LABEL: name: fsub
+    ; FP16: liveins: $h0, $h1
+    ; FP16: %x:_(s16) = COPY $h0
+    ; FP16: %y:_(s16) = COPY $h1
+    ; FP16: %op:_(s16) = G_FSUB %x, %y
+    ; FP16: $h0 = COPY %op(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    %x:_(s16) = COPY $h0
+    %y:_(s16) = COPY $h1
+    %op:_(s16) = G_FSUB %x, %y
+    $h0 = COPY %op(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            fmul
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+
+    ; NO-FP16-LABEL: name: fmul
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16: %x:_(s16) = COPY $h0
+    ; NO-FP16: %y:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
+    ; NO-FP16: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FMUL]](s32)
+    ; NO-FP16: $h0 = COPY %op(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    ; FP16-LABEL: name: fmul
+    ; FP16: liveins: $h0, $h1
+    ; FP16: %x:_(s16) = COPY $h0
+    ; FP16: %y:_(s16) = COPY $h1
+    ; FP16: %op:_(s16) = G_FMUL %x, %y
+    ; FP16: $h0 = COPY %op(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    %x:_(s16) = COPY $h0
+    %y:_(s16) = COPY $h1
+    %op:_(s16) = G_FMUL %x, %y
+    $h0 = COPY %op(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            fdiv
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0, $h1
+
+    ; NO-FP16-LABEL: name: fdiv
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16: %x:_(s16) = COPY $h0
+    ; NO-FP16: %y:_(s16) = COPY $h1
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
+    ; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %y(s16)
+    ; NO-FP16: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[FPEXT]], [[FPEXT1]]
+    ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FDIV]](s32)
+    ; NO-FP16: $h0 = COPY %op(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    ; FP16-LABEL: name: fdiv
+    ; FP16: liveins: $h0, $h1
+    ; FP16: %x:_(s16) = COPY $h0
+    ; FP16: %y:_(s16) = COPY $h1
+    ; FP16: %op:_(s16) = G_FDIV %x, %y
+    ; FP16: $h0 = COPY %op(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    %x:_(s16) = COPY $h0
+    %y:_(s16) = COPY $h1
+    %op:_(s16) = G_FDIV %x, %y
+    $h0 = COPY %op(s16)
+    RET_ReallyLR implicit $h0
+
+...
+---
+name:            fneg
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $h0
+
+    ; NO-FP16-LABEL: name: fneg
+    ; NO-FP16: liveins: $h0
+    ; NO-FP16: %x:_(s16) = COPY $h0
+    ; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %x(s16)
+    ; NO-FP16: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FPEXT]]
+    ; NO-FP16: %op:_(s16) = G_FPTRUNC [[FNEG]](s32)
+    ; NO-FP16: $h0 = COPY %op(s16)
+    ; NO-FP16: RET_ReallyLR implicit $h0
+    ; FP16-LABEL: name: fneg
+    ; FP16: liveins: $h0
+    ; FP16: %x:_(s16) = COPY $h0
+    ; FP16: %op:_(s16) = G_FNEG %x
+    ; FP16: $h0 = COPY %op(s16)
+    ; FP16: RET_ReallyLR implicit $h0
+    %x:_(s16) = COPY $h0
+    %op:_(s16) = G_FNEG %x
+    $h0 = COPY %op(s16)
+    RET_ReallyLR implicit $h0
+
+...