Index: lldb/source/Host/common/NativeRegisterContext.cpp
===================================================================
--- lldb/source/Host/common/NativeRegisterContext.cpp
+++ lldb/source/Host/common/NativeRegisterContext.cpp
@@ -64,6 +64,13 @@
         reg_name.equals_insensitive(reg_info->alt_name))
       return reg_info;
   }
+
+  // if none of the register entries matched directly, try matching
+  // using a generic register name.
+  uint32_t generic_reg = Args::StringToGenericRegister(reg_name);
+  if (generic_reg != LLDB_INVALID_REGNUM)
+    return GetRegisterInfo(eRegisterKindGeneric, generic_reg);
+
   return nullptr;
 }
 
Index: lldb/source/Target/RegisterContext.cpp
===================================================================
--- lldb/source/Target/RegisterContext.cpp
+++ lldb/source/Target/RegisterContext.cpp
@@ -62,6 +62,13 @@
         reg_name.equals_insensitive(reg_info->alt_name))
       return reg_info;
   }
+
+  // if none of the register entries matched directly, try matching
+  // using a generic register name.
+  uint32_t generic_reg = Args::StringToGenericRegister(reg_name);
+  if (generic_reg != LLDB_INVALID_REGNUM)
+    return GetRegisterInfo(eRegisterKindGeneric, generic_reg);
+
   return nullptr;
 }
 
Index: lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
===================================================================
--- lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -20,8 +20,16 @@
                           <architecture>i386:x86-64</architecture>
                           <osabi>GNU/Linux</osabi>
                           <feature name="org.gnu.gdb.i386.core">
+                            <reg name="rcx" bitsize="64" type="int64" regnum="2"/>
+                            <reg name="rdx" bitsize="64" type="int64" regnum="3"/>
+                            <reg name="rsi" bitsize="64" type="int64" regnum="4"/>
+                            <reg name="rdi" bitsize="64" type="int64" regnum="5"/>
+                            <reg name="rbp" bitsize="64" type="data_ptr" regnum="6"/>
                             <reg name="rsp" bitsize="64" type="data_ptr" regnum="7"/>
+                            <reg name="r8" bitsize="64" type="int64" regnum="8"/>
+                            <reg name="r9" bitsize="64" type="int64" regnum="9"/>
                             <reg name="rip" bitsize="64" type="code_ptr" regnum="16"/>
+                            <reg name="eflags" bitsize="32" type="i386_eflags" regnum="17"/>
                             <reg name="st0" bitsize="80" type="i387_ext" regnum="24"/>
                             <reg name="st1" bitsize="80" type="i387_ext" regnum="25"/>
                             <reg name="st2" bitsize="80" type="i387_ext" regnum="26"/>
@@ -59,8 +67,16 @@
 
             def readRegisters(self):
                 return (
-                    "0102030405060708"  # rsp
-                    "1112131415161718"  # rip
+                    "0102030405060708"  # rcx
+                    "1112131415161718"  # rdx
+                    "2122232425262728"  # rsi
+                    "3132333435363738"  # rdi
+                    "4142434445464748"  # rbp
+                    "5152535455565758"  # rsp
+                    "6162636465666768"  # r8
+                    "7172737475767778"  # r9
+                    "8182838485868788"  # rip
+                    "91929394"  # eflags
                     "0102030405060708090a"  # st0
                     "1112131415161718191a" +  # st1
                     "2122232425262728292a" * 6 +  # st2..st7
@@ -81,9 +97,31 @@
 
         # rsp and rip should be displayed as uints
         self.match("register read rsp",
-                   ["rsp = 0x0807060504030201"])
+                   ["rsp = 0x5857565554535251"])
         self.match("register read rip",
-                   ["rip = 0x1817161514131211"])
+                   ["rip = 0x8887868584838281"])
+
+        # test generic aliases
+        self.match("register read arg4",
+                   ["rcx = 0x0807060504030201"])
+        self.match("register read arg3",
+                   ["rdx = 0x1817161514131211"])
+        self.match("register read arg2",
+                   ["rsi = 0x2827262524232221"])
+        self.match("register read arg1",
+                   ["rdi = 0x3837363534333231"])
+        self.match("register read fp",
+                   ["rbp = 0x4847464544434241"])
+        self.match("register read sp",
+                   ["rsp = 0x5857565554535251"])
+        self.match("register read arg5",
+                   ["r8 = 0x6867666564636261"])
+        self.match("register read arg6",
+                   ["r9 = 0x7877767574737271"])
+        self.match("register read pc",
+                   ["rip = 0x8887868584838281"])
+        self.match("register read flags",
+                   ["eflags = 0x94939291"])
 
         # both stX and xmmX should be displayed as vectors
         self.match("register read st0",