diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2979,20 +2979,19 @@ return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV); } - // If the result type is XLenVT and CondV is the output of a SETCC node - // which also operated on XLenVT inputs, then merge the SETCC node into the - // lowered RISCVISD::SELECT_CC to take advantage of the integer - // compare+branch instructions. i.e.: + // If CondV is the output of a SETCC node which operates on XLenVT + // inputs, then merge the SETCC node into the lowered RISCVISD::SELECT_CC to + // take advantage of the integer compare+branch instructions. i.e.: // (select (setcc lhs, rhs, cc), truev, falsev) // -> (riscvisd::select_cc lhs, rhs, cc, truev, falsev) - if (VT == XLenVT && CondV.getOpcode() == ISD::SETCC && + if (CondV.getOpcode() == ISD::SETCC && CondV.getOperand(0).getSimpleValueType() == XLenVT) { SDValue LHS = CondV.getOperand(0); SDValue RHS = CondV.getOperand(1); const auto *CC = cast(CondV.getOperand(2)); ISD::CondCode CCVal = CC->get(); - // Special case for a select of 2 constants that have a diffence of 1. + // Special case for a select of 2 int constants that have a diffence of 1. // Normally this is done by DAGCombine, but if the select is introduced by // type legalization or op legalization, we miss it. Restricting to SETLT // case for now because that is what signed saturating add/sub need. @@ -3000,7 +2999,7 @@ // but we would probably want to swap the true/false values if the condition // is SETGE/SETLE to avoid an XORI. if (isa(TrueV) && isa(FalseV) && - CCVal == ISD::SETLT) { + CCVal == ISD::SETLT && VT == XLenVT) { const APInt &TrueVal = cast(TrueV)->getAPIntValue(); const APInt &FalseVal = cast(FalseV)->getAPIntValue(); if (TrueVal - 1 == FalseVal)