diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2124,6 +2124,7 @@
     clearFeatureBits(RISCV::FeatureStdExtD, "d");
     clearFeatureBits(RISCV::FeatureStdExtC, "c");
     clearFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+    clearFeatureBits(RISCV::FeatureStdExtP, "experimental-p");
     clearFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
     clearFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
     clearFeatureBits(RISCV::FeatureExtZba, "experimental-zba");
@@ -2137,6 +2138,9 @@
     clearFeatureBits(RISCV::FeatureExtZbr, "experimental-zbr");
     clearFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
     clearFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
+    clearFeatureBits(RISCV::FeatureExtZpn, "experimental-zpn");
+    clearFeatureBits(RISCV::FeatureExtZpsfoperand, "experimental-zpsfoperand");
+    clearFeatureBits(RISCV::FeatureExtZprvsfextra, "experimental-zprvsfextra");
     clearFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
     clearFeatureBits(RISCV::FeatureStdExtZvlsseg, "experimental-zvlsseg");
 
@@ -2165,6 +2169,8 @@
         setFeatureBits(RISCV::FeatureStdExtC, "c");
       } else if (Arch[0] == 'b') {
         setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+      } else if (Arch[0] == 'p') {
+        setFeatureBits(RISCV::FeatureStdExtP, "experimental-p");
       } else if (Arch[0] == 'v') {
         setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
       } else if (Arch[0] == 's' || Arch[0] == 'x' || Arch[0] == 'z') {
@@ -2193,7 +2199,17 @@
           setFeatureBits(RISCV::FeatureExtZbs, "experimental-zbs");
         else if (Ext == "zbt")
           setFeatureBits(RISCV::FeatureExtZbt, "experimental-zbt");
-        else if (Ext == "zfh")
+        else if (Ext == "zpn")
+          setFeatureBits(RISCV::FeatureExtZpn, "experimental-zpn");
+        else if (Ext == "zpsfoperand")
+          setFeatureBits(RISCV::FeatureExtZpsfoperand,
+                         "experimental-zpsfoperand");
+        else if (Ext == "zprvsfextra") {
+          if (!getFeatureBits(RISCV::Feature64Bit))
+            return Error(ValueExprLoc, "zprvsfextra is RV64 only");
+          setFeatureBits(RISCV::FeatureExtZprvsfextra,
+                         "experimental-zprvsfextra");
+        } else if (Ext == "zfh")
           setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
         else if (Ext == "zvamo")
           setFeatureBits(RISCV::FeatureExtZvamo, "experimental-zvamo");
@@ -2210,9 +2226,10 @@
         Arch = Arch.drop_front(1);
       int major = 0;
       int minor = 0;
-      Arch.consumeInteger(10, major);
-      Arch.consume_front("p");
-      Arch.consumeInteger(10, minor);
+      if (!Arch.consumeInteger(10, major)) {
+        Arch.consume_front("p");
+        Arch.consumeInteger(10, minor);
+      }
       Arch = Arch.drop_while([](char c) { return c == '_'; });
     }
   }
@@ -2243,6 +2260,8 @@
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtB))
         formalArchStr = (Twine(formalArchStr) + "_b0p93").str();
+      if (getFeatureBits(RISCV::FeatureStdExtP))
+        formalArchStr = (Twine(formalArchStr) + "_p0p93").str();
       if (getFeatureBits(RISCV::FeatureStdExtV))
         formalArchStr = (Twine(formalArchStr) + "_v0p10").str();
       if (getFeatureBits(RISCV::FeatureExtZfh))
@@ -2269,6 +2288,13 @@
         formalArchStr = (Twine(formalArchStr) + "_zbs0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZbt))
         formalArchStr = (Twine(formalArchStr) + "_zbt0p93").str();
+      if (getFeatureBits(RISCV::FeatureExtZpn))
+        formalArchStr = (Twine(formalArchStr) + "_zpn0p93").str();
+      if (getFeatureBits(RISCV::FeatureExtZpsfoperand))
+        formalArchStr = (Twine(formalArchStr) + "_zpsfoperand0p93").str();
+      if (getFeatureBits(RISCV::FeatureExtZprvsfextra) &&
+          getFeatureBits(RISCV::Feature64Bit))
+        formalArchStr = (Twine(formalArchStr) + "_zprvsfextra0p93").str();
       if (getFeatureBits(RISCV::FeatureExtZvamo))
         formalArchStr = (Twine(formalArchStr) + "_zvamo0p10").str();
       if (getFeatureBits(RISCV::FeatureStdExtZvlsseg))
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -62,6 +62,8 @@
     Arch += "_c2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtB))
     Arch += "_b0p93";
+  if (STI.hasFeature(RISCV::FeatureStdExtP))
+    Arch += "_p0p93";
   if (STI.hasFeature(RISCV::FeatureStdExtV))
     Arch += "_v0p10";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
@@ -92,6 +94,13 @@
     Arch += "_zvamo0p10";
   if (STI.hasFeature(RISCV::FeatureStdExtZvlsseg))
     Arch += "_zvlsseg0p10";
+  if (STI.hasFeature(RISCV::FeatureExtZpn))
+    Arch += "_zpn0p93";
+  if (STI.hasFeature(RISCV::FeatureExtZpsfoperand))
+    Arch += "_zpsfoperand0p93";
+  if (STI.hasFeature(RISCV::FeatureExtZprvsfextra) &&
+      STI.hasFeature(RISCV::Feature64Bit))
+    Arch += "_zprvsfextra0p93";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -20,6 +20,9 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV32ZBS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV32ZBT %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV32COMBINED %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV32P %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV32ZPN %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV32ZPSFOPERAND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
@@ -40,6 +43,10 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb,+experimental-zfh,+experimental-zvamo,+experimental-v,+f,+experimental-zvlsseg %s -o - | FileCheck --check-prefix=RV64COMBINED %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-p %s -o - | FileCheck --check-prefix=RV64P %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpn %s -o - | FileCheck --check-prefix=RV64ZPN %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zpsfoperand %s -o - | FileCheck --check-prefix=RV64ZPSFOPERAND %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zprvsfextra %s -o - | FileCheck --check-prefix=RV64ZPRVSFEXTRA %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
@@ -61,6 +68,9 @@
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs0p93"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
 ; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV32P: .attribute 5, "rv32i2p0_p0p93_zpn0p93_zpsfoperand0p93"
+; RV32ZPN: .attribute 5, "rv32i2p0_zpn0p93"
+; RV32ZPSFOPERAND: .attribute 5, "rv32i2p0_zpsfoperand0p93"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
@@ -82,6 +92,10 @@
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
 ; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvlsseg0p10"
 ; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zbb0p93_zvamo0p10_zvlsseg0p10"
+; RV64P: .attribute 5, "rv64i2p0_p0p93_zpn0p93_zpsfoperand0p93_zprvsfextra0p93"
+; RV64ZPN: .attribute 5, "rv64i2p0_zpn0p93"
+; RV64ZPSFOPERAND: .attribute 5, "rv64i2p0_zpsfoperand0p93"
+; RV64ZPRVSFEXTRA: .attribute 5, "rv64i2p0_zprvsfextra0p93"
 
 
 define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/attribute-arch-invalid.s b/llvm/test/MC/RISCV/attribute-arch-invalid.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/attribute-arch-invalid.s
@@ -0,0 +1,3 @@
+# RUN: not llvm-mc %s -triple=riscv32 -filetype=asm 2>&1 | FileCheck %s
+
+.attribute arch, "rv32izprvsfextra" # CHECK: :[[@LINE]]:18: error: zprvsfextra is RV64 only
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -39,6 +39,12 @@
 .attribute arch, "rv32ib"
 # CHECK: attribute      5, "rv32i2p0_b0p93_zba0p93_zbb0p93_zbc0p93_zbe0p93_zbf0p93_zbm0p93_zbp0p93_zbr0p93_zbs0p93_zbt0p93"
 
+.attribute arch, "rv32ip"
+# CHECK: attribute      5, "rv32i2p0_p0p93_zpn0p93_zpsfoperand0p93"
+
+.attribute arch, "rv64ip"
+# CHECK: attribute      5, "rv64i2p0_p0p93_zpn0p93_zpsfoperand0p93_zprvsfextra0p93"
+
 .attribute arch, "rv32iv"
 # CHECK: attribute      5, "rv32i2p0_v0p10"
 
@@ -75,6 +81,15 @@
 .attribute arch, "rv32izbt"
 # CHECK: attribute      5, "rv32i2p0_zbt0p93"
 
+.attribute arch, "rv32izpn"
+# CHECK: attribute      5, "rv32i2p0_zpn0p93"
+
+.attribute arch, "rv32izpsfoperand"
+# CHECK: attribute      5, "rv32i2p0_zpsfoperand0p93"
+
+.attribute arch, "rv64izprvsfextra"
+# CHECK: attribute      5, "rv64i2p0_zprvsfextra0p93"
+
 .attribute arch, "rv32ifzfh"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfh0p1"