diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -8515,11 +8515,32 @@
   // Both operands must be equivalent extend nodes.
   SDValue LeftOp = ShiftOperand.getOperand(0);
   SDValue RightOp = ShiftOperand.getOperand(1);
+
   bool IsSignExt = LeftOp.getOpcode() == ISD::SIGN_EXTEND;
   bool IsZeroExt = LeftOp.getOpcode() == ISD::ZERO_EXTEND;
 
-  if ((!(IsSignExt || IsZeroExt)) || LeftOp.getOpcode() != RightOp.getOpcode())
+  if (!(IsSignExt || IsZeroExt))
+    return SDValue();
+
+  ConstantSDNode *Constant = isConstOrConstSplat(RightOp);
+
+  if (Constant) {
+    unsigned NarrowVTBits =
+        LeftOp.getOperand(0).getValueType().getScalarSizeInBits();
+    unsigned ActiveBits = Constant->getAPIntValue().getActiveBits();
+    if (IsSignExt) {
+      // If is negative constant, should cout with the signed bit.
+      bool IsSignedConstant = Constant->getAPIntValue().isNegative();
+      if (IsSignedConstant) {
+        auto Positive = -Constant->getAPIntValue();
+        ActiveBits = Positive.getActiveBits() + 1;
+      }
+    }
+    if (ActiveBits > NarrowVTBits)
+      return SDValue();
+  } else if (LeftOp.getOpcode() != RightOp.getOpcode()) {
     return SDValue();
+  }
 
   EVT WideVT1 = LeftOp.getValueType();
   EVT WideVT2 = RightOp.getValueType();
@@ -8530,7 +8551,7 @@
 
   EVT NarrowVT = LeftOp.getOperand(0).getValueType();
   // Check that the two extend nodes are the same type.
-  if (NarrowVT !=  RightOp.getOperand(0).getValueType())
+  if (!Constant && (NarrowVT != RightOp.getOperand(0).getValueType()))
     return SDValue();
 
   // Proceed with the transformation if the wide type is twice as large
@@ -8554,8 +8575,14 @@
   if (!TLI.isOperationLegalOrCustom(MulhOpcode, NarrowVT))
     return SDValue();
 
-  SDValue Result = DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0),
-                               RightOp.getOperand(0));
+  SDValue Result =
+      Constant
+          ? DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0),
+                        DAG.getConstant(Constant->getAPIntValue().trunc(
+                                            NarrowVT.getScalarSizeInBits()),
+                                        DL, NarrowVT))
+          : DAG.getNode(MulhOpcode, DL, NarrowVT, LeftOp.getOperand(0),
+                        RightOp.getOperand(0));
   return (N->getOpcode() == ISD::SRA ? DAG.getSExtOrTrunc(Result, DL, WideVT1)
                                      : DAG.getZExtOrTrunc(Result, DL, WideVT1));
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll
@@ -23,3 +23,291 @@
   %cc = icmp eq <vscale x 4 x i8> %rem, zeroinitializer
   ret <vscale x 4 x i1> %cc
 }
+
+define <vscale x 1 x i32> @vmulh_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v9, v8
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %ve = mul <vscale x 1 x i64> %vc, %vd
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vf = lshr <vscale x 1 x i64> %ve, %splat
+  %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vg
+}
+
+define <vscale x 1 x i32> @vmulh_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulh_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulh_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = sext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v9, v8
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %ve = mul <vscale x 2 x i64> %vc, %vd
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vf = lshr <vscale x 2 x i64> %ve, %splat
+  %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vg
+}
+
+define <vscale x 2 x i32> @vmulh_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulh_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = sext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v10, v8
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %ve = mul <vscale x 4 x i64> %vc, %vd
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vf = lshr <vscale x 4 x i64> %ve, %splat
+  %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vg
+}
+
+define <vscale x 4 x i32> @vmulh_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulh_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = sext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vmulh_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v12, v8
+; CHECK-NEXT:    ret
+  %vc = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulh_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulh_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulh_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, 16
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = sext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode-rv32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode-rv32.ll
@@ -0,0 +1,286 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i32> @vmulhu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v9, v8
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
+  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %ve = mul <vscale x 1 x i64> %vc, %vd
+  %head = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %vf = lshr <vscale x 1 x i64> %ve, %splat
+  %vg = trunc <vscale x 1 x i64> %vf to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vg
+}
+
+define <vscale x 1 x i32> @vmulhu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv1i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 1 x i32> @vmulhu_vi_nxv1i32_1(<vscale x 1 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv1i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 28
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 1 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 1 x i32> %head1, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
+  %vb = zext <vscale x 1 x i32> %splat1 to <vscale x 1 x i64>
+  %vc = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
+  %vd = mul <vscale x 1 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 1 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 1 x i64> %head2, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
+  %ve = lshr <vscale x 1 x i64> %vd, %splat2
+  %vf = trunc <vscale x 1 x i64> %ve to <vscale x 1 x i32>
+  ret <vscale x 1 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v9, v8
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
+  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %ve = mul <vscale x 2 x i64> %vc, %vd
+  %head = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %vf = lshr <vscale x 2 x i64> %ve, %splat
+  %vg = trunc <vscale x 2 x i64> %vf to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vg
+}
+
+define <vscale x 2 x i32> @vmulhu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv2i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 2 x i32> @vmulhu_vi_nxv2i32_1(<vscale x 2 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv2i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 28
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 2 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 2 x i32> %head1, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
+  %vb = zext <vscale x 2 x i32> %splat1 to <vscale x 2 x i64>
+  %vc = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
+  %vd = mul <vscale x 2 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 2 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 2 x i64> %head2, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %ve = lshr <vscale x 2 x i64> %vd, %splat2
+  %vf = trunc <vscale x 2 x i64> %ve to <vscale x 2 x i32>
+  ret <vscale x 2 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v10, v8
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
+  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %ve = mul <vscale x 4 x i64> %vc, %vd
+  %head = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %vf = lshr <vscale x 4 x i64> %ve, %splat
+  %vg = trunc <vscale x 4 x i64> %vf to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vg
+}
+
+define <vscale x 4 x i32> @vmulhu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 4 x i32> @vmulhu_vi_nxv4i32_1(<vscale x 4 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv4i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 28
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 4 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 4 x i32> %head1, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %vb = zext <vscale x 4 x i32> %splat1 to <vscale x 4 x i64>
+  %vc = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
+  %vd = mul <vscale x 4 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 4 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 4 x i64> %head2, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
+  %ve = lshr <vscale x 4 x i64> %vd, %splat2
+  %vf = trunc <vscale x 4 x i64> %ve to <vscale x 4 x i32>
+  ret <vscale x 4 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
+; CHECK-LABEL: vmulhu_vv_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v12, v8
+; CHECK-NEXT:    ret
+  %vc = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
+  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulhu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %x) {
+; CHECK-LABEL: vmulhu_vx_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi a0, zero, -7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
+; CHECK-LABEL: vmulhu_vi_nxv8i32_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 28
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
+  %vb = zext <vscale x 8 x i32> %splat1 to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> undef, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}