Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -6831,14 +6831,20 @@
 multiclass SIMDFPThreeScalar<bit U, bit S, bits<3> opc, string asm,
                              SDPatternOperator OpNode = null_frag> {
   let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
+    // FABD is illegal in streaming mode. FMULX/FRECPS/FRSQRTS are legal.
+    let Predicates = !if(!ne(opc, 0b010), [HasNEONorStreamingSVE],
+                                          [HasNEON]) in {
     def NAME#64 : BaseSIMDThreeScalar<U, {S,0b11}, {0b11,opc}, FPR64, asm,
       [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
     def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
       [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
-    let Predicates = [HasNEON, HasFullFP16] in {
+    }
+    let Predicates = !if(!ne(opc, 0b010),
+                         [HasNEONorStreamingSVE, HasFullFP16],
+                         [HasNEON, HasFullFP16]) in {
     def NAME#16 : BaseSIMDThreeScalar<U, {S,0b10}, {0b00,opc}, FPR16, asm,
       [(set (f16 FPR16:$Rd), (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]>;
-    } // Predicates = [HasNEON, HasFullFP16]
+    }
   }
 
   def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
@@ -7029,9 +7035,15 @@
 }
 
 multiclass SIMDFPTwoScalar<bit U, bit S, bits<5> opc, string asm> {
+  // FRECPE/FRECPX/FRSQRTE are legal in streaming mode.
+  let Predicates = !if(!or(!eq(opc, 0b11101), !eq(opc, 0b11111)),
+                       [HasNEONorStreamingSVE], [HasNEON]) in {
   def v1i64       : BaseSIMDTwoScalar<U, {S,1}, 0b00, opc, FPR64, FPR64, asm,[]>;
   def v1i32       : BaseSIMDTwoScalar<U, {S,0}, 0b00, opc, FPR32, FPR32, asm,[]>;
-  let Predicates = [HasNEON, HasFullFP16] in {
+  }
+  let Predicates = !if(!or(!eq(opc, 0b11101), !eq(opc, 0b11111)),
+                      [HasNEONorStreamingSVE, HasFullFP16],
+                      [HasNEON, HasFullFP16]) in {
   def v1f16       : BaseSIMDTwoScalar<U, {S,1}, 0b11, opc, FPR16, FPR16, asm,[]>;
   }
 }
Index: llvm/test/MC/AArch64/SME/streaming-mode-neon-fp16.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AArch64/SME/streaming-mode-neon-fp16.s
@@ -0,0 +1,43 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+fullfp16 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=-neon < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+streaming-sve,+fullfp16 < %s \
+// RUN:        | llvm-objdump --mattr=+fullfp16 -d - | FileCheck %s --check-prefix=CHECK-INST
+// Disassemble encoding and check the re-encoding (-show-encoding) matches.
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve,+fullfp16 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+streaming-sve,+fullfp16 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+// Scalar FP instructions
+
+fmulx h0, h1, h2
+// CHECK-INST: fmulx h0, h1, h2
+// CHECK-ENCODING: [0x20,0x1c,0x42,0x5e]
+// CHECK-ERROR: instruction requires: fullfp16
+
+frecps h0, h1, h2
+// CHECK-INST: frecps h0, h1, h2
+// CHECK-ENCODING: [0x20,0x3c,0x42,0x5e]
+// CHECK-ERROR: instruction requires: fullfp16
+
+frsqrts h0, h1, h2
+// CHECK-INST: frsqrts h0, h1, h2
+// CHECK-ENCODING: [0x20,0x3c,0xc2,0x5e]
+// CHECK-ERROR: instruction requires: fullfp16
+
+frecpe h0, h1
+// CHECK-INST: frecpe h0, h1
+// CHECK-ENCODING: [0x20,0xd8,0xf9,0x5e]
+// CHECK-ERROR: instruction requires: fullfp16
+
+frecpx h0, h1
+// CHECK-INST: frecpx h0, h1
+// CHECK-ENCODING: [0x20,0xf8,0xf9,0x5e]
+// CHECK-ERROR: instruction requires: fullfp16
+
+frsqrte h0, h1
+// CHECK-INST: frsqrte h0, h1
+// CHECK-ENCODING: [0x20,0xd8,0xf9,0x7e]
+// CHECK-ERROR: instruction requires: fullfp16
Index: llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
===================================================================
--- llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
+++ llvm/test/MC/AArch64/SME/streaming-mode-neon-negative.s
@@ -154,3 +154,11 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
 // CHECK-NEXT: umov x0, v0.d[1]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// ------------------------------------------------------------------------- //
+// Check FABD is illegal in streaming mode
+
+fabd s0, s1, s2
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: neon
+// CHECK-NEXT: fabd s0, s1, s2
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/test/MC/AArch64/SME/streaming-mode-neon.s
===================================================================
--- llvm/test/MC/AArch64/SME/streaming-mode-neon.s
+++ llvm/test/MC/AArch64/SME/streaming-mode-neon.s
@@ -10,6 +10,8 @@
 // RUN:        | llvm-mc -triple=aarch64 -mattr=+streaming-sve -disassemble -show-encoding \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
+// Vector to GPR integer move instructions
+
 smov w0, v0.b[0]
 // CHECK-INST: smov w0, v0.b[0]
 // CHECK-ENCODING: [0x00,0x2c,0x01,0x0e]
@@ -66,3 +68,65 @@
 // CHECK-INST: mov x0, v0.d[0]
 // CHECK-ENCODING: [0x00,0x3c,0x08,0x4e]
 // CHECK-ERROR: instruction requires: neon
+
+// Scalar FP instructions
+
+fmulx s0, s1, s2
+// CHECK-INST: fmulx s0, s1, s2
+// CHECK-ENCODING: [0x20,0xdc,0x22,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+fmulx d0, d1, d2
+// CHECK-INST: fmulx d0, d1, d2
+// CHECK-ENCODING: [0x20,0xdc,0x62,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecps s0, s1, s2
+// CHECK-INST: frecps s0, s1, s2
+// CHECK-ENCODING: [0x20,0xfc,0x22,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecps d0, d1, d2
+// CHECK-INST: frecps d0, d1, d2
+// CHECK-ENCODING: [0x20,0xfc,0x62,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frsqrts s0, s1, s2
+// CHECK-INST: frsqrts s0, s1, s2
+// CHECK-ENCODING: [0x20,0xfc,0xa2,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frsqrts d0, d1, d2
+// CHECK-INST: frsqrts d0, d1, d2
+// CHECK-ENCODING: [0x20,0xfc,0xe2,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecpe s0, s1
+// CHECK-INST: frecpe s0, s1
+// CHECK-ENCODING: [0x20,0xd8,0xa1,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecpe d0, d1
+// CHECK-INST: frecpe d0, d1
+// CHECK-ENCODING: [0x20,0xd8,0xe1,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecpx s0, s1
+// CHECK-INST: frecpx s0, s1
+// CHECK-ENCODING: [0x20,0xf8,0xa1,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frecpx d0, d1
+// CHECK-INST: frecpx d0, d1
+// CHECK-ENCODING: [0x20,0xf8,0xe1,0x5e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frsqrte s0, s1
+// CHECK-INST: frsqrte s0, s1
+// CHECK-ENCODING: [0x20,0xd8,0xa1,0x7e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon
+
+frsqrte d0, d1
+// CHECK-INST: frsqrte d0, d1
+// CHECK-ENCODING: [0x20,0xd8,0xe1,0x7e]
+// CHECK-ERROR: instruction requires: streaming-sve or neon