Index: include/clang/Basic/Attr.td =================================================================== --- include/clang/Basic/Attr.td +++ include/clang/Basic/Attr.td @@ -421,8 +421,8 @@ } def ARMInterrupt : InheritableAttr, TargetSpecificAttr { - // NOTE: If you add any additional spellings, MSP430Interrupt's spellings - // must match. + // NOTE: If you add any additional spellings, MSP430Interrupt's and + // MipsInterrupt's spellings must match. let Spellings = [GNU<"interrupt">]; let Args = [EnumArgument<"Interrupt", "InterruptType", ["IRQ", "FIQ", "SWI", "ABORT", "UNDEF", ""], @@ -836,8 +836,8 @@ } def MSP430Interrupt : InheritableAttr, TargetSpecificAttr { - // NOTE: If you add any additional spellings, ARMInterrupt's spellings must - // match. + // NOTE: If you add any additional spellings, ARMInterrupt's and + // MipsInterrupt's spellings must match. let Spellings = [GNU<"interrupt">]; let Args = [UnsignedArgument<"Number">]; let ParseKind = "Interrupt"; @@ -851,6 +851,22 @@ let Documentation = [Undocumented]; } +def MipsInterrupt : InheritableAttr, TargetSpecificAttr { + // NOTE: If you add any additional spellings, ARMInterrupt's and + // MSP430Interrupt's spellings must match. + let Spellings = [GNU<"interrupt">]; + let Args = [EnumArgument<"Interrupt", "InterruptType", + ["vector=sw0", "vector=sw1", "vector=hw0", + "vector=hw1", "vector=hw2", "vector=hw3", + "vector=hw4", "vector=hw5", "eic", ""], + ["sw0", "sw1", "hw0", "hw1", "hw2", "hw3", + "hw4", "hw5", "eic", "eic"] + >]; + let ParseKind = "Interrupt"; + let HasCustomParsing = 1; + let Documentation = [MipsInterruptDocs]; +} + def Mode : Attr { let Spellings = [GCC<"mode">]; let Args = [IdentifierArgument<"Mode">]; Index: include/clang/Basic/AttrDocs.td =================================================================== --- include/clang/Basic/AttrDocs.td +++ include/clang/Basic/AttrDocs.td @@ -706,6 +706,46 @@ }]; } +def MipsInterruptDocs : Documentation { + let Category = DocCatFunction; + let Content = [{ +Clang supports the GNU style ``__attribute__((interrupt("ARGUMENT")))`` attribute on +MIPS targets. This attribute may be attached ot a function definition and instructs +the backend to generate appropriate function entry/exit code so that it can be used +directly as an interrupt service routine. + +By default the compiler will produce a function prologue and epilogue suitable for +an interrupt service routine that handles an External Interrupt Controller (eic) +generated interrupt. This behaviour can be explicitly requested with the "eic" +argument. + +Otherwise, for use with vectored interrupt mode the argument passed should be +of the form "vector=LEVEL" where LEVEL is one of the following values: +"sw0", "sw1", "hw0", "hw1", "hw2", "hw3", "hw4", "hw5". The compiler will +then set the interrupt mask to the corresponding level which will mask all +interrupts up to and including the argument. + +The semantics are as follows: + +- The prologue is modified so that the Exception Program Counter (EPC) and + Status coprocessor registers are saved to the stack. The interrupt mask is + set so that the function can only be interrupted by a higher priority + interrupt. The epilogue will restore the previous values of EPC and Status. + +- The prologue and epilogue are modified to save and restore all non-kernel + registers as necessary. + +- The FPU is disabled in the prologue as the floating pointer registers are not + spilled to the stack. + +- Function return is changed to an exception return instruction. + +- The parameter sets the interrupt mask for the function corresponding to the + interrupt level specified. If no mask is specified the interrupt mask + defaults to "eic". + }]; +} + def TargetDocs : Documentation { let Category = DocCatFunction; let Content = [{ Index: lib/CodeGen/TargetInfo.cpp =================================================================== --- lib/CodeGen/TargetInfo.cpp +++ lib/CodeGen/TargetInfo.cpp @@ -5805,6 +5805,34 @@ else if (FD->hasAttr()) { Fn->addFnAttr("nomips16"); } + + const MipsInterruptAttr * Attr = FD->getAttr(); + if (!Attr) + return; + + assert(Fn->arg_empty() && + "Functions with arguments and interrupt attribute not supported!"); + + assert(!Fn->hasFnAttribute("mips16") && + "Functions with the interrupt and " + "mips16 attributes are not supported!"); + + const char *Kind; + switch (Attr->getInterrupt()) { + default: llvm_unreachable("Unknown Mips interrupt attribute type!"); + case MipsInterruptAttr::eic: Kind = "eic"; break; + case MipsInterruptAttr::sw0: Kind = "sw0"; break; + case MipsInterruptAttr::sw1: Kind = "sw1"; break; + case MipsInterruptAttr::hw0: Kind = "hw0"; break; + case MipsInterruptAttr::hw1: Kind = "hw1"; break; + case MipsInterruptAttr::hw2: Kind = "hw2"; break; + case MipsInterruptAttr::hw3: Kind = "hw3"; break; + case MipsInterruptAttr::hw4: Kind = "hw4"; break; + case MipsInterruptAttr::hw5: Kind = "hw5"; break; + } + + Fn->addFnAttr("interrupt", Kind); + } bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, Index: lib/Sema/SemaDeclAttr.cpp =================================================================== --- lib/Sema/SemaDeclAttr.cpp +++ lib/Sema/SemaDeclAttr.cpp @@ -4251,10 +4251,44 @@ D->addAttr(UsedAttr::CreateImplicit(S.Context)); } +static void handleMipsInterruptAttr(Sema &S, Decl *D, + const AttributeList &Attr) { + // Only one optional argument permitted. + if (Attr.getNumArgs() > 1) { + S.Diag(Attr.getLoc(), diag::err_attribute_too_many_arguments) + << Attr.getName() << 1; + return; + } + + StringRef Str; + SourceLocation ArgLoc; + + if (Attr.getNumArgs() == 0) + Str = ""; + else if (!S.checkStringLiteralArgumentAttr(Attr, 0, Str, &ArgLoc)) + return; + + MipsInterruptAttr::InterruptType Kind; + if (!MipsInterruptAttr::ConvertStrToInterruptType(Str, Kind)) { + S.Diag(Attr.getLoc(), diag::warn_attribute_type_not_supported) + << Attr.getName() << Str << ArgLoc; + return; + } + + unsigned Index = Attr.getAttributeSpellingListIndex(); + D->addAttr(::new (S.Context) + MipsInterruptAttr(Attr.getLoc(), S.Context, Kind, Index)); +} + static void handleInterruptAttr(Sema &S, Decl *D, const AttributeList &Attr) { // Dispatch the interrupt attribute based on the current target. if (S.Context.getTargetInfo().getTriple().getArch() == llvm::Triple::msp430) handleMSP430InterruptAttr(S, D, Attr); + else if (S.Context.getTargetInfo().getTriple().getArch() == + llvm::Triple::mipsel || + S.Context.getTargetInfo().getTriple().getArch() == + llvm::Triple::mips) + handleMipsInterruptAttr(S, D, Attr); else handleARMInterruptAttr(S, D, Attr); } Index: test/CodeGen/mips-interrupt-attr-arg.c =================================================================== --- /dev/null +++ test/CodeGen/mips-interrupt-attr-arg.c @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -triple mipsel-unknown-linux -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK +// XFAIL: * + +void __attribute__ ((interrupt("vector=sw0"))) +isr_sw0 (char * a) +{ + // CHECK: define void @isr_sw0(i8* %a) [[SW0:#[0-9]+]] +} + + +// CHECK: attributes [[SW0]] = { {{.*}} "interrupt"="sw0" {{.*}} } + Index: test/CodeGen/mips-interrupt-attr.c =================================================================== --- /dev/null +++ test/CodeGen/mips-interrupt-attr.c @@ -0,0 +1,64 @@ +// RUN: %clang_cc1 -triple mipsel-unknown-linux -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK + +void __attribute__ ((interrupt("vector=sw0"))) +isr_sw0 (void) +{ + // CHECK: define void @isr_sw0() [[SW0:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=sw1"))) +isr_sw1 (void) +{ + // CHECK: define void @isr_sw1() [[SW1:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw0"))) +isr_hw0 (void) +{ + // CHECK: define void @isr_hw0() [[HW0:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw1"))) +isr_hw1 (void) +{ + // CHECK: define void @isr_hw1() [[HW1:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw2"))) +isr_hw2 (void) +{ + // CHECK: define void @isr_hw2() [[HW2:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw3"))) +isr_hw3 (void) +{ + // CHECK: define void @isr_hw3() [[HW3:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw4"))) +isr_hw4 (void) +{ + // CHECK: define void @isr_hw4() [[HW4:#[0-9]+]] +} + +void __attribute__ ((interrupt("vector=hw5"))) +isr_hw5 (void) +{ + // CHECK: define void @isr_hw5() [[HW5:#[0-9]+]] +} + +void __attribute__ ((interrupt)) +isr_eic (void) +{ + // CHECK: define void @isr_eic() [[EIC:#[0-9]+]] +} +// CHECK: attributes [[SW0]] = { {{.*}} "interrupt"="sw0" {{.*}} } +// CHECK: attributes [[SW1]] = { {{.*}} "interrupt"="sw1" {{.*}} } +// CHECK: attributes [[HW0]] = { {{.*}} "interrupt"="hw0" {{.*}} } +// CHECK: attributes [[HW1]] = { {{.*}} "interrupt"="hw1" {{.*}} } +// CHECK: attributes [[HW2]] = { {{.*}} "interrupt"="hw2" {{.*}} } +// CHECK: attributes [[HW3]] = { {{.*}} "interrupt"="hw3" {{.*}} } +// CHECK: attributes [[HW4]] = { {{.*}} "interrupt"="hw4" {{.*}} } +// CHECK: attributes [[HW5]] = { {{.*}} "interrupt"="hw5" {{.*}} } +// CHECK: attributes [[EIC]] = { {{.*}} "interrupt"="eic" {{.*}} } Index: test/Sema/mips-interrupt-attr.c =================================================================== --- /dev/null +++ test/Sema/mips-interrupt-attr.c @@ -0,0 +1,18 @@ +// RUN: %clang_cc1 %s -triple mips-img-elf -verify -fsyntax-only + +__attribute__((interrupt("EIC"))) void foo1() {} // expected-warning {{'interrupt' attribute argument not supported: EIC}} + +__attribute__((interrupt("eic", 1))) void foo2() {} // expected-error {{'interrupt' attribute takes no more than 1 argument}} + +__attribute__((interrupt("eic"))) void foo3(int a) {} +__attribute__((interrupt("vector=sw0"))) void foo4() {} +__attribute__((interrupt("vector=hw0"))) void foo5() {} +__attribute__((interrupt("vector=hw1"))) void foo6() {} +__attribute__((interrupt("vector=hw2"))) void foo7() {} +__attribute__((interrupt("vector=hw3"))) void foo8() {} +__attribute__((interrupt("vector=hw4"))) void foo9() {} +__attribute__((interrupt("vector=hw5"))) void fooa() {} + +__attribute__((interrupt)) void foob() {} +__attribute__((interrupt())) void fooc() {} +__attribute__((interrupt(""))) void food() {}