Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4941,7 +4941,7 @@
     return V;
 
   if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64) {
+      VT.getSizeInBits() <= 64 && N0.hasOneUse()) {
     if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
Index: llvm/test/CodeGen/AArch64/arm64-srl-and.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/arm64-srl-and.ll
@@ -0,0 +1,24 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=tsv110 -O3 < %s | FileCheck %s
+
+; Disable the dagcombine if operand has multi use
+
+@g = dso_local local_unnamed_addr global i16 0, align 4
+define dso_local noundef i32 @srl_and() local_unnamed_addr  {
+; CHECK-LABEL: srl_and:
+; CHECK:    mov w9, #65535
+; CHECK-NEXT:    add w8, w8, w9
+; CHECK-NEXT:    and w0, w8, w8, lsr #16
+entry:
+  %0 = load i16, i16* @g, align 4
+  %1 = xor i16 %0, 50
+  %tobool = icmp ne i16 %1, 0
+  %lor.ext = zext i1 %tobool to i32
+  %sub = add i16 %1, -1
+
+  %srl = zext i16 %sub to i32
+  %and = and i32 %srl, %lor.ext
+
+  ret i32 %and
+}
+