Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2172,8 +2172,13 @@
 
   // If we can emit an efficient shift operation, do so now.  Check to see if
   // the RHS is a constant.
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+    if (CN->getAPIntValue().uge(VT.getSizeInBits())) {
+      SplitRes_UNDEF(N, Lo, Hi);
+      return;
+    }
     return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
+  }
 
   // If we can determine that the high bit of the shift is zero or one, even if
   // the low bits are variable, emit this shift in an optimized form.
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -22712,7 +22712,7 @@
       // We shift all of the values by one. In many cases we do not have
       // hardware support for this operation. This is better expressed as an ADD
       // of two values.
-      if (N1SplatC->getZExtValue() == 1)
+      if (N1SplatC->getAPIntValue() == 1)
         return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N0);
     }
 
Index: test/CodeGen/X86/legalize-shl-vec.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/legalize-shl-vec.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86    | FileCheck %s
+
+; CHECK-LABEL: test1
+define <2 x i256> @test1(<2 x i256> %In) {
+  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+  %Out = shl <2 x i256> %In, %Amt
+  ret <2 x i256> %Out
+}
+
+; CHECK-LABEL: test2
+define <2 x i256> @test2(<2 x i256> %In) {
+  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+  %Out = ashr <2 x i256> %In, %Amt
+  ret <2 x i256> %Out
+}
+
+; CHECK-LABEL: test3
+define <2 x i256> @test3(<2 x i256> %In) {
+  %Amt = insertelement <2 x i256> undef, i256 -1, i32 0
+  %Out = lshr <2 x i256> %In, %Amt
+  ret <2 x i256> %Out
+}