diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -4475,6 +4475,11 @@ if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHS, DL, VT, {N0, N1})) return C; + // canonicalize constant to RHS. + if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && + !DAG.isConstantIntBuildVectorOrConstantInt(N1)) + return DAG.getNode(ISD::MULHS, DL, N->getVTList(), N1, N0); + // fold (mulhs x, 0) -> 0 if (isNullConstant(N1)) return N1; @@ -4527,6 +4532,11 @@ if (SDValue C = DAG.FoldConstantArithmetic(ISD::MULHU, DL, VT, {N0, N1})) return C; + // canonicalize constant to RHS. + if (DAG.isConstantIntBuildVectorOrConstantInt(N0) && + !DAG.isConstantIntBuildVectorOrConstantInt(N1)) + return DAG.getNode(ISD::MULHU, DL, N->getVTList(), N1, N0); + // fold (mulhu x, 0) -> 0 if (isNullConstant(N1)) return N1; diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -8225,7 +8225,7 @@ ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: s_mov_b32 s6, -1 @@ -8251,7 +8251,7 @@ ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2 -; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 @@ -8294,7 +8294,7 @@ ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s3 -; GFX6-NEXT: v_mul_hi_u32 v3, s3, v0 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 @@ -8344,7 +8344,7 @@ ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 @@ -8366,7 +8366,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8 -; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v6, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4 @@ -8411,7 +8411,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 -; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v4 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_mov_b32_e32 v3, s1 @@ -8873,7 +8873,7 @@ ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_ashr_i32 s0, s9, 31 ; GFX6-NEXT: s_lshr_b32 s0, s0, 20 -; GFX6-NEXT: v_mul_hi_u32 v2, s6, v0 +; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6 ; GFX6-NEXT: v_mul_lo_u32 v3, v1, s6 ; GFX6-NEXT: s_add_u32 s2, s8, s0 ; GFX6-NEXT: s_addc_u32 s3, s9, 0 @@ -8902,7 +8902,7 @@ ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v6, v5, vcc ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_mul_lo_u32 v5, v2, s6 -; GFX6-NEXT: v_mul_hi_u32 v7, s6, v0 +; GFX6-NEXT: v_mul_hi_u32 v7, v0, s6 ; GFX6-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; GFX6-NEXT: v_mul_lo_u32 v7, v0, s6 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, v0, v5 @@ -8944,7 +8944,7 @@ ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v6, v2, vcc ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s9 -; GFX6-NEXT: v_mul_hi_u32 v3, s9, v0 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s9 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s9 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v4 @@ -8999,7 +8999,7 @@ ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_ashr_i32 s2, s5, 31 ; GFX9-NEXT: s_lshr_b32 s2, s2, 20 -; GFX9-NEXT: v_mul_hi_u32 v2, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v2, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v3, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s8 ; GFX9-NEXT: s_add_u32 s4, s4, s2 @@ -9025,7 +9025,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v6, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v5, v2, s8 -; GFX9-NEXT: v_mul_hi_u32 v7, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v7, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x24 @@ -9070,7 +9070,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v6, v2, vcc ; GFX9-NEXT: v_mul_lo_u32 v5, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s3 -; GFX9-NEXT: v_mul_hi_u32 v3, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s3 ; GFX9-NEXT: v_sub_co_u32_e32 v5, vcc, s6, v5 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 ; GFX9-NEXT: v_mov_b32_e32 v3, s7 @@ -9689,7 +9689,7 @@ ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 ; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s2 ; GFX6-NEXT: v_mul_lo_u32 v2, v1, s2 ; GFX6-NEXT: v_mul_lo_u32 v4, v0, s2 ; GFX6-NEXT: s_mov_b32 s6, -1 @@ -9715,7 +9715,7 @@ ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc ; GFX6-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] ; GFX6-NEXT: v_mul_lo_u32 v4, v2, s2 -; GFX6-NEXT: v_mul_hi_u32 v5, s2, v0 +; GFX6-NEXT: v_mul_hi_u32 v5, v0, s2 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GFX6-NEXT: v_mul_lo_u32 v5, v0, s2 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 @@ -9757,7 +9757,7 @@ ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc -; GFX6-NEXT: v_mul_hi_u32 v2, s3, v0 +; GFX6-NEXT: v_mul_hi_u32 v2, v0, s3 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v2, v1 @@ -9806,7 +9806,7 @@ ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; GFX9-NEXT: v_mul_hi_u32 v3, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v3, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v2, v1, s8 ; GFX9-NEXT: v_mul_lo_u32 v4, v0, s8 ; GFX9-NEXT: v_add_u32_e32 v2, v3, v2 @@ -9828,7 +9828,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v7, v4, vcc ; GFX9-NEXT: v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3] ; GFX9-NEXT: v_mul_lo_u32 v4, v2, s8 -; GFX9-NEXT: v_mul_hi_u32 v6, s8, v0 +; GFX9-NEXT: v_mul_hi_u32 v6, v0, s8 ; GFX9-NEXT: v_mul_lo_u32 v8, v0, s8 ; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 ; GFX9-NEXT: v_add_u32_e32 v4, v6, v4 @@ -9871,7 +9871,7 @@ ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, v6, v5, vcc ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v0, v1 ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v7, v2, vcc -; GFX9-NEXT: v_mul_hi_u32 v2, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v2, v0, s3 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s3 ; GFX9-NEXT: v_mul_lo_u32 v0, v0, s3 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -1203,18 +1203,17 @@ ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 -; GCN-NEXT: v_mul_hi_u32 v0, 24, v0 -; GCN-NEXT: v_mul_hi_u32 v5, 24, v3 -; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 +; GCN-NEXT: v_mov_b32_e32 v5, s9 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v2, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v3, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v4, s9, v0 -; GCN-NEXT: v_mov_b32_e32 v5, s9 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; GCN-NEXT: v_mul_lo_u32 v3, s8, v0 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 @@ -1420,14 +1419,13 @@ ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v4, 24 -; GCN-NEXT: v_mul_hi_u32 v3, 24, v3 -; GCN-NEXT: v_mul_hi_u32 v6, 24, v4 -; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 +; GCN-NEXT: v_mul_hi_u32 v4, v4, 24 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v6, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v4, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, 0, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 @@ -1629,17 +1627,15 @@ ; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8 ; GCN-NEXT: v_addc_u32_e64 v4, vcc, v4, v6, s[4:5] ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_mul_hi_u32 v3, s4, v3 -; GCN-NEXT: v_mul_hi_u32 v5, s4, v4 -; GCN-NEXT: v_lshlrev_b32_e32 v6, 15, v4 -; GCN-NEXT: v_mul_hi_u32 v4, 0, v4 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v13, v5, vcc +; GCN-NEXT: v_lshrrev_b32_e32 v5, 17, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v4, 15, v4 +; GCN-NEXT: v_lshrrev_b32_e32 v3, 17, v3 +; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 +; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v5, vcc ; GCN-NEXT: v_add_i32_e32 v3, vcc, 0, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v4, v12, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc +; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v12, vcc ; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 ; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 ; GCN-NEXT: v_mul_lo_u32 v7, v1, v3 @@ -1647,7 +1643,7 @@ ; GCN-NEXT: v_mul_lo_u32 v6, v0, v3 ; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; GCN-NEXT: v_sub_i32_e32 v7, vcc, 0, v5 -; GCN-NEXT: v_sub_i32_e32 v6, vcc, s4, v6 +; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0x8000, v6 ; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v7, v1, vcc ; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v6, v0 ; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -1391,14 +1391,13 @@ ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 -; GCN-NEXT: v_mul_hi_u32 v0, 24, v0 -; GCN-NEXT: v_mul_hi_u32 v5, 24, v3 -; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v3, vcc ; GCN-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: v_mul_lo_u32 v1, s8, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-NEXT: v_mul_lo_u32 v3, s9, v0 @@ -1605,14 +1604,13 @@ ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 -; GCN-NEXT: v_mul_hi_u32 v2, 24, v2 -; GCN-NEXT: v_mul_hi_u32 v5, 24, v3 -; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 +; GCN-NEXT: v_mul_hi_u32 v2, v2, 24 +; GCN-NEXT: v_mul_hi_u32 v3, v3, 24 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v12, v5, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v12, v3, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0, v2 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v2 @@ -1812,17 +1810,15 @@ ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 ; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: s_mov_b32 s4, 0x8000 ; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_hi_u32 v2, s4, v2 -; GCN-NEXT: v_mul_hi_u32 v4, s4, v3 -; GCN-NEXT: v_lshlrev_b32_e32 v5, 15, v3 -; GCN-NEXT: v_mul_hi_u32 v3, 0, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_addc_u32_e32 v4, vcc, v12, v4, vcc +; GCN-NEXT: v_lshrrev_b32_e32 v4, 17, v3 +; GCN-NEXT: v_lshlrev_b32_e32 v3, 15, v3 +; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: v_addc_u32_e32 v3, vcc, v12, v4, vcc ; GCN-NEXT: v_add_i32_e32 v2, vcc, 0, v2 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v11, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc +; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v11, vcc ; GCN-NEXT: v_mul_lo_u32 v3, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 ; GCN-NEXT: v_mul_lo_u32 v5, v1, v2 @@ -1830,7 +1826,7 @@ ; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 ; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 ; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v3 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s4, v2 +; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0x8000, v2 ; GCN-NEXT: v_subb_u32_e64 v4, s[4:5], v4, v1, vcc ; GCN-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v0 ; GCN-NEXT: v_subbrev_u32_e64 v6, s[6:7], 0, v4, s[4:5] diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -779,23 +779,21 @@ ; GCN-NEXT: v_mov_b32_e32 v3, s6 ; GCN-NEXT: v_alignbit_b32 v3, s7, v3, 24 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_hi_u32 v5, v3, v1 ; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v3, v2 -; GCN-NEXT: v_mul_hi_u32 v1, 0, v1 -; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 -; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc -; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc +; GCN-NEXT: v_mul_hi_u32 v1, v3, v1 +; GCN-NEXT: v_mul_hi_u32 v2, v3, v2 +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc +; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 +; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v8, vcc ; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 ; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc ; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v5, v0, v1 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v1 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6 ; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc