diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2962,11 +2962,11 @@
 def : Pat<WToDPExtractConv.BV02S,
           (v2f64 (XVCVSXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13S,
-          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 3)))>;
+          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
 def : Pat<WToDPExtractConv.BV02U,
           (v2f64 (XVCVUXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13U,
-          (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 3)))>;
+          (v2f64 (XVCVUXWDP (XXSLDWI $A, $A, 1)))>;
 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 0)),
           (v2f64 (XXPERMDI (SUBREG_TO_REG (i64 1), $B, sub_64), $A, 1))>;
 def : Pat<(v2f64 (insertelt v2f64:$A, f64:$B, 1)),
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -6160,7 +6160,7 @@
 define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {
 ; P9BE-LABEL: sint_to_fp_widen13:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P9BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P9BE-NEXT:    xvcvsxwdp v2, vs0
 ; P9BE-NEXT:    blr
 ;
@@ -6171,7 +6171,7 @@
 ;
 ; P8BE-LABEL: sint_to_fp_widen13:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P8BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P8BE-NEXT:    xvcvsxwdp v2, vs0
 ; P8BE-NEXT:    blr
 ;
@@ -6224,7 +6224,7 @@
 define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) {
 ; P9BE-LABEL: uint_to_fp_widen13:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P9BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P9BE-NEXT:    xvcvuxwdp v2, vs0
 ; P9BE-NEXT:    blr
 ;
@@ -6235,7 +6235,7 @@
 ;
 ; P8BE-LABEL: uint_to_fp_widen13:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P8BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P8BE-NEXT:    xvcvuxwdp v2, vs0
 ; P8BE-NEXT:    blr
 ;
diff --git a/llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll
--- a/llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_int_to_double_shuffle.ll
@@ -12,7 +12,7 @@
 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
 ; CHECK-BE-NEXT:    xvcvsxwdp 34, 0
 ; CHECK-BE-NEXT:    blr
 entry:
@@ -29,7 +29,7 @@
 ;
 ; CHECK-BE-LABEL: bar:
 ; CHECK-BE:       # %bb.0: # %entry
-; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 3
+; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
 ; CHECK-BE-NEXT:    xvcvuxwdp 34, 0
 ; CHECK-BE-NEXT:    blr
 entry: