diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
--- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td
@@ -2962,7 +2962,7 @@
 def : Pat<WToDPExtractConv.BV02S,
           (v2f64 (XVCVSXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13S,
-          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 3)))>;
+          (v2f64 (XVCVSXWDP (XXSLDWI $A, $A, 1)))>;
 def : Pat<WToDPExtractConv.BV02U,
           (v2f64 (XVCVUXWDP $A))>;
 def : Pat<WToDPExtractConv.BV13U,
diff --git a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
--- a/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
+++ b/llvm/test/CodeGen/PowerPC/build-vector-tests.ll
@@ -6160,7 +6160,7 @@
 define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {
 ; P9BE-LABEL: sint_to_fp_widen13:
 ; P9BE:       # %bb.0: # %entry
-; P9BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P9BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P9BE-NEXT:    xvcvsxwdp v2, vs0
 ; P9BE-NEXT:    blr
 ;
@@ -6171,7 +6171,7 @@
 ;
 ; P8BE-LABEL: sint_to_fp_widen13:
 ; P8BE:       # %bb.0: # %entry
-; P8BE-NEXT:    xxsldwi vs0, v2, v2, 3
+; P8BE-NEXT:    xxsldwi vs0, v2, v2, 1
 ; P8BE-NEXT:    xvcvsxwdp v2, vs0
 ; P8BE-NEXT:    blr
 ;
diff --git a/llvm/test/CodeGen/PowerPC/vec_sitofp_shuffle.ll b/llvm/test/CodeGen/PowerPC/vec_sitofp_shuffle.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/vec_sitofp_shuffle.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LE %s
+; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown \
+; RUN:   -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-BE %s
+
+define <2 x double> @foo(<4 x i32> %s) {
+; CHECK-LE-LABEL: foo:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    xvcvsxwdp 34, 34
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: foo:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    xxsldwi 0, 34, 34, 1
+; CHECK-BE-NEXT:    xvcvsxwdp 34, 0
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = shufflevector <4 x i32> %s, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
+  %1 = sitofp <2 x i32> %0 to <2 x double>
+  ret <2 x double> %1
+}