diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3846,12 +3846,13 @@
           return DAG.getSetCC(dl, VT, Val, N1,
                               Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
         }
-      } else if (N1C->isOne()) {
+      } else if (N1C->isNullValue() || N1C->isOne()) {
         SDValue Op0 = N0;
         if (Op0.getOpcode() == ISD::TRUNCATE)
           Op0 = Op0.getOperand(0);
 
-        if ((Op0.getOpcode() == ISD::XOR) &&
+        // FIXME: allow comparison with zero.
+        if (N1C->isOne() && (Op0.getOpcode() == ISD::XOR) &&
             Op0.getOperand(0).getOpcode() == ISD::SETCC &&
             Op0.getOperand(1).getOpcode() == ISD::SETCC) {
           SDValue XorLHS = Op0.getOperand(0);
@@ -3867,8 +3868,12 @@
             return DAG.getSetCC(dl, VT, XorLHS, XorRHS, Cond);
           }
         }
-        if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1))) {
-          // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
+        if (Op0.getOpcode() == ISD::AND && isOneConstant(Op0.getOperand(1)) &&
+            (N1C->isOne() ||
+             (Cond == ISD::SETNE && !DCI.isAfterLegalizeDAG()))) {
+          // If this is (X&1) == / != 1,   normalize it to (X&1) != / == 0.
+          // If this is (X&1)      != 0, renormalize it to (X&1)      != 0.
+          SDValue OrigOp0 = Op0;
           if (Op0.getValueType().bitsGT(VT))
             Op0 = DAG.getNode(ISD::AND, dl, VT,
                           DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
@@ -3877,12 +3882,15 @@
             Op0 = DAG.getNode(ISD::AND, dl, VT,
                         DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
                         DAG.getConstant(1, dl, VT));
-
-          return DAG.getSetCC(dl, VT, Op0,
-                              DAG.getConstant(0, dl, Op0.getValueType()),
-                              Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
+          if (N1C->isOne() || Op0 != OrigOp0) {
+            if (N1C->isOne())
+              Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
+            return DAG.getSetCC(
+                dl, VT, Op0, DAG.getConstant(0, dl, Op0.getValueType()), Cond);
+          }
         }
-        if (Op0.getOpcode() == ISD::AssertZext &&
+        // FIXME: allow comparison with zero.
+        if (N1C->isOne() && Op0.getOpcode() == ISD::AssertZext &&
             cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
           return DAG.getSetCC(dl, VT, Op0,
                               DAG.getConstant(0, dl, Op0.getValueType()),
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-47.ll b/llvm/test/CodeGen/SystemZ/int-cmp-47.ll
--- a/llvm/test/CodeGen/SystemZ/int-cmp-47.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-47.ll
@@ -267,7 +267,8 @@
 define void @f12(i64 %a) {
 ; CHECK-LABEL: f12:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    tmhh %r2, 256
+; CHECK-NEXT:    srlg %r0, %r2, 56
+; CHECK-NEXT:    tmll %r0, 1
 ; CHECK-NEXT:    bner %r14
 ; CHECK-NEXT:  .LBB11_1: # %store
 ; CHECK-NEXT:    lgrl %r1, g@GOT
diff --git a/llvm/test/CodeGen/SystemZ/knownbits.ll b/llvm/test/CodeGen/SystemZ/knownbits.ll
--- a/llvm/test/CodeGen/SystemZ/knownbits.ll
+++ b/llvm/test/CodeGen/SystemZ/knownbits.ll
@@ -44,10 +44,10 @@
 ; CHECK-NEXT:    vrepig %v1, 1
 ; CHECK-NEXT:    vx %v0, %v0, %v1
 ; CHECK-NEXT:    vlgvg %r0, %v0, 0
-; CHECK-NEXT:    cgijlh %r0, 0, .LBB1_3
+; CHECK-NEXT:    cijlh %r0, 0, .LBB1_3
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    vlgvg %r0, %v0, 1
-; CHECK-NEXT:    cgijlh %r0, 0, .LBB1_3
+; CHECK-NEXT:    cijlh %r0, 0, .LBB1_3
 ; CHECK-NEXT:  # %bb.2:
 ; CHECK-NEXT:  .LBB1_3:
   %1 = and i64 %a0, 1
diff --git a/llvm/test/CodeGen/X86/bool-math.ll b/llvm/test/CodeGen/X86/bool-math.ll
--- a/llvm/test/CodeGen/X86/bool-math.ll
+++ b/llvm/test/CodeGen/X86/bool-math.ll
@@ -272,10 +272,9 @@
 ;
 ; X32-LABEL: opaque_constant:
 ; X32:       # %bb.0:
-; X32-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    xorl {{[0-9]+}}(%esp), %eax
-; X32-NEXT:    andl $1, %eax
-; X32-NEXT:    # kill: def $al killed $al killed $eax
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    xorb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    andb $1, %al
 ; X32-NEXT:    retl
   %andx = and i48 %x, 4294967296
   %andy = and i48 %y, 4294967296
diff --git a/llvm/test/CodeGen/X86/parity-vec.ll b/llvm/test/CodeGen/X86/parity-vec.ll
--- a/llvm/test/CodeGen/X86/parity-vec.ll
+++ b/llvm/test/CodeGen/X86/parity-vec.ll
@@ -19,8 +19,7 @@
 ; CHECK-NEXT:    psllw $7, %xmm0
 ; CHECK-NEXT:    pmovmskb %xmm0, %eax
 ; CHECK-NEXT:    popcntw %ax, %ax
-; CHECK-NEXT:    testb $1, %al
-; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    # kill: def $al killed $al killed $ax
 ; CHECK-NEXT:    retq
   %i1 = bitcast <16 x i1> %x to i16
   %i2 = call i16 @llvm.ctpop.i16(i16 %i1)