diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.h b/llvm/lib/Target/Lanai/LanaiISelLowering.h --- a/llvm/lib/Target/Lanai/LanaiISelLowering.h +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.h @@ -90,6 +90,11 @@ SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; + bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool IsVarArg, + const SmallVectorImpl &Outs, + LLVMContext &Context) const override; + Register getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const override; std::pair diff --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp --- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp +++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp @@ -530,6 +530,15 @@ return Chain; } +bool LanaiTargetLowering::CanLowerReturn( + CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, + const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + + return CCInfo.CheckReturn(Outs, RetCC_Lanai32); +} + SDValue LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, diff --git a/llvm/test/CodeGen/Lanai/lowering-128.ll b/llvm/test/CodeGen/Lanai/lowering-128.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/Lanai/lowering-128.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=lanai < %s | FileCheck %s + +; Tests that lowering wide registers (128 bits or more) works on Lanai. +; The emitted assembly is not checked, we just do a smoketest. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; CHECK-LABEL: add128: +define i128 @add128(i128 %x, i128 %y) { + %a = add i128 %x, %y + ret i128 %a +} +