diff --git a/utils/bazel/configure.bzl b/utils/bazel/configure.bzl
--- a/utils/bazel/configure.bzl
+++ b/utils/bazel/configure.bzl
@@ -16,15 +16,20 @@
     "AArch64",
     "AMDGPU",
     "ARM",
+    "AVR",
     "BPF",
     "Hexagon",
     "Lanai",
+    "Mips",
+    "MSP430",
     "NVPTX",
     "PowerPC",
     "RISCV",
     "Sparc",
+    "SystemZ",
     "WebAssembly",
     "X86",
+    "XCore",
 ]
 
 def _overlay_directories(repository_ctx):
diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
--- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
@@ -1490,6 +1490,21 @@
             ":r600_target_gen",
         ],
     },
+    {
+        "name": "AVR",
+        "short_name": "AVR",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "AVRGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "AVRGenAsmWriter.inc"),
+            ("-gen-callingconv", "AVRGenCallingConv.inc"),
+            ("-gen-dag-isel", "AVRGenDAGISel.inc"),
+            ("-gen-disassembler", "AVRGenDisassemblerTables.inc"),
+            ("-gen-emitter", "AVRGenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "AVRGenInstrInfo.inc"),
+            ("-gen-register-info", "AVRGenRegisterInfo.inc"),
+            ("-gen-subtarget", "AVRGenSubtargetInfo.inc"),
+        ],
+    },
     {
         "name": "BPF",
         "short_name": "BPF",
@@ -1536,6 +1551,41 @@
             ("-gen-subtarget", "lib/Target/Lanai/LanaiGenSubtargetInfo.inc"),
         ],
     },
+    {
+        "name": "Mips",
+        "short_name": "Mips",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "MipsGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "MipsGenAsmWriter.inc"),
+            ("-gen-callingconv", "MipsGenCallingConv.inc"),
+            ("-gen-dag-isel", "MipsGenDAGISel.inc"),
+            ("-gen-disassembler", "MipsGenDisassemblerTables.inc"),
+            ("-gen-emitter", "MipsGenMCCodeEmitter.inc"),
+            ("-gen-exegesis", "MipsGenExegesis.inc"),
+            ("-gen-fast-isel", "MipsGenFastISel.inc"),
+            ("-gen-global-isel", "MipsGenGlobalISel.inc"),
+            ("-gen-instr-info", "MipsGenInstrInfo.inc"),
+            ("-gen-pseudo-lowering", "MipsGenMCPseudoLowering.inc"),
+            ("-gen-register-bank", "MipsGenRegisterBank.inc"),
+            ("-gen-register-info", "MipsGenRegisterInfo.inc"),
+            ("-gen-subtarget", "MipsGenSubtargetInfo.inc"),
+        ],
+    },
+    {
+        "name": "MSP430",
+        "short_name": "MSP430",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "MSP430GenAsmMatcher.inc"),
+            ("-gen-asm-writer", "MSP430GenAsmWriter.inc"),
+            ("-gen-callingconv", "MSP430GenCallingConv.inc"),
+            ("-gen-dag-isel", "MSP430GenDAGISel.inc"),
+            ("-gen-disassembler", "MSP430GenDisassemblerTables.inc"),
+            ("-gen-emitter", "MSP430GenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "MSP430GenInstrInfo.inc"),
+            ("-gen-register-info", "MSP430GenRegisterInfo.inc"),
+            ("-gen-subtarget", "MSP430GenSubtargetInfo.inc"),
+        ],
+    },
     {
         "name": "NVPTX",
         "short_name": "NVPTX",
@@ -1580,6 +1630,21 @@
             ("-gen-disassembler", "lib/Target/Sparc/SparcGenDisassemblerTables.inc"),
         ],
     },
+    {
+        "name": "SystemZ",
+        "short_name": "SystemZ",
+        "tbl_outs": [
+            ("-gen-asm-matcher", "SystemZGenAsmMatcher.inc"),
+            ("-gen-asm-writer", "SystemZGenAsmWriter.inc"),
+            ("-gen-callingconv", "SystemZGenCallingConv.inc"),
+            ("-gen-dag-isel", "SystemZGenDAGISel.inc"),
+            ("-gen-disassembler", "SystemZGenDisassemblerTables.inc"),
+            ("-gen-emitter", "SystemZGenMCCodeEmitter.inc"),
+            ("-gen-instr-info", "SystemZGenInstrInfo.inc"),
+            ("-gen-register-info", "SystemZGenRegisterInfo.inc"),
+            ("-gen-subtarget", "SystemZGenSubtargetInfo.inc"),
+        ],
+    },
     {
         "name": "RISCV",
         "short_name": "RISCV",
@@ -1634,6 +1699,19 @@
             ("-gen-exegesis", "lib/Target/X86/X86GenExegesis.inc"),
         ],
     },
+    {
+        "name": "XCore",
+        "short_name": "XCore",
+        "tbl_outs": [
+            ("-gen-asm-writer", "XCoreGenAsmWriter.inc"),
+            ("-gen-callingconv", "XCoreGenCallingConv.inc"),
+            ("-gen-dag-isel", "XCoreGenDAGISel.inc"),
+            ("-gen-disassembler", "XCoreGenDisassemblerTables.inc"),
+            ("-gen-instr-info", "XCoreGenInstrInfo.inc"),
+            ("-gen-register-info", "XCoreGenRegisterInfo.inc"),
+            ("-gen-subtarget", "XCoreGenSubtargetInfo.inc"),
+        ],
+    },
 ] if lib["name"] in llvm_targets]
 
 cc_library(