Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -1368,7 +1368,9 @@
 
 def MatrixTileList : MatrixTileListOperand<>;
 
-def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
+def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)> {
+  let DiagnosticType = "InvalidMatrixIndexGPR32_12_15";
+}
 def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
   let EncoderMethod = "encodeMatrixIndexGPR32";
 }
Index: llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
===================================================================
--- llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -5307,6 +5307,8 @@
     return Error(Loc, "invalid matrix operand, expected za[0-7].d");
   case Match_InvalidMatrix:
     return Error(Loc, "invalid matrix operand, expected za");
+  case Match_InvalidMatrixIndexGPR32_12_15:
+    return Error(Loc, "operand must be a register in range [w12, w15]");
   default:
     llvm_unreachable("unexpected error code!");
   }
@@ -5842,6 +5844,7 @@
   case Match_InvalidMatrixTileVectorV64:
   case Match_InvalidMatrixTileVectorV128:
   case Match_InvalidSVCR:
+  case Match_InvalidMatrixIndexGPR32_12_15:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
Index: llvm/test/MC/AArch64/SME/dup-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/dup-diagnostics.s
+++ llvm/test/MC/AArch64/SME/dup-diagnostics.s
@@ -25,12 +25,12 @@
 // Invalid index base register register (w12-w15)
 
 dup p0.b, p0/z, p0.b[w11]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: dup  p0.b, p0/z, p0.b[w11]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 dup p0.b, p0/z, p0.b[w16]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: dup  p0.b, p0/z, p0.b[w16]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ld1b {za0h.b[w11, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1b {za0h.b[w11, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1b {za0h.b[w16, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1b {za0h.b[w16, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ld1d {za0h.d[w11, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1d {za0h.d[w11, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1d {za0h.d[w16, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1d {za0h.d[w16, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ld1h {za0h.h[w11, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1h {za0h.h[w11, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1h {za0h.h[w16, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1h {za0h.h[w16, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ld1q {za0h.q[w11]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1q {za0h.q[w11]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1q {za0h.q[w16]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1q {za0h.q[w16]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ld1w {za0h.s[w11, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1w {za0h.s[w11, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld1w {za0h.s[w16, #0]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ld1w {za0h.s[w16, #0]}, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/ldr-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/ldr-diagnostics.s
+++ llvm/test/MC/AArch64/SME/ldr-diagnostics.s
@@ -17,12 +17,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 ldr za[w11, #0], [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ldr za[w11, #0], [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ldr za[w16, #0], [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: ldr za[w16, #0], [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/mova-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/mova-diagnostics.s
+++ llvm/test/MC/AArch64/SME/mova-diagnostics.s
@@ -107,22 +107,22 @@
 // Invalid vector select register (expected: w12-w15)
 
 mova z0.h, p0/m, za0h.h[w11, #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: mova z0.h, p0/m, za0h.h[w11, #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 mova z0.s, p0/m, za0h.s[w16, #0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: mova z0.s, p0/m, za0h.s[w16, #0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 mova za0h.d[w11, #0], p0/m, z0.d
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: mova za0h.d[w11, #0], p0/m, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 mova za0h.q[w16, #0], p0/m, z0.q
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: mova za0h.q[w16, #0], p0/m, z0.q
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/st1b-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/st1b-diagnostics.s
+++ llvm/test/MC/AArch64/SME/st1b-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 st1b {za0h.b[w11, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1b {za0h.b[w11, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1b {za0h.b[w16, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1b {za0h.b[w16, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/st1d-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/st1d-diagnostics.s
+++ llvm/test/MC/AArch64/SME/st1d-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 st1d {za0h.d[w11, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1d {za0h.d[w11, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1d {za0h.d[w16, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1d {za0h.d[w16, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/st1h-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/st1h-diagnostics.s
+++ llvm/test/MC/AArch64/SME/st1h-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 st1h {za0h.h[w11, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1h {za0h.h[w11, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1h {za0h.h[w16, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1h {za0h.h[w16, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/st1q-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/st1q-diagnostics.s
+++ llvm/test/MC/AArch64/SME/st1q-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 st1q {za0h.q[w11]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1q {za0h.q[w11]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1q {za0h.q[w16]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1q {za0h.q[w16]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/st1w-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/st1w-diagnostics.s
+++ llvm/test/MC/AArch64/SME/st1w-diagnostics.s
@@ -22,12 +22,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 st1w {za0h.s[w11, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1w {za0h.s[w11, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st1w {za0h.s[w16, #0]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: st1w {za0h.s[w16, #0]}, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
Index: llvm/test/MC/AArch64/SME/str-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME/str-diagnostics.s
+++ llvm/test/MC/AArch64/SME/str-diagnostics.s
@@ -17,12 +17,12 @@
 // Invalid vector select register (expected: w12-w15)
 
 str za[w11, #0], [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: str za[w11, #0], [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 str za[w16, #0], [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
 // CHECK-NEXT: str za[w16, #0], [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: