diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h --- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.h @@ -91,6 +91,8 @@ class Error writeYaml(const LLVMState &State, const StringRef Filename); }; +bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B); + //------------------------------------------------------------------------------ // Utilities to work with Benchmark measures. diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp --- a/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp @@ -423,5 +423,11 @@ MinValue = std::min(MinValue, BM.PerInstructionValue); } +bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) { + return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) == + std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue); +} + + } // namespace exegesis } // namespace llvm diff --git a/llvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/AArch64/CMakeLists.txt @@ -1,10 +1,10 @@ -include_directories( +add_llvm_exegesis_unittest_includes( ${LLVM_MAIN_SRC_DIR}/lib/Target/AArch64 ${LLVM_BINARY_DIR}/lib/Target/AArch64 ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) -set(LLVM_LINK_COMPONENTS +add_llvm_exegesis_unittest_link_components( MC MCParser Object @@ -13,9 +13,8 @@ AArch64 ) -add_llvm_target_unittest(LLVMExegesisAArch64Tests +add_llvm_exegesis_unittest_sources( TargetTest.cpp ) -target_link_libraries(LLVMExegesisAArch64Tests PRIVATE - LLVMExegesis +add_llvm_exegesis_unittest_link_libraries( LLVMExegesisAArch64) diff --git a/llvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/ARM/CMakeLists.txt @@ -1,10 +1,10 @@ -include_directories( +add_llvm_exegesis_unittest_includes( ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM ${LLVM_BINARY_DIR}/lib/Target/ARM ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) -set(LLVM_LINK_COMPONENTS +add_llvm_exegesis_unittest_link_components( Core MC MCParser @@ -14,7 +14,6 @@ ARM ) -add_llvm_target_unittest(LLVMExegesisARMTests +add_llvm_exegesis_unittest_sources( AssemblerTest.cpp ) -target_link_libraries(LLVMExegesisARMTests PRIVATE LLVMExegesis) diff --git a/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/CMakeLists.txt @@ -1,4 +1,4 @@ -include_directories( +set(exegesis_includes ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) @@ -10,27 +10,56 @@ Symbolize ) -add_llvm_unittest(LLVMExegesisTests +set(exegesis_sources BenchmarkRunnerTest.cpp ClusteringTest.cpp PerfHelperTest.cpp RegisterValueTest.cpp SnippetGeneratorTest.cpp ) -target_link_libraries(LLVMExegesisTests PRIVATE LLVMExegesis) + +set(exegesis_link_libraries LLVMExegesis) + +function(add_llvm_exegesis_unittest_includes) + set(exegesis_includes ${exegesis_includes} ${ARGV} PARENT_SCOPE) +endfunction() + +function(add_llvm_exegesis_unittest_sources) + set(sources ${ARGV}) + list(TRANSFORM sources PREPEND "${CMAKE_CURRENT_LIST_DIR}/") + set(exegesis_sources ${exegesis_sources} ${sources} PARENT_SCOPE) +endfunction() + +function(add_llvm_exegesis_unittest_link_components comps) + set(LLVM_LINK_COMPONENTS ${LLVM_LINK_COMPONENTS} ${ARGV} PARENT_SCOPE) +endfunction() + +function(add_llvm_exegesis_unittest_link_libraries libs) + set(exegesis_link_libraries ${exegesis_link_libraries} ${ARGV} PARENT_SCOPE) +endfunction() + if(LLVM_TARGETS_TO_BUILD MATCHES "X86") - add_subdirectory(X86) + include(X86/CMakeLists.txt) endif() if(LLVM_TARGETS_TO_BUILD MATCHES "ARM") - add_subdirectory(ARM) + include(ARM/CMakeLists.txt) endif() if(LLVM_TARGETS_TO_BUILD MATCHES "AArch64") - add_subdirectory(AArch64) + include(AArch64/CMakeLists.txt) endif() if(LLVM_TARGETS_TO_BUILD MATCHES "PowerPC") - add_subdirectory(PowerPC) + include(PowerPC/CMakeLists.txt) endif() if(LLVM_TARGETS_TO_BUILD MATCHES "Mips") - add_subdirectory(Mips) + include(Mips/CMakeLists.txt) endif() + +include_directories(${exegesis_includes}) + +list(REMOVE_DUPLICATES LLVM_LINK_COMPONENTS) + +add_llvm_target_unittest(LLVMExegesisTests + ${exegesis_sources} + ) +target_link_libraries(LLVMExegesisTests PRIVATE ${exegesis_link_libraries}) diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp @@ -31,11 +31,6 @@ namespace llvm { namespace exegesis { -bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) { - return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) == - std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue); -} - static std::string Dump(const MCInst &McInst) { std::string Buffer; raw_string_ostream OS(Buffer); @@ -55,9 +50,9 @@ namespace { -class BenchmarkResultTest : public MipsTestBase {}; +class MipsBenchmarkResultTest : public MipsTestBase {}; -TEST_F(BenchmarkResultTest, WriteToAndReadFromDisk) { +TEST_F(MipsBenchmarkResultTest, WriteToAndReadFromDisk) { ExitOnError ExitOnErr; InstructionBenchmark ToDisk; @@ -120,7 +115,7 @@ } } -TEST_F(BenchmarkResultTest, PerInstructionStats) { +TEST_F(MipsBenchmarkResultTest, PerInstructionStats) { PerInstructionStats Stats; Stats.push(BenchmarkMeasure{"a", 0.5, 0.0}); Stats.push(BenchmarkMeasure{"a", 1.5, 0.0}); diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/Mips/CMakeLists.txt @@ -1,10 +1,10 @@ -include_directories( +add_llvm_exegesis_unittest_includes( ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips ${LLVM_BINARY_DIR}/lib/Target/Mips ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) -set(LLVM_LINK_COMPONENTS +add_llvm_exegesis_unittest_link_components( MC MCParser Object @@ -13,12 +13,11 @@ Mips ) -add_llvm_target_unittest(LLVMExegesisMipsTests +add_llvm_exegesis_unittest_sources( BenchmarkResultTest.cpp RegisterAliasingTest.cpp SnippetGeneratorTest.cpp TargetTest.cpp ) -target_link_libraries(LLVMExegesisMipsTests PRIVATE - LLVMExegesis +add_llvm_exegesis_unittest_link_libraries( LLVMExegesisMips) diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/Mips/RegisterAliasingTest.cpp @@ -22,9 +22,9 @@ namespace exegesis { namespace { -class RegisterAliasingTest : public MipsTestBase {}; +class MipsRegisterAliasingTest : public MipsTestBase {}; -TEST_F(RegisterAliasingTest, TrackSimpleRegister) { +TEST_F(MipsRegisterAliasingTest, TrackSimpleRegister) { const auto &RegInfo = State.getRegInfo(); const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64); std::set ActualAliasedRegisters; @@ -37,7 +37,7 @@ } } -TEST_F(RegisterAliasingTest, TrackRegisterClass) { +TEST_F(MipsRegisterAliasingTest, TrackRegisterClass) { // The alias bits for // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID // are the union of the alias bits for ZERO_64, V0_64, V1_64 and S1_64. @@ -58,7 +58,7 @@ ASSERT_THAT(RegClassTracker.aliasedBits(), sum); } -TEST_F(RegisterAliasingTest, TrackRegisterClassCache) { +TEST_F(MipsRegisterAliasingTest, TrackRegisterClassCache) { // Fetching the same tracker twice yields the same pointers. const auto &RegInfo = State.getRegInfo(); const BitVector NoReservedReg(RegInfo.getNumRegs()); diff --git a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp @@ -29,12 +29,10 @@ MATCHER(IsInvalid, "") { return !arg.isValid(); } MATCHER(IsReg, "") { return arg.isReg(); } -class MipsSnippetGeneratorTest : public MipsTestBase {}; - template -class SnippetGeneratorTest : public MipsSnippetGeneratorTest { +class MipsSnippetGeneratorTest : public MipsTestBase { protected: - SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} + MipsSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} std::vector checkAndGetCodeTemplates(unsigned Opcode) { randomGenerator().seed(0); // Initialize seed. @@ -48,12 +46,12 @@ SnippetGeneratorT Generator; }; -using SerialSnippetGeneratorTest = SnippetGeneratorTest; +using MipsSerialSnippetGeneratorTest = MipsSnippetGeneratorTest; -using ParallelSnippetGeneratorTest = - SnippetGeneratorTest; +using MipsParallelSnippetGeneratorTest = + MipsSnippetGeneratorTest; -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { +TEST_F(MipsSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { // - ADD // - Op0 Explicit Def RegClass(GPR32) // - Op1 Explicit Use RegClass(GPR32) @@ -77,7 +75,7 @@ << "Op0 is either set to Op1 or to Op2"; } -TEST_F(SerialSnippetGeneratorTest, +TEST_F(MipsSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegsForbidAll) { // - XOR // - Op0 Explicit Def RegClass(GPR32) @@ -97,7 +95,7 @@ consumeError(std::move(Error)); } -TEST_F(ParallelSnippetGeneratorTest, MemoryUse) { +TEST_F(MipsParallelSnippetGeneratorTest, MemoryUse) { // LB reads from memory. // - LB // - Op0 Explicit Def RegClass(GPR32) diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp b/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/AnalysisTest.cpp @@ -1,4 +1,4 @@ -//===-- AnalysisTest.cpp ---------------------------------------*- C++ -*-===// +//===-- PPCAnalysisTest.cpp ---------------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -23,9 +23,9 @@ using testing::Pair; using testing::UnorderedElementsAre; -class AnalysisTest : public ::testing::Test { +class PPCAnalysisTest : public ::testing::Test { protected: - AnalysisTest() { + PPCAnalysisTest() { const std::string TT = "powerpc64le-unknown-linux"; std::string error; const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error); @@ -69,19 +69,19 @@ uint16_t IPAGENIdx = 0; }; -TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_2ALU) { +TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_2ALU) { const auto Pressure = computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 2}}); EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 2.0))); } -TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_1ALUE) { +TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALUE) { const auto Pressure = computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUEIdx, 2}}); EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUEIdx, 2.0))); } -TEST_F(AnalysisTest, ComputeIdealizedProcResPressure_1ALU1IPAGEN) { +TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALU1IPAGEN) { const auto Pressure = computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 1}, {IPAGENIdx, 1}}); EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 1.0),Pair(IPAGENIdx, 1))); diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/CMakeLists.txt @@ -1,10 +1,10 @@ -include_directories( +add_llvm_exegesis_unittest_includes( ${LLVM_MAIN_SRC_DIR}/lib/Target/PowerPC ${LLVM_BINARY_DIR}/lib/Target/PowerPC ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) -set(LLVM_LINK_COMPONENTS +add_llvm_exegesis_unittest_link_components( MC MCParser Object @@ -13,11 +13,10 @@ PowerPC ) -add_llvm_target_unittest(LLVMExegesisPowerPCTests +add_llvm_exegesis_unittest_sources( AnalysisTest.cpp SnippetGeneratorTest.cpp TargetTest.cpp ) -target_link_libraries(LLVMExegesisPowerPCTests PRIVATE - LLVMExegesis +add_llvm_exegesis_unittest_link_libraries( LLVMExegesisPowerPC) diff --git a/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/PowerPC/SnippetGeneratorTest.cpp @@ -29,12 +29,10 @@ MATCHER(IsInvalid, "") { return !arg.isValid(); } MATCHER(IsReg, "") { return arg.isReg(); } -class PPCSnippetGeneratorTest : public PPCTestBase {}; - template -class SnippetGeneratorTest : public PPCSnippetGeneratorTest { +class PPCSnippetGeneratorTest : public PPCTestBase { protected: - SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} + PPCSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} std::vector checkAndGetCodeTemplates(unsigned Opcode) { randomGenerator().seed(0); // Initialize seed. @@ -48,12 +46,12 @@ SnippetGeneratorT Generator; }; -using SerialSnippetGeneratorTest = SnippetGeneratorTest; +using PPCSerialSnippetGeneratorTest = PPCSnippetGeneratorTest; -using ParallelSnippetGeneratorTest = - SnippetGeneratorTest; +using PPCParallelSnippetGeneratorTest = + PPCSnippetGeneratorTest; -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { +TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { // - ADD8 // - Op0 Explicit Def RegClass(G8RC) // - Op1 Explicit Use RegClass(G8RC) @@ -77,7 +75,7 @@ << "Op0 is either set to Op1 or to Op2"; } -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { +TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { // - RLDIMI // - Op0 Explicit Def RegClass(G8RC) @@ -105,7 +103,7 @@ EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set"; } -TEST_F(ParallelSnippetGeneratorTest, MemoryUse) { +TEST_F(PPCParallelSnippetGeneratorTest, MemoryUse) { // - LDX // - Op0 Explicit Def RegClass(G8RC) // - Op1 Explicit Use Memory RegClass(GPRC) diff --git a/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp @@ -28,11 +28,6 @@ namespace llvm { namespace exegesis { -bool operator==(const BenchmarkMeasure &A, const BenchmarkMeasure &B) { - return std::tie(A.Key, A.PerInstructionValue, A.PerSnippetValue) == - std::tie(B.Key, B.PerInstructionValue, B.PerSnippetValue); -} - static std::string Dump(const MCInst &McInst) { std::string Buffer; raw_string_ostream OS(Buffer); diff --git a/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt b/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt --- a/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt +++ b/llvm/unittests/tools/llvm-exegesis/X86/CMakeLists.txt @@ -1,10 +1,21 @@ -include_directories( +add_llvm_exegesis_unittest_includes( ${LLVM_MAIN_SRC_DIR}/lib/Target/X86 ${LLVM_BINARY_DIR}/lib/Target/X86 ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib ) -set(LLVM_LINK_COMPONENTS +add_llvm_exegesis_unittest_sources( + AssemblerTest.cpp + BenchmarkResultTest.cpp + RegisterAliasingTest.cpp + SchedClassResolutionTest.cpp + SnippetFileTest.cpp + SnippetGeneratorTest.cpp + SnippetRepetitorTest.cpp + TargetTest.cpp + ) + +add_llvm_exegesis_unittest_link_components( Core Codegen MC @@ -15,16 +26,7 @@ X86 ) -add_llvm_target_unittest(LLVMExegesisX86Tests - AssemblerTest.cpp - BenchmarkResultTest.cpp - RegisterAliasingTest.cpp - SchedClassResolutionTest.cpp - SnippetFileTest.cpp - SnippetGeneratorTest.cpp - SnippetRepetitorTest.cpp - TargetTest.cpp +add_llvm_exegesis_unittest_link_libraries( + LLVMExegesisX86 ) -target_link_libraries(LLVMExegesisX86Tests PRIVATE - LLVMExegesis - LLVMExegesisX86) +message("Sources: ${exegesis_sources} Comps: ${LLVM_LINK_COMPONENTS} Libs: ${exegesis_link_libraries}") diff --git a/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/RegisterAliasingTest.cpp @@ -1,4 +1,4 @@ -//===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===// +//===-- X86RegisterAliasingTest.cpp --------------------------------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -23,9 +23,9 @@ namespace exegesis { namespace { -class RegisterAliasingTest : public X86TestBase {}; +class X86RegisterAliasingTest : public X86TestBase {}; -TEST_F(RegisterAliasingTest, TrackSimpleRegister) { +TEST_F(X86RegisterAliasingTest, TrackSimpleRegister) { const auto &RegInfo = State.getRegInfo(); const RegisterAliasingTracker tracker(RegInfo, X86::EAX); std::set ActualAliasedRegisters; @@ -39,7 +39,7 @@ } } -TEST_F(RegisterAliasingTest, TrackRegisterClass) { +TEST_F(X86RegisterAliasingTest, TrackRegisterClass) { // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for // AL, BL, CL and DL. const auto &RegInfo = State.getRegInfo(); @@ -57,7 +57,7 @@ ASSERT_THAT(RegClassTracker.aliasedBits(), sum); } -TEST_F(RegisterAliasingTest, TrackRegisterClassCache) { +TEST_F(X86RegisterAliasingTest, TrackRegisterClassCache) { // Fetching twice the same tracker yields the same pointers. const auto &RegInfo = State.getRegInfo(); const BitVector NoReservedReg(RegInfo.getNumRegs()); diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SchedClassResolutionTest.cpp @@ -24,9 +24,9 @@ using testing::Pair; using testing::UnorderedElementsAre; -class SchedClassResolutionTest : public X86TestBase { +class X86SchedClassResolutionTest : public X86TestBase { protected: - SchedClassResolutionTest() : STI(State.getSubtargetInfo()) { + X86SchedClassResolutionTest() : STI(State.getSubtargetInfo()) { // Compute the ProxResIdx of ports uses in tests. const auto &SM = STI.getSchedModel(); for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) { @@ -63,20 +63,20 @@ uint16_t P0156Idx = 0; }; -TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) { +TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) { const auto Pressure = computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}}); EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0))); } -TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) { +TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) { const auto Pressure = computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}}); EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0))); } -TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) { +TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) { const auto Pressure = computeIdealizedProcResPressure( STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}}); EXPECT_THAT(Pressure, @@ -84,7 +84,7 @@ Pair(P5Idx, 1.0), Pair(P6Idx, 1.0))); } -TEST_F(SchedClassResolutionTest, +TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_1P1_1P05_2P0156) { const auto Pressure = computeIdealizedProcResPressure( STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}}); diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -35,17 +35,11 @@ MATCHER(IsInvalid, "") { return !arg.isValid(); } MATCHER(IsReg, "") { return arg.isReg(); } -class X86SnippetGeneratorTest : public X86TestBase { -protected: - X86SnippetGeneratorTest() : InstrInfo(State.getInstrInfo()) {} - - const MCInstrInfo &InstrInfo; -}; - template -class SnippetGeneratorTest : public X86SnippetGeneratorTest { +class X86SnippetGeneratorTest : public X86TestBase { protected: - SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} + X86SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()), + InstrInfo(State.getInstrInfo()) {} std::vector checkAndGetCodeTemplates(unsigned Opcode) { randomGenerator().seed(0); // Initialize seed. @@ -57,14 +51,15 @@ } SnippetGeneratorT Generator; + const MCInstrInfo &InstrInfo; }; -using SerialSnippetGeneratorTest = SnippetGeneratorTest; +using X86SerialSnippetGeneratorTest = X86SnippetGeneratorTest; -using ParallelSnippetGeneratorTest = - SnippetGeneratorTest; +using X86ParallelSnippetGeneratorTest = + X86SnippetGeneratorTest; -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) { +TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) { // - ADC16i16 // - Op0 Explicit Use Immediate // - Op1 Implicit Def Reg(AX) @@ -90,7 +85,7 @@ EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set"; } -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { +TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { // - ADD16ri // - Op0 Explicit Def RegClass(GR16) // - Op1 Explicit Use RegClass(GR16) TiedToOp0 @@ -114,7 +109,7 @@ EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set"; } -TEST_F(SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { +TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { // - VXORPSrr // - Op0 Explicit Def RegClass(VR128) // - Op1 Explicit Use RegClass(VR128) @@ -138,7 +133,7 @@ << "Op0 is either set to Op1 or to Op2"; } -TEST_F(SerialSnippetGeneratorTest, +TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegsForbidAll) { // - VXORPSrr // - Op0 Explicit Def RegClass(VR128) @@ -159,7 +154,7 @@ consumeError(std::move(Error)); } -TEST_F(SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) { +TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) { // - CMP64rr // - Op0 Explicit Use RegClass(GR64) // - Op1 Explicit Use RegClass(GR64) @@ -183,7 +178,7 @@ } } -TEST_F(SerialSnippetGeneratorTest, LAHF) { +TEST_F(X86SerialSnippetGeneratorTest, LAHF) { // - LAHF // - Op0 Implicit Def Reg(AH) // - Op1 Implicit Use Reg(EFLAGS) @@ -199,7 +194,7 @@ } } -TEST_F(SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) { +TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) { // - VCVTUSI642SDZrrb_Int // - Op0 Explicit Def RegClass(VR128X) // - Op1 Explicit Use RegClass(VR128X) @@ -218,7 +213,7 @@ ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm()); } -TEST_F(ParallelSnippetGeneratorTest, ParallelInstruction) { +TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) { // - BNDCL32rr // - Op0 Explicit Use RegClass(BNDR) // - Op1 Explicit Use RegClass(GR32) @@ -238,7 +233,7 @@ EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()); } -TEST_F(ParallelSnippetGeneratorTest, SerialInstruction) { +TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) { // - CDQ // - Op0 Implicit Def Reg(EAX) // - Op1 Implicit Def Reg(EDX) @@ -257,7 +252,7 @@ ASSERT_THAT(IT.getVariableValues(), SizeIs(0)); } -TEST_F(ParallelSnippetGeneratorTest, StaticRenaming) { +TEST_F(X86ParallelSnippetGeneratorTest, StaticRenaming) { // CMOV32rr has tied variables, we enumerate the possible values to execute // as many in parallel as possible. @@ -288,7 +283,7 @@ << "Each instruction writes to a different register"; } -TEST_F(ParallelSnippetGeneratorTest, NoTiedVariables) { +TEST_F(X86ParallelSnippetGeneratorTest, NoTiedVariables) { // CMOV_GR32 has no tied variables, we make sure def and use are different // from each other. @@ -322,7 +317,7 @@ EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()); } -TEST_F(ParallelSnippetGeneratorTest, MemoryUse) { +TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) { // Mov32rm reads from memory. // - MOV32rm // - Op0 Explicit Def RegClass(GR32) @@ -356,7 +351,7 @@ EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u); } -TEST_F(ParallelSnippetGeneratorTest, MOV16ms) { +TEST_F(X86ParallelSnippetGeneratorTest, MOV16ms) { const unsigned Opcode = X86::MOV16ms; const Instruction &Instr = State.getIC().getInstr(Opcode); std::vector Benchmarks; @@ -367,9 +362,9 @@ testing::HasSubstr("no available registers")); } -class FakeSnippetGenerator : public SnippetGenerator { +class X86FakeSnippetGenerator : public SnippetGenerator { public: - FakeSnippetGenerator(const LLVMState &State, const Options &Opts) + X86FakeSnippetGenerator(const LLVMState &State, const Options &Opts) : SnippetGenerator(State, Opts) {} const Instruction &getInstr(unsigned Opcode) { @@ -387,7 +382,7 @@ } }; -using FakeSnippetGeneratorTest = SnippetGeneratorTest; +using X86FakeSnippetGeneratorTest = X86SnippetGeneratorTest; testing::Matcher IsRegisterValue(unsigned Reg, APInt Value) { @@ -395,7 +390,7 @@ testing::Field(&RegisterValue::Value, Value)); } -TEST_F(FakeSnippetGeneratorTest, MemoryUse_Movsb) { +TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) { // MOVSB writes to scratch memory register. // - MOVSB // - Op0 Explicit Use Memory RegClass(GR8) @@ -421,7 +416,7 @@ consumeError(std::move(Error)); } -TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) { +TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) { // ADD16ri: // explicit def 0 : reg RegClass=GR16 // explicit use 1 : reg RegClass=GR16 | TIED_TO:0 @@ -435,7 +430,7 @@ EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt()))); } -TEST_F(FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) { +TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) { // ADD64rr: // mov64ri rax, 42 // add64rr rax, rax, rbx diff --git a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp --- a/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp +++ b/llvm/unittests/tools/llvm-exegesis/X86/TargetTest.cpp @@ -126,26 +126,26 @@ LLVMState State; }; -class Core2TargetTest : public X86TargetTest { +class X86Core2TargetTest : public X86TargetTest { public: - Core2TargetTest() : X86TargetTest("") {} + X86Core2TargetTest() : X86TargetTest("") {} }; -class Core2AvxTargetTest : public X86TargetTest { +class X86Core2AvxTargetTest : public X86TargetTest { public: - Core2AvxTargetTest() : X86TargetTest("+avx") {} + X86Core2AvxTargetTest() : X86TargetTest("+avx") {} }; -class Core2Avx512TargetTest : public X86TargetTest { +class X86Core2Avx512TargetTest : public X86TargetTest { public: - Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {} + X86Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {} }; -TEST_F(Core2TargetTest, NoHighByteRegs) { +TEST_F(X86Core2TargetTest, NoHighByteRegs) { EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH)); } -TEST_F(Core2TargetTest, SetFlags) { +TEST_F(X86Core2TargetTest, SetFlags) { const unsigned Reg = X86::EFLAGS; EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)), ElementsAre(IsStackAllocate(8), @@ -154,35 +154,35 @@ OpcodeIs(X86::POPF64))); } -TEST_F(Core2TargetTest, SetRegToGR8Value) { +TEST_F(X86Core2TargetTest, SetRegToGR8Value) { const uint8_t Value = 0xFFU; const unsigned Reg = X86::AL; EXPECT_THAT(setRegTo(Reg, APInt(8, Value)), ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value))); } -TEST_F(Core2TargetTest, SetRegToGR16Value) { +TEST_F(X86Core2TargetTest, SetRegToGR16Value) { const uint16_t Value = 0xFFFFU; const unsigned Reg = X86::BX; EXPECT_THAT(setRegTo(Reg, APInt(16, Value)), ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value))); } -TEST_F(Core2TargetTest, SetRegToGR32Value) { +TEST_F(X86Core2TargetTest, SetRegToGR32Value) { const uint32_t Value = 0x7FFFFU; const unsigned Reg = X86::ECX; EXPECT_THAT(setRegTo(Reg, APInt(32, Value)), ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value))); } -TEST_F(Core2TargetTest, SetRegToGR64Value) { +TEST_F(X86Core2TargetTest, SetRegToGR64Value) { const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL; const unsigned Reg = X86::RDX; EXPECT_THAT(setRegTo(Reg, APInt(64, Value)), ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value))); } -TEST_F(Core2TargetTest, SetRegToVR64Value) { +TEST_F(X86Core2TargetTest, SetRegToVR64Value) { EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)), ElementsAre(IsStackAllocate(8), IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0), @@ -191,7 +191,7 @@ IsStackDeallocate(8))); } -TEST_F(Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) { +TEST_F(X86Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) { EXPECT_THAT( setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), ElementsAre(IsStackAllocate(16), @@ -203,7 +203,7 @@ IsStackDeallocate(16))); } -TEST_F(Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) { +TEST_F(X86Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) { EXPECT_THAT( setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), ElementsAre(IsStackAllocate(16), @@ -215,7 +215,7 @@ IsStackDeallocate(16))); } -TEST_F(Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) { +TEST_F(X86Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) { EXPECT_THAT( setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)), ElementsAre(IsStackAllocate(16), @@ -227,7 +227,7 @@ IsStackDeallocate(16))); } -TEST_F(Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) { +TEST_F(X86Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) { const char ValueStr[] = "1111111122222222333333334444444455555555666666667777777788888888"; EXPECT_THAT( @@ -245,7 +245,7 @@ IsStackDeallocate(32)})); } -TEST_F(Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) { +TEST_F(X86Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) { const char ValueStr[] = "1111111122222222333333334444444455555555666666667777777788888888"; EXPECT_THAT( @@ -263,7 +263,7 @@ IsStackDeallocate(32)})); } -TEST_F(Core2Avx512TargetTest, SetRegToVR512Value) { +TEST_F(X86Core2Avx512TargetTest, SetRegToVR512Value) { const char ValueStr[] = "1111111122222222333333334444444455555555666666667777777788888888" "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000"; @@ -293,7 +293,7 @@ // Note: We always put 80 bits on the stack independently of the size of the // value. This uses a bit more space but makes the code simpler. -TEST_F(Core2TargetTest, SetRegToST0_32Bits) { +TEST_F(X86Core2TargetTest, SetRegToST0_32Bits) { EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0), @@ -302,7 +302,7 @@ OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToST1_32Bits) { +TEST_F(X86Core2TargetTest, SetRegToST1_32Bits) { const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1); EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)), ElementsAre(IsStackAllocate(10), @@ -313,7 +313,7 @@ IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToST0_64Bits) { +TEST_F(X86Core2TargetTest, SetRegToST0_64Bits) { EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0), @@ -322,7 +322,7 @@ OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToST0_80Bits) { +TEST_F(X86Core2TargetTest, SetRegToST0_80Bits) { EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0), @@ -331,7 +331,7 @@ OpcodeIs(X86::LD_F80m), IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToFP0_80Bits) { +TEST_F(X86Core2TargetTest, SetRegToFP0_80Bits) { EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0), @@ -340,7 +340,7 @@ OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToFP1_32Bits) { +TEST_F(X86Core2TargetTest, SetRegToFP1_32Bits) { EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0), @@ -349,7 +349,7 @@ OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } -TEST_F(Core2TargetTest, SetRegToFP1_4Bits) { +TEST_F(X86Core2TargetTest, SetRegToFP1_4Bits) { EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)), ElementsAre(IsStackAllocate(10), IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0), @@ -358,7 +358,7 @@ OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10))); } -TEST_F(Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) { +TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) { const Instruction &I = getInstr(X86::ADD64rm); InstructionTemplate IT(&I); constexpr const int kOffset = 42; @@ -371,7 +371,7 @@ EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0)); } -TEST_F(Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) { +TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) { const Instruction &I = getInstr(X86::VGATHERDPSZ128rm); InstructionTemplate IT(&I); constexpr const int kOffset = 42; @@ -384,7 +384,7 @@ EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0)); } -TEST_F(Core2TargetTest, AllowAsBackToBack) { +TEST_F(X86Core2TargetTest, AllowAsBackToBack) { EXPECT_TRUE( State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr))); EXPECT_FALSE(