diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -1212,13 +1212,13 @@
 // 7.4. Vector Unit-Stride Instructions
 def vle1: RVVVLEMaskBuiltin;
 defm vle8: RVVVLEBuiltin<["c"]>;
-defm vle16: RVVVLEBuiltin<["s"]>;
+defm vle16: RVVVLEBuiltin<["s","x"]>;
 defm vle32: RVVVLEBuiltin<["i","f"]>;
 defm vle64: RVVVLEBuiltin<["l","d"]>;
 
 def vse1 : RVVVSEMaskBuiltin;
 defm vse8 : RVVVSEBuiltin<["c"]>;
-defm vse16: RVVVSEBuiltin<["s"]>;
+defm vse16: RVVVSEBuiltin<["s","x"]>;
 defm vse32: RVVVSEBuiltin<["i","f"]>;
 defm vse64: RVVVSEBuiltin<["l","d"]>;
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vle.c
@@ -1,11 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
 // RUN:   -disable-O0-optnone  -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -16,7 +16,6 @@
   return vle8_v_i8mf8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -27,7 +26,6 @@
   return vle8_v_i8mf4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -38,7 +36,6 @@
   return vle8_v_i8mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -49,7 +46,6 @@
   return vle8_v_i8m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -60,7 +56,6 @@
   return vle8_v_i8m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -71,7 +66,6 @@
   return vle8_v_i8m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -82,7 +76,6 @@
   return vle8_v_i8m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -93,7 +86,6 @@
   return vle16_v_i16mf4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -104,7 +96,6 @@
   return vle16_v_i16mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -115,7 +106,6 @@
   return vle16_v_i16m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -126,7 +116,6 @@
   return vle16_v_i16m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -137,7 +126,6 @@
   return vle16_v_i16m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -148,7 +136,6 @@
   return vle16_v_i16m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -159,7 +146,6 @@
   return vle32_v_i32mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -170,7 +156,6 @@
   return vle32_v_i32m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -181,7 +166,6 @@
   return vle32_v_i32m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -192,7 +176,6 @@
   return vle32_v_i32m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -203,7 +186,6 @@
   return vle32_v_i32m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -214,7 +196,6 @@
   return vle64_v_i64m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -225,7 +206,6 @@
   return vle64_v_i64m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -236,7 +216,6 @@
   return vle64_v_i64m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -247,7 +226,6 @@
   return vle64_v_i64m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -258,7 +236,6 @@
   return vle8_v_u8mf8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -269,7 +246,6 @@
   return vle8_v_u8mf4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -280,7 +256,6 @@
   return vle8_v_u8mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -291,7 +266,6 @@
   return vle8_v_u8m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -302,7 +276,6 @@
   return vle8_v_u8m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -313,7 +286,6 @@
   return vle8_v_u8m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -324,7 +296,6 @@
   return vle8_v_u8m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -335,7 +306,6 @@
   return vle16_v_u16mf4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -346,7 +316,6 @@
   return vle16_v_u16mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -357,7 +326,6 @@
   return vle16_v_u16m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -368,7 +336,6 @@
   return vle16_v_u16m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -379,7 +346,6 @@
   return vle16_v_u16m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -390,7 +356,6 @@
   return vle16_v_u16m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -401,7 +366,6 @@
   return vle32_v_u32mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -412,7 +376,6 @@
   return vle32_v_u32m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -423,7 +386,6 @@
   return vle32_v_u32m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -434,7 +396,6 @@
   return vle32_v_u32m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -445,7 +406,6 @@
   return vle32_v_u32m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -456,7 +416,6 @@
   return vle64_v_u64m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -467,7 +426,6 @@
   return vle64_v_u64m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -478,7 +436,6 @@
   return vle64_v_u64m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -489,7 +446,6 @@
   return vle64_v_u64m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
@@ -500,7 +456,6 @@
   return vle32_v_f32mf2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
@@ -511,7 +466,6 @@
   return vle32_v_f32m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
@@ -522,7 +476,6 @@
   return vle32_v_f32m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
@@ -533,7 +486,6 @@
   return vle32_v_f32m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
@@ -544,7 +496,6 @@
   return vle32_v_f32m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
@@ -555,7 +506,6 @@
   return vle64_v_f64m1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
@@ -566,7 +516,6 @@
   return vle64_v_f64m2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
@@ -577,7 +526,6 @@
   return vle64_v_f64m4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
@@ -588,7 +536,6 @@
   return vle64_v_f64m8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -599,7 +546,6 @@
   return vle8_v_i8mf8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -610,7 +556,6 @@
   return vle8_v_i8mf4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -621,7 +566,6 @@
   return vle8_v_i8mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -632,7 +576,6 @@
   return vle8_v_i8m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -643,7 +586,6 @@
   return vle8_v_i8m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -654,7 +596,6 @@
   return vle8_v_i8m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_i8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -665,7 +606,6 @@
   return vle8_v_i8m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -676,7 +616,6 @@
   return vle16_v_i16mf4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -687,7 +626,6 @@
   return vle16_v_i16mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -698,7 +636,6 @@
   return vle16_v_i16m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -709,7 +646,6 @@
   return vle16_v_i16m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -720,7 +656,6 @@
   return vle16_v_i16m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_i16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -731,7 +666,6 @@
   return vle16_v_i16m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -742,7 +676,6 @@
   return vle32_v_i32mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -753,7 +686,6 @@
   return vle32_v_i32m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -764,7 +696,6 @@
   return vle32_v_i32m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -775,7 +706,6 @@
   return vle32_v_i32m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_i32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -786,7 +716,6 @@
   return vle32_v_i32m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -797,7 +726,6 @@
   return vle64_v_i64m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -808,7 +736,6 @@
   return vle64_v_i64m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -819,7 +746,6 @@
   return vle64_v_i64m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_i64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -830,7 +756,6 @@
   return vle64_v_i64m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -841,7 +766,6 @@
   return vle8_v_u8mf8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -852,7 +776,6 @@
   return vle8_v_u8mf4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -863,7 +786,6 @@
   return vle8_v_u8mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -874,7 +796,6 @@
   return vle8_v_u8m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -885,7 +806,6 @@
   return vle8_v_u8m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -896,7 +816,6 @@
   return vle8_v_u8m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle8_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -907,7 +826,6 @@
   return vle8_v_u8m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -918,7 +836,6 @@
   return vle16_v_u16mf4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -929,7 +846,6 @@
   return vle16_v_u16mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -940,7 +856,6 @@
   return vle16_v_u16m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -951,7 +866,6 @@
   return vle16_v_u16m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -962,7 +876,6 @@
   return vle16_v_u16m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle16_v_u16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -973,7 +886,6 @@
   return vle16_v_u16m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -984,7 +896,6 @@
   return vle32_v_u32mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -995,7 +906,6 @@
   return vle32_v_u32m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -1006,7 +916,6 @@
   return vle32_v_u32m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -1017,7 +926,6 @@
   return vle32_v_u32m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_u32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -1028,7 +936,6 @@
   return vle32_v_u32m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -1039,7 +946,6 @@
   return vle64_v_u64m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -1050,7 +956,6 @@
   return vle64_v_u64m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -1061,7 +966,6 @@
   return vle64_v_u64m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_u64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -1072,7 +976,6 @@
   return vle64_v_u64m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
@@ -1083,7 +986,6 @@
   return vle32_v_f32mf2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
@@ -1094,7 +996,6 @@
   return vle32_v_f32m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
@@ -1105,7 +1006,6 @@
   return vle32_v_f32m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
@@ -1116,7 +1016,6 @@
   return vle32_v_f32m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle32_v_f32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
@@ -1127,7 +1026,6 @@
   return vle32_v_f32m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
@@ -1138,7 +1036,6 @@
   return vle64_v_f64m1_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
@@ -1149,7 +1046,6 @@
   return vle64_v_f64m2_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
@@ -1160,7 +1056,6 @@
   return vle64_v_f64m4_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle64_v_f64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
@@ -1171,7 +1066,6 @@
   return vle64_v_f64m8_m(mask, maskedoff, base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
@@ -1182,7 +1076,6 @@
   return vle1_v_b1(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
@@ -1193,7 +1086,6 @@
   return vle1_v_b2(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
@@ -1204,7 +1096,6 @@
   return vle1_v_b4(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
@@ -1215,7 +1106,6 @@
   return vle1_v_b8(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
@@ -1226,7 +1116,6 @@
   return vle1_v_b16(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b32(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
@@ -1237,7 +1126,6 @@
   return vle1_v_b32(base, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vle1_v_b64(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
@@ -1247,3 +1135,63 @@
 vbool64_t test_vle1_v_b64(const uint8_t *base, size_t vl) {
   return vle1_v_b64(base, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 1 x half> @llvm.riscv.vle.nxv1f16.i64(<vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP1]]
+//
+vfloat16mf4_t test_vle16_v_f16mf4(const _Float16 *base, size_t vl) {
+  return vle16_v_f16mf4(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 2 x half> @llvm.riscv.vle.nxv2f16.i64(<vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP1]]
+//
+vfloat16mf2_t test_vle16_v_f16mf2(const _Float16 *base, size_t vl) {
+  return vle16_v_f16mf2(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 4 x half> @llvm.riscv.vle.nxv4f16.i64(<vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP1]]
+//
+vfloat16m1_t test_vle16_v_f16m1(const _Float16 *base, size_t vl) {
+  return vle16_v_f16m1(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 8 x half> @llvm.riscv.vle.nxv8f16.i64(<vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP1]]
+//
+vfloat16m2_t test_vle16_v_f16m2(const _Float16 *base, size_t vl) {
+  return vle16_v_f16m2(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 16 x half> @llvm.riscv.vle.nxv16f16.i64(<vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP1]]
+//
+vfloat16m4_t test_vle16_v_f16m4(const _Float16 *base, size_t vl) {
+  return vle16_v_f16m4(base, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vle16_v_f16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = call <vscale x 32 x half> @llvm.riscv.vle.nxv32f16.i64(<vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP1]]
+//
+vfloat16m8_t test_vle16_v_f16m8(const _Float16 *base, size_t vl) {
+  return vle16_v_f16m8(base, vl);
+}
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vse.c
@@ -1,11 +1,11 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \
-// RUN:   -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
+// RUN:   -target-feature +experimental-v -target-feature +experimental-zfh \
+// RUN:   -disable-O0-optnone  -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
 #include <riscv_vector.h>
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -16,7 +16,6 @@
   return vse8_v_i8mf8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -27,7 +26,6 @@
   return vse8_v_i8mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -38,7 +36,6 @@
   return vse8_v_i8mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -49,7 +46,6 @@
   return vse8_v_i8m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -60,7 +56,6 @@
   return vse8_v_i8m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -71,7 +66,6 @@
   return vse8_v_i8m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -82,7 +76,6 @@
   return vse8_v_i8m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -93,7 +86,6 @@
   return vse16_v_i16mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -104,7 +96,6 @@
   return vse16_v_i16mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -115,7 +106,6 @@
   return vse16_v_i16m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -126,7 +116,6 @@
   return vse16_v_i16m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -137,7 +126,6 @@
   return vse16_v_i16m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -148,7 +136,6 @@
   return vse16_v_i16m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -159,7 +146,6 @@
   return vse32_v_i32mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -170,7 +156,6 @@
   return vse32_v_i32m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -181,7 +166,6 @@
   return vse32_v_i32m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -192,7 +176,6 @@
   return vse32_v_i32m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -203,7 +186,6 @@
   return vse32_v_i32m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -214,7 +196,6 @@
   return vse64_v_i64m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -225,7 +206,6 @@
   return vse64_v_i64m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -236,7 +216,6 @@
   return vse64_v_i64m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -247,7 +226,6 @@
   return vse64_v_i64m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -258,7 +236,6 @@
   return vse8_v_u8mf8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -269,7 +246,6 @@
   return vse8_v_u8mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -280,7 +256,6 @@
   return vse8_v_u8mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -291,7 +266,6 @@
   return vse8_v_u8m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -302,7 +276,6 @@
   return vse8_v_u8m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -313,7 +286,6 @@
   return vse8_v_u8m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -324,7 +296,6 @@
   return vse8_v_u8m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16mf4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -335,7 +306,6 @@
   return vse16_v_u16mf4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -346,7 +316,6 @@
   return vse16_v_u16mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -357,7 +326,6 @@
   return vse16_v_u16m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -368,7 +336,6 @@
   return vse16_v_u16m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -379,7 +346,6 @@
   return vse16_v_u16m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -390,7 +356,6 @@
   return vse16_v_u16m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -401,7 +366,6 @@
   return vse32_v_u32mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -412,7 +376,6 @@
   return vse32_v_u32m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -423,7 +386,6 @@
   return vse32_v_u32m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -434,7 +396,6 @@
   return vse32_v_u32m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -445,7 +406,6 @@
   return vse32_v_u32m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -456,7 +416,6 @@
   return vse64_v_u64m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -467,7 +426,6 @@
   return vse64_v_u64m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -478,7 +436,6 @@
   return vse64_v_u64m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -489,7 +446,6 @@
   return vse64_v_u64m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32mf2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
@@ -500,7 +456,6 @@
   return vse32_v_f32mf2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
@@ -511,7 +466,6 @@
   return vse32_v_f32m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
@@ -522,7 +476,6 @@
   return vse32_v_f32m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
@@ -533,7 +486,6 @@
   return vse32_v_f32m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
@@ -544,7 +496,6 @@
   return vse32_v_f32m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
@@ -555,7 +506,6 @@
   return vse64_v_f64m1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
@@ -566,7 +516,6 @@
   return vse64_v_f64m2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
@@ -577,7 +526,6 @@
   return vse64_v_f64m4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
@@ -588,7 +536,6 @@
   return vse64_v_f64m8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -599,7 +546,6 @@
   return vse8_v_i8mf8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -610,7 +556,6 @@
   return vse8_v_i8mf4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -621,7 +566,6 @@
   return vse8_v_i8mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -632,7 +576,6 @@
   return vse8_v_i8m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -643,7 +586,6 @@
   return vse8_v_i8m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -654,7 +596,6 @@
   return vse8_v_i8m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_i8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -665,7 +606,6 @@
   return vse8_v_i8m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -676,7 +616,6 @@
   return vse16_v_i16mf4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -687,7 +626,6 @@
   return vse16_v_i16mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -698,7 +636,6 @@
   return vse16_v_i16m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -709,7 +646,6 @@
   return vse16_v_i16m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -720,7 +656,6 @@
   return vse16_v_i16m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_i16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -731,7 +666,6 @@
   return vse16_v_i16m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -742,7 +676,6 @@
   return vse32_v_i32mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -753,7 +686,6 @@
   return vse32_v_i32m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -764,7 +696,6 @@
   return vse32_v_i32m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -775,7 +706,6 @@
   return vse32_v_i32m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_i32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -786,7 +716,6 @@
   return vse32_v_i32m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -797,7 +726,6 @@
   return vse64_v_i64m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -808,7 +736,6 @@
   return vse64_v_i64m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -819,7 +746,6 @@
   return vse64_v_i64m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_i64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -830,7 +756,6 @@
   return vse64_v_i64m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i8>*
@@ -841,7 +766,6 @@
   return vse8_v_u8mf8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i8>*
@@ -852,7 +776,6 @@
   return vse8_v_u8mf4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i8>*
@@ -863,7 +786,6 @@
   return vse8_v_u8mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i8>*
@@ -874,7 +796,6 @@
   return vse8_v_u8m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i8>*
@@ -885,7 +806,6 @@
   return vse8_v_u8m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i8>*
@@ -896,7 +816,6 @@
   return vse8_v_u8m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse8_v_u8m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i8>*
@@ -907,7 +826,6 @@
   return vse8_v_u8m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16mf4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 1 x i16>*
@@ -918,7 +836,6 @@
   return vse16_v_u16mf4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 2 x i16>*
@@ -929,7 +846,6 @@
   return vse16_v_u16mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 4 x i16>*
@@ -940,7 +856,6 @@
   return vse16_v_u16m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 8 x i16>*
@@ -951,7 +866,6 @@
   return vse16_v_u16m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 16 x i16>*
@@ -962,7 +876,6 @@
   return vse16_v_u16m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse16_v_u16m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <vscale x 32 x i16>*
@@ -973,7 +886,6 @@
   return vse16_v_u16m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 1 x i32>*
@@ -984,7 +896,6 @@
   return vse32_v_u32mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 2 x i32>*
@@ -995,7 +906,6 @@
   return vse32_v_u32m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 4 x i32>*
@@ -1006,7 +916,6 @@
   return vse32_v_u32m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 8 x i32>*
@@ -1017,7 +926,6 @@
   return vse32_v_u32m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_u32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <vscale x 16 x i32>*
@@ -1028,7 +936,6 @@
   return vse32_v_u32m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 1 x i64>*
@@ -1039,7 +946,6 @@
   return vse64_v_u64m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 2 x i64>*
@@ -1050,7 +956,6 @@
   return vse64_v_u64m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 4 x i64>*
@@ -1061,7 +966,6 @@
   return vse64_v_u64m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_u64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i64* [[BASE:%.*]] to <vscale x 8 x i64>*
@@ -1072,7 +976,6 @@
   return vse64_v_u64m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32mf2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 1 x float>*
@@ -1083,7 +986,6 @@
   return vse32_v_f32mf2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 2 x float>*
@@ -1094,7 +996,6 @@
   return vse32_v_f32m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 4 x float>*
@@ -1105,7 +1006,6 @@
   return vse32_v_f32m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 8 x float>*
@@ -1116,7 +1016,6 @@
   return vse32_v_f32m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse32_v_f32m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast float* [[BASE:%.*]] to <vscale x 16 x float>*
@@ -1127,7 +1026,6 @@
   return vse32_v_f32m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m1_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 1 x double>*
@@ -1138,7 +1036,6 @@
   return vse64_v_f64m1_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m2_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 2 x double>*
@@ -1149,7 +1046,6 @@
   return vse64_v_f64m2_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m4_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 4 x double>*
@@ -1160,7 +1056,6 @@
   return vse64_v_f64m4_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse64_v_f64m8_m(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast double* [[BASE:%.*]] to <vscale x 8 x double>*
@@ -1171,7 +1066,6 @@
   return vse64_v_f64m8_m(mask, base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 64 x i1>*
@@ -1182,7 +1076,6 @@
   return vse1_v_b1(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b2(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 32 x i1>*
@@ -1193,7 +1086,6 @@
   return vse1_v_b2(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b4(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 16 x i1>*
@@ -1204,7 +1096,6 @@
   return vse1_v_b4(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b8(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 8 x i1>*
@@ -1215,7 +1106,6 @@
   return vse1_v_b8(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b16(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 4 x i1>*
@@ -1226,7 +1116,6 @@
   return vse1_v_b16(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b32(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 2 x i1>*
@@ -1237,7 +1126,6 @@
   return vse1_v_b32(base, value, vl);
 }
 
-//
 // CHECK-RV64-LABEL: @test_vse1_v_b64(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast i8* [[BASE:%.*]] to <vscale x 1 x i1>*
@@ -1247,3 +1135,63 @@
 void test_vse1_v_b64(uint8_t *base, vbool64_t value, size_t vl) {
   return vse1_v_b64(base, value, vl);
 }
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16mf4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 1 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv1f16.i64(<vscale x 1 x half> [[VALUE:%.*]], <vscale x 1 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16mf4(_Float16 *base, vfloat16mf4_t value, size_t vl) {
+  return vse16_v_f16mf4(base, value, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16mf2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 2 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv2f16.i64(<vscale x 2 x half> [[VALUE:%.*]], <vscale x 2 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16mf2(_Float16 *base, vfloat16mf2_t value, size_t vl) {
+  return vse16_v_f16mf2(base, value, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16m1(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 4 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv4f16.i64(<vscale x 4 x half> [[VALUE:%.*]], <vscale x 4 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16m1(_Float16 *base, vfloat16m1_t value, size_t vl) {
+  return vse16_v_f16m1(base, value, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16m2(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 8 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> [[VALUE:%.*]], <vscale x 8 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16m2(_Float16 *base, vfloat16m2_t value, size_t vl) {
+  return vse16_v_f16m2(base, value, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16m4(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 16 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv16f16.i64(<vscale x 16 x half> [[VALUE:%.*]], <vscale x 16 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16m4(_Float16 *base, vfloat16m4_t value, size_t vl) {
+  return vse16_v_f16m4(base, value, vl);
+}
+
+// CHECK-RV64-LABEL: @test_vse16_v_f16m8(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast half* [[BASE:%.*]] to <vscale x 32 x half>*
+// CHECK-RV64-NEXT:    call void @llvm.riscv.vse.nxv32f16.i64(<vscale x 32 x half> [[VALUE:%.*]], <vscale x 32 x half>* [[TMP0]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:    ret void
+//
+void test_vse16_v_f16m8(_Float16 *base, vfloat16m8_t value, size_t vl) {
+  return vse16_v_f16m8(base, value, vl);
+}