Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp =================================================================== --- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -61,6 +61,7 @@ #include "llvm/ADT/SetOperations.h" #include "llvm/ADT/SmallSet.h" #include "llvm/CodeGen/LivePhysRegs.h" +#include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineLoopUtils.h" @@ -359,6 +360,7 @@ MachineBasicBlock *Preheader = nullptr; MachineLoopInfo &MLI; ReachingDefAnalysis &RDA; + MachineDominatorTree &DT; const TargetRegisterInfo &TRI; const ARMBaseInstrInfo &TII; MachineFunction *MF = nullptr; @@ -375,9 +377,9 @@ bool CannotTailPredicate = false; LowOverheadLoop(MachineLoop &ML, MachineLoopInfo &MLI, - ReachingDefAnalysis &RDA, const TargetRegisterInfo &TRI, - const ARMBaseInstrInfo &TII) - : ML(ML), MLI(MLI), RDA(RDA), TRI(TRI), TII(TII), + ReachingDefAnalysis &RDA, MachineDominatorTree &DT, + const TargetRegisterInfo &TRI, const ARMBaseInstrInfo &TII) + : ML(ML), MLI(MLI), RDA(RDA), DT(DT), TRI(TRI), TII(TII), TPNumElements(MachineOperand::CreateImm(0)) { MF = ML.getHeader()->getParent(); if (auto *MBB = ML.getLoopPreheader()) @@ -469,6 +471,7 @@ MachineFunction *MF = nullptr; MachineLoopInfo *MLI = nullptr; ReachingDefAnalysis *RDA = nullptr; + MachineDominatorTree *DT = nullptr; const ARMBaseInstrInfo *TII = nullptr; MachineRegisterInfo *MRI = nullptr; const TargetRegisterInfo *TRI = nullptr; @@ -483,6 +486,7 @@ AU.setPreservesCFG(); AU.addRequired(); AU.addRequired(); + AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -858,6 +862,7 @@ static bool producesFalseLanesZero(MachineInstr &MI, const TargetRegisterClass *QPRs, const ReachingDefAnalysis &RDA, + const MachineDominatorTree &DT, InstSet &FalseLanesZero) { if (canGenerateNonZeros(MI)) return false; @@ -874,6 +879,30 @@ Def->getOperand(1).getImm() == 0; }; + // An unpredicated VORR on identical operands mimics a VMOV and doesn't modify + // the incoming lane values, so it produces zeroed false lanes if the operand + // def does + if (MI.getOpcode() == ARM::MVE_VORR && + MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) { + SmallPtrSet Defs; + RDA.getGlobalReachingDefs(&MI, MI.getOperand(1).getReg(), Defs); + + bool Valid = true; + // The VORR isn't valid if the def of its operand is in the loop and doesn't + // produce zero false lanes. Ignore defs that come later in the loop as they + // will be checked for validity later on + for (auto Def : Defs) { + if (!FalseLanesZero.contains(Def) && Def->getParent() == MI.getParent() && + !DT.dominates(&MI, Def)) { + Valid = false; + break; + } + } + + if (Valid) + return true; + } + bool AllowScalars = isHorizontalReduction(MI); for (auto &MO : MI.operands()) { if (!MO.isReg() || !MO.getReg()) @@ -940,7 +969,7 @@ if (isPredicated) Predicated.insert(&MI); - if (producesFalseLanesZero(MI, QPRs, RDA, FalseLanesZero)) + if (producesFalseLanesZero(MI, QPRs, RDA, DT, FalseLanesZero)) FalseLanesZero.insert(&MI); else if (MI.getNumDefs() == 0) continue; @@ -1250,6 +1279,7 @@ MLI = &getAnalysis(); RDA = &getAnalysis(); + DT = &getAnalysis(); MF->getProperties().set(MachineFunctionProperties::Property::TracksLiveness); MRI = &MF->getRegInfo(); TII = static_cast(ST.getInstrInfo()); @@ -1298,7 +1328,7 @@ return nullptr; }; - LowOverheadLoop LoLoop(*ML, *MLI, *RDA, *TRI, *TII); + LowOverheadLoop LoLoop(*ML, *MLI, *RDA, *DT, *TRI, *TII); // Search the preheader for the start intrinsic. // FIXME: I don't see why we shouldn't be supporting multiple predecessors // with potentially multiple set.loop.iterations, so we need to enable this. Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir @@ -281,6 +281,7 @@ ; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12 ; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us) ; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 + ; CHECK: $q2 = MVE_VORR $q0, $q0, 0, $noreg, undef $q2 ; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg ; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg @@ -289,9 +290,9 @@ ; CHECK: $lr = t2DLS renamable $r0 ; CHECK: bb.6.vector.body: ; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000) - ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 + ; CHECK: liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - ; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q2 + ; CHECK: $q2 = MVE_VORR killed $q1, killed $q2, 0, $noreg, undef $q2 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1012, align 2) ; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv46, align 2) @@ -439,6 +440,7 @@ renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load (s32) from %ir.arrayidx12.us) $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 + $q2 = MVE_VORR $q0, $q0, 0, $noreg, undef $q2 $r2 = tMOVr killed $lr, 14, $noreg renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg $r6 = tMOVr $r5, 14, $noreg @@ -448,10 +450,10 @@ bb.6.vector.body: successors: %bb.6(0x7c000000), %bb.7(0x04000000) - liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 + liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - $q2 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q2 + $q2 = MVE_VORR killed $q1, $q2, 0, $noreg, undef $q2 MVE_VPST 4, implicit $vpr renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv1012, align 2) renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv46, align 2) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir @@ -124,6 +124,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg @@ -132,14 +133,14 @@ ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $q1, $q2, $r0, $r1, $r2, $r3 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q2, 0, $noreg, undef $q0 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q1 = nsw MVE_VMULi32 renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 @@ -170,6 +171,7 @@ frame-setup CFI_INSTRUCTION offset $r7, -8 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg @@ -179,10 +181,10 @@ bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - liveins: $q1, $r0, $r1, $r2, $r3 + liveins: $q1, $q2, $r0, $r1, $r2, $r3 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + $q0 = MVE_VORR killed $q1, $q2, 0, $noreg, undef $q0 MVE_VPST 4, implicit $vpr renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir @@ -135,18 +135,19 @@ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 3, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + ; CHECK: renamable $q2 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $q0, $q2, $r0, $r1, $r2, $r3 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg - ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 + ; CHECK: $q1 = MVE_VORR killed $q0, killed $q2, 0, $noreg, undef $q1 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 8, 14 /* CC::al */, $noreg - ; CHECK: renamable $q0 = nuw MVE_VMULi16 killed renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 + ; CHECK: renamable $q0 = nuw MVE_VMULi16 renamable $q2, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: renamable $q0 = MVE_VSUBi16 renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0 ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2 ; CHECK: bb.3.middle.block: @@ -186,16 +187,17 @@ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg renamable $r3 = tLEApcrel %const.0, 14, $noreg renamable $r12 = t2LSRri killed renamable $r12, 3, 14, $noreg, $noreg - renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + renamable $q0 = MVE_VLDRWU32 renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + renamable $q2 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg $lr = t2DoLoopStart renamable $lr bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - liveins: $lr, $q0, $r0, $r1, $r2, $r3 + liveins: $lr, $q0, $q2, $r0, $r1, $r2, $r3 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg - $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 + $q1 = MVE_VORR killed $q0, $q2, 0, $noreg, undef $q1 MVE_VPST 4, implicit $vpr renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/vorr-false-lanes-zero.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/vorr-false-lanes-zero.mir @@ -0,0 +1,308 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s +--- | + + define arm_aapcs_vfpcc void @vorr_false_lanes_zero() { + entry: + ret void + } + + define arm_aapcs_vfpcc void @vorr_def_in_loop_after() { + entry: + ret void + } + + define arm_aapcs_vfpcc void @vorr_def_in_loop_before() { + entry: + ret void + } + +... +--- +name: vorr_false_lanes_zero +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: name: vorr_false_lanes_zero + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK: $lr = MVE_DLSTP_16 renamable $r3 + ; CHECK: bb.1: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12 + ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 + ; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg + ; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg + ; CHECK: dead renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, undef renamable $q5 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + ; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + ; CHECK: bb.3: + ; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + bb.0: + successors: %bb.1(0x80000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + $r9 = tMOVr $r3, 14 /* CC::al */, $noreg + renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3 + + bb.1: + successors: %bb.1(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 + + renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg + $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 + MVE_VPST 8, implicit $vpr + renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr + renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr + MVE_VPST 2, implicit $vpr + renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, undef renamable $q5 + renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg + $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + MVE_VPST 1, implicit $vpr + renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr + renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr + tB %bb.2, 14 /* CC::al */, $noreg + + bb.2: + successors: %bb.3(0x04000000), %bb.0(0x7c000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + + bb.3: + $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + +... +--- +name: vorr_def_in_loop_after +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: name: vorr_def_in_loop_after + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK: $lr = MVE_DLSTP_16 renamable $r3 + ; CHECK: bb.1: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12 + ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 + ; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg + ; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg + ; CHECK: dead renamable $q0 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, undef renamable $q0 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg + ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1 + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + ; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + ; CHECK: bb.3: + ; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + bb.0: + successors: %bb.1(0x80000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + $r9 = tMOVr $r3, 14 /* CC::al */, $noreg + renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3 + + bb.1: + successors: %bb.1(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 + + renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg + $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 + MVE_VPST 8, implicit $vpr + renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr + renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr + renamable $q0 = MVE_VSHR_immu16 renamable $q3, 11, 0, $noreg, undef renamable $q0 + MVE_VPST 2, implicit $vpr + renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg + $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + MVE_VPST 1, implicit $vpr + renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr + renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr + tB %bb.2, 14 /* CC::al */, $noreg + + bb.2: + successors: %bb.3(0x04000000), %bb.0(0x7c000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + + bb.3: + $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + +... +--- +name: vorr_def_in_loop_before +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +stack: + - { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8, + stack-id: default, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +body: | + ; CHECK-LABEL: name: vorr_def_in_loop_before + ; CHECK: bb.0: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + ; CHECK: $r9 = tMOVr $r3, 14 /* CC::al */, $noreg + ; CHECK: $lr = t2DLS renamable $r1 + ; CHECK: bb.1: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 + ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg + ; CHECK: renamable $q0 = MVE_VSHR_immu16 killed renamable $q0, 11, 0, $noreg, undef renamable $q0 + ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 + ; CHECK: MVE_VPST 8, implicit $vpr + ; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr + ; CHECK: dead renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr + ; CHECK: MVE_VPST 2, implicit $vpr + ; CHECK: renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: MVE_VPST 1, implicit $vpr + ; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr + ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1 + ; CHECK: bb.2: + ; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000) + ; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + ; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + ; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + ; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + ; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + ; CHECK: bb.3: + ; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + ; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + ; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + bb.0: + successors: %bb.1(0x80000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + $r6 = tMOVr $r2, 14 /* CC::al */, $noreg + $r0 = tMOVr $r12, 14 /* CC::al */, $noreg + $r9 = tMOVr $r3, 14 /* CC::al */, $noreg + renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3 + + bb.1: + successors: %bb.1(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12 + + renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg + renamable $q0 = MVE_VSHR_immu16 killed renamable $q0, 11, 0, $noreg, undef renamable $q0 + $q1 = MVE_VORR $q0, $q0, 0, $noreg, undef $q1 + MVE_VPST 8, implicit $vpr + renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr + renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr + MVE_VPST 2, implicit $vpr + renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg + $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + MVE_VPST 1, implicit $vpr + renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr + renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr + tB %bb.2, 14 /* CC::al */, $noreg + + bb.2: + successors: %bb.3(0x04000000), %bb.0(0x7c000000) + liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12 + + renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg :: (load (s128) from %stack.0, align 8) + renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg + renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg + renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg + renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg + renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg + tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr + tBcc %bb.0, 1 /* CC::ne */, killed $cpsr + + bb.3: + $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg + $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15 + $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg + $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc + +... Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir @@ -437,16 +437,17 @@ ; CHECK: successors: %bb.2(0x80000000) ; CHECK: liveins: $lr, $r0, $r1, $r2 ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.3(0x04000000), %bb.2(0x7c000000) - ; CHECK: liveins: $lr, $q1, $r0, $r1, $r2 - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: liveins: $lr, $q1, $q2, $r0, $r1, $r2 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q2, 0, $noreg, undef $q0 ; CHECK: renamable $vpr = MVE_VCTP32 $r2, 0, $noreg ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) ; CHECK: renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv1, align 4) ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q1 = nsw MVE_VMULi32 renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg @@ -485,12 +486,13 @@ liveins: $lr, $r0, $r1, $r2 renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 bb.2.vector.body: successors: %bb.3(0x04000000), %bb.2(0x7c000000) - liveins: $lr, $q1, $r0, $r1, $r2 + liveins: $lr, $q1, $q2, $r0, $r1, $r2 - $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + $q0 = MVE_VORR killed $q1, $q2, 0, $noreg, undef $q0 renamable $vpr = MVE_VCTP32 $r2, 0, $noreg MVE_VPST 4, implicit $vpr renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr :: (load (s128) from %ir.lsr.iv24, align 4) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir @@ -135,13 +135,14 @@ ; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3 = tLEApcrel %const.0, 14 /* CC::al */, $noreg ; CHECK: renamable $r12 = t2LSRri killed renamable $r12, 2, 14 /* CC::al */, $noreg, $noreg - ; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + ; CHECK: renamable $q0 = MVE_VLDRWU32 renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + ; CHECK: renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) ; CHECK: renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14 /* CC::al */, $noreg, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 ; CHECK: renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg - ; CHECK: $q1 = MVE_VORR killed $q0, killed $q0, 0, $noreg, undef $q1 + ; CHECK: $q1 = MVE_VORR killed $q0, killed $q1, 0, $noreg, undef $q1 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) @@ -186,16 +187,17 @@ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, renamable $r12, 27, 14, $noreg, $noreg renamable $r3 = tLEApcrel %const.0, 14, $noreg renamable $r12 = t2LSRri killed renamable $r12, 2, 14, $noreg, $noreg - renamable $q0 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + renamable $q0 = MVE_VLDRWU32 renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) + renamable $q1 = MVE_VLDRWU32 killed renamable $r3, 0, 0, $noreg :: (load (s128) from constant-pool) renamable $r3 = t2SUBrs renamable $r2, killed renamable $r12, 26, 14, $noreg, $noreg $lr = t2DoLoopStart renamable $lr bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - liveins: $lr, $q0, $r0, $r1, $r2, $r3 + liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3 renamable $vpr = MVE_VCTP16 renamable $r2, 0, $noreg - $q1 = MVE_VORR killed $q0, $q0, 0, $noreg, undef $q1 + $q1 = MVE_VORR killed $q0, $q1, 0, $noreg, undef $q1 MVE_VPST 4, implicit $vpr renamable $r0, renamable $q0 = MVE_VLDRBU16_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv19, align 1) renamable $r1, renamable $q2 = MVE_VLDRBU16_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv2022, align 1) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir @@ -129,6 +129,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg @@ -138,14 +139,14 @@ ; CHECK: $r3 = tMOVr $r2, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3, $r12 + ; CHECK: liveins: $q1, $q2, $r0, $r1, $r2, $r3, $r12 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q2, 0, $noreg, undef $q0 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: $lr = tMOVr $r12, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q1 = nsw MVE_VMULi32 renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 @@ -178,6 +179,7 @@ frame-setup CFI_INSTRUCTION offset $r7, -8 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg @@ -188,10 +190,10 @@ bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - liveins: $q1, $r0, $r1, $r2, $r3, $r12 + liveins: $q1, $q2, $r0, $r1, $r2, $r3, $r12 renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg - $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + $q0 = MVE_VORR killed $q1, $q2, 0, $noreg, undef $q0 MVE_VPST 4, implicit $vpr renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir =================================================================== --- llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir @@ -121,6 +121,7 @@ ; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8 ; CHECK: renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 ; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg ; CHECK: renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg @@ -129,14 +130,14 @@ ; CHECK: $r3 = tMOVr killed $r12, 14 /* CC::al */, $noreg ; CHECK: bb.2.vector.body: ; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - ; CHECK: liveins: $q1, $r0, $r1, $r2, $r3 + ; CHECK: liveins: $q1, $q2, $r0, $r1, $r2, $r3 ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - ; CHECK: $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, undef $q0 + ; CHECK: $q0 = MVE_VORR killed $q1, killed $q2, 0, $noreg, undef $q0 ; CHECK: MVE_VPST 4, implicit $vpr ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) ; CHECK: renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) ; CHECK: $lr = tMOVr $r3, 14 /* CC::al */, $noreg - ; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 + ; CHECK: renamable $q1 = nsw MVE_VMULi32 renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 ; CHECK: renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14 /* CC::al */, $noreg ; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg ; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1 @@ -166,6 +167,7 @@ frame-setup CFI_INSTRUCTION offset $r7, -8 renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1 + renamable $q2 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q2 renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg @@ -175,15 +177,15 @@ bb.2.vector.body: successors: %bb.2(0x7c000000), %bb.3(0x04000000) - liveins: $q1, $r0, $r1, $r2, $r3 + liveins: $q1, $q2, $r0, $r1, $r2, $r3 renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg - $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, undef $q0 + $q0 = MVE_VORR killed $q1, $q2, 0, $noreg, undef $q0 MVE_VPST 4, implicit $vpr renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load (s64) from %ir.lsr.iv17, align 2) renamable $r1, renamable $q2 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr :: (load (s64) from %ir.lsr.iv1820, align 2) $lr = tMOVr $r3, 14, $noreg - renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 + renamable $q1 = nsw MVE_VMULi32 renamable $q2, killed renamable $q1, 0, $noreg, undef renamable $q1 renamable $r3, dead $cpsr = nsw tSUBi8 killed $r3, 1, 14, $noreg renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q0, 0, $noreg, undef renamable $q1