diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -169,6 +169,7 @@ Instruction *visitLandingPadInst(LandingPadInst &LI); Instruction *visitVAEndInst(VAEndInst &I); Value *pushFreezeToPreventPoisonFromPropagating(FreezeInst &FI); + Instruction *freezeAllUsesOfArgument(FreezeInst &FI); Instruction *visitFreeze(FreezeInst &I); /// Specify what to return for unhandled instructions. diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -3570,12 +3570,43 @@ return OrigOp; } +Instruction *InstCombinerImpl::freezeAllUsesOfArgument(FreezeInst &FI) { + Argument *Arg = dyn_cast(FI.getOperand(0)); + assert(Arg && "expected an argument"); + + Instruction *InsertBefore = nullptr; + for (auto *U : Arg->users()) { + auto *UI = dyn_cast(U); + if (!UI) + continue; + + auto *BB = UI->getParent(); + if (!BB->isEntryBlock()) + continue; + + if (!InsertBefore || DT.dominates(UI, InsertBefore)) + InsertBefore = UI; + } + if (!InsertBefore) + InsertBefore = FI.getFunction()->getEntryBlock().getTerminator(); + + FreezeInst *NewFI = new FreezeInst(PoisonValue::get(Arg->getType()), + Arg->getName() + ".fr", InsertBefore); + Arg->replaceAllUsesWith(NewFI); + NewFI->setOperand(0, Arg); + return replaceInstUsesWith(FI, NewFI); +} + Instruction *InstCombinerImpl::visitFreeze(FreezeInst &I) { Value *Op0 = I.getOperand(0); if (Value *V = SimplifyFreezeInst(Op0, SQ.getWithInstruction(&I))) return replaceInstUsesWith(I, V); + // If I is freeze(arg), replace all uses of arg to freeze(arg). + if (dyn_cast(Op0) && !Op0->hasOneUse()) + return freezeAllUsesOfArgument(I); + // freeze (phi const, x) --> phi const, (freeze x) if (auto *PN = dyn_cast(Op0)) { if (Instruction *NV = foldOpIntoPhi(I, PN)) diff --git a/llvm/test/Transforms/InstCombine/freeze.ll b/llvm/test/Transforms/InstCombine/freeze.ll --- a/llvm/test/Transforms/InstCombine/freeze.ll +++ b/llvm/test/Transforms/InstCombine/freeze.ll @@ -135,3 +135,53 @@ %v4.fr = freeze i32 %v4 ret i32 %v4.fr } + +; If freeze is applied to function argument, replace all +; uses of arg to freeze(arg). + +define void @argument_freeze_test1(i32 %arg) { +; CHECK-LABEL: @argument_freeze_test1( +; CHECK-NEXT: [[ARG_FR1:%.*]] = freeze i32 [[ARG:%.*]] +; CHECK-NEXT: call void @use_i32(i32 [[ARG_FR1]]) +; CHECK-NEXT: call void @use_i32(i32 [[ARG_FR1]]) +; CHECK-NEXT: ret void +; + call void @use_i32(i32 %arg) + %arg.fr = freeze i32 %arg + call void @use_i32(i32 %arg.fr) + ret void +} + +define void @argument_freeze_test2(i32 %arg) { +; CHECK-LABEL: @argument_freeze_test2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ARG_FR1:%.*]] = freeze i32 [[ARG:%.*]] +; CHECK-NEXT: call void @use_i32(i32 [[ARG_FR1]]) +; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[ARG_FR1]], 0 +; CHECK-NEXT: br i1 [[COND]], label [[BB0:%.*]], label [[BB1:%.*]] +; CHECK: bb0: +; CHECK-NEXT: call void @use_i32(i32 [[ARG_FR1]]) +; CHECK-NEXT: br label [[END:%.*]] +; CHECK: bb1: +; CHECK-NEXT: call void @use_i32(i32 [[ARG_FR1]]) +; CHECK-NEXT: br label [[END]] +; CHECK: end: +; CHECK-NEXT: ret void +; +entry: + call void @use_i32(i32 %arg) + %cond = icmp eq i32 %arg, 0 + br i1 %cond, label %bb0, label %bb1 + +bb0: + %arg.fr = freeze i32 %arg + call void @use_i32(i32 %arg.fr) + br label %end + +bb1: + call void @use_i32(i32 %arg) + br label %end + +end: + ret void +} diff --git a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll --- a/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/vector-reductions-logical.ll @@ -7,8 +7,8 @@ define float @test_merge_allof_v4sf(<4 x float> %t) { ; CHECK-LABEL: @test_merge_allof_v4sf( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] -; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x float> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR7]], zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1 ; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]] @@ -16,12 +16,11 @@ ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[LOR_LHS_FALSE]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret float [[COMMON_RET_OP]] ; CHECK: lor.lhs.false: -; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]] -; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], +; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR7]], ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR7]], <4 x float> poison, <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR7]] ; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0 ; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] ; CHECK-NEXT: br label [[COMMON_RET]] @@ -91,22 +90,22 @@ define float @test_merge_anyof_v4sf(<4 x float> %t) { ; CHECK-LABEL: @test_merge_anyof_v4sf( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T:%.*]], i32 3 -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T]], i32 2 -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T]], i32 0 -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T]] -; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x float> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T_FR7]], i32 3 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T_FR7]], i32 2 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T_FR7]], i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T_FR7]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR7]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 ; CHECK-NEXT: [[CMP19:%.*]] = fcmp ogt float [[TMP3]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP19]] +; CHECK-NEXT: [[OR_COND3:%.*]] = or i1 [[TMP6]], [[CMP19]] ; CHECK-NEXT: [[CMP24:%.*]] = fcmp ogt float [[TMP2]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP24]] +; CHECK-NEXT: [[OR_COND4:%.*]] = or i1 [[OR_COND3]], [[CMP24]] ; CHECK-NEXT: [[CMP29:%.*]] = fcmp ogt float [[TMP1]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP29]] +; CHECK-NEXT: [[OR_COND5:%.*]] = or i1 [[OR_COND4]], [[CMP29]] ; CHECK-NEXT: [[CMP34:%.*]] = fcmp ogt float [[TMP0]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP34]] +; CHECK-NEXT: [[OR_COND6:%.*]] = or i1 [[OR_COND5]], [[CMP34]] ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]] ; CHECK-NEXT: ret float [[RETVAL_0]] @@ -176,8 +175,8 @@ define float @test_separate_allof_v4sf(<4 x float> %t) { ; CHECK-LABEL: @test_separate_allof_v4sf( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T:%.*]] -; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x float> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = fcmp olt <4 x float> [[T_FR7]], zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1 ; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]] @@ -185,12 +184,11 @@ ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi float [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0.000000e+00, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret float [[COMMON_RET_OP]] ; CHECK: if.end: -; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x float> [[T]] -; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR6]], +; CHECK-NEXT: [[TMP3:%.*]] = fcmp ogt <4 x float> [[T_FR7]], ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x float> [[T_FR7]], <4 x float> poison, <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = fadd <4 x float> [[SHIFT]], [[T_FR7]] ; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x float> [[TMP6]], i32 0 ; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], float 0.000000e+00, float [[ADD]] ; CHECK-NEXT: br label [[COMMON_RET]] @@ -263,22 +261,22 @@ define float @test_separate_anyof_v4sf(<4 x float> %t) { ; CHECK-LABEL: @test_separate_anyof_v4sf( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T:%.*]], i32 3 -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T]], i32 2 -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T]], i32 0 -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x float> [[T]] -; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR]], zeroinitializer +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x float> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x float> [[T_FR7]], i32 3 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x float> [[T_FR7]], i32 2 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x float> [[T_FR7]], i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[T_FR7]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = fcmp olt <4 x float> [[T_FR7]], zeroinitializer ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 ; CHECK-NEXT: [[CMP18:%.*]] = fcmp ogt float [[TMP3]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP18]] +; CHECK-NEXT: [[OR_COND3:%.*]] = or i1 [[TMP6]], [[CMP18]] ; CHECK-NEXT: [[CMP23:%.*]] = fcmp ogt float [[TMP2]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP23]] +; CHECK-NEXT: [[OR_COND4:%.*]] = or i1 [[OR_COND3]], [[CMP23]] ; CHECK-NEXT: [[CMP28:%.*]] = fcmp ogt float [[TMP1]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP28]] +; CHECK-NEXT: [[OR_COND5:%.*]] = or i1 [[OR_COND4]], [[CMP28]] ; CHECK-NEXT: [[CMP33:%.*]] = fcmp ogt float [[TMP0]], 1.000000e+00 -; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP33]] +; CHECK-NEXT: [[OR_COND6:%.*]] = or i1 [[OR_COND5]], [[CMP33]] ; CHECK-NEXT: [[ADD:%.*]] = fadd float [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[ADD]] ; CHECK-NEXT: ret float [[RETVAL_0]] @@ -351,20 +349,19 @@ define float @test_merge_allof_v4si(<4 x i32> %t) { ; CHECK-LABEL: @test_merge_allof_v4si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] -; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x i32> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR7]], ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1 ; CHECK-NEXT: br i1 [[TMP2]], label [[RETURN:%.*]], label [[LOR_LHS_FALSE:%.*]] ; CHECK: lor.lhs.false: -; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR6]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR7]], ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1 ; CHECK-NEXT: br i1 [[TMP5]], label [[RETURN]], label [[IF_END:%.*]] ; CHECK: if.end: -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR7]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T_FR7]] ; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0 ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float ; CHECK-NEXT: br label [[RETURN]] @@ -430,22 +427,22 @@ define float @test_merge_anyof_v4si(<4 x i32> %t) { ; CHECK-LABEL: @test_merge_anyof_v4si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[T:%.*]], i32 3 -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[T]], i32 2 -; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[T]], i32 1 -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[T]], i32 0 -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T]] -; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x i32> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i32> [[T_FR7]], i32 3 +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[T_FR7]], i32 2 +; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[T_FR7]], i32 1 +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[T_FR7]], i32 0 +; CHECK-NEXT: [[TMP4:%.*]] = icmp slt <4 x i32> [[T_FR7]], ; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i1> [[TMP4]] to i4 ; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i4 [[TMP5]], 0 ; CHECK-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP3]], 255 -; CHECK-NEXT: [[OR_COND3:%.*]] = select i1 [[TMP6]], i1 true, i1 [[CMP11]] +; CHECK-NEXT: [[OR_COND3:%.*]] = or i1 [[TMP6]], [[CMP11]] ; CHECK-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP2]], 255 -; CHECK-NEXT: [[OR_COND4:%.*]] = select i1 [[OR_COND3]], i1 true, i1 [[CMP14]] +; CHECK-NEXT: [[OR_COND4:%.*]] = or i1 [[OR_COND3]], [[CMP14]] ; CHECK-NEXT: [[CMP17:%.*]] = icmp sgt i32 [[TMP1]], 255 -; CHECK-NEXT: [[OR_COND5:%.*]] = select i1 [[OR_COND4]], i1 true, i1 [[CMP17]] +; CHECK-NEXT: [[OR_COND5:%.*]] = or i1 [[OR_COND4]], [[CMP17]] ; CHECK-NEXT: [[CMP20:%.*]] = icmp sgt i32 [[TMP0]], 255 -; CHECK-NEXT: [[OR_COND6:%.*]] = select i1 [[OR_COND5]], i1 true, i1 [[CMP20]] +; CHECK-NEXT: [[OR_COND6:%.*]] = or i1 [[OR_COND5]], [[CMP20]] ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]] ; CHECK-NEXT: [[CONV:%.*]] = sitofp i32 [[ADD]] to float ; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[OR_COND6]], float 0.000000e+00, float [[CONV]] @@ -509,8 +506,8 @@ define i32 @test_separate_allof_v4si(<4 x i32> %t) { ; CHECK-LABEL: @test_separate_allof_v4si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] -; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[T_FR7:%.*]] = freeze <4 x i32> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR7]], ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i4 [[TMP1]], -1 ; CHECK-NEXT: br i1 [[TMP2]], label [[COMMON_RET:%.*]], label [[IF_END:%.*]] @@ -518,12 +515,11 @@ ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK: if.end: -; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]] -; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR6]], +; CHECK-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i32> [[T_FR7]], ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i1> [[TMP3]] to i4 ; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i4 [[TMP4]], -1 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR7]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = add nsw <4 x i32> [[SHIFT]], [[T_FR7]] ; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP6]], i32 0 ; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[TMP5]], i32 0, i32 [[ADD]] ; CHECK-NEXT: br label [[COMMON_RET]] @@ -588,8 +584,8 @@ define i32 @test_separate_anyof_v4si(<4 x i32> %t) { ; CHECK-LABEL: @test_separate_anyof_v4si( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[T_FR:%.*]] = freeze <4 x i32> [[T:%.*]] -; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR]], +; CHECK-NEXT: [[T_FR8:%.*]] = freeze <4 x i32> [[T:%.*]] +; CHECK-NEXT: [[TMP0:%.*]] = icmp slt <4 x i32> [[T_FR8]], ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[TMP0]] to i4 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i4 [[TMP1]], 0 ; CHECK-NEXT: br i1 [[DOTNOT]], label [[IF_END:%.*]], label [[COMMON_RET:%.*]] @@ -597,12 +593,11 @@ ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], [[IF_END]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]] ; CHECK: if.end: -; CHECK-NEXT: [[T_FR6:%.*]] = freeze <4 x i32> [[T]] -; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR6]], +; CHECK-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[T_FR8]], ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i1> [[TMP2]] to i4 ; CHECK-NEXT: [[DOTNOT7:%.*]] = icmp eq i4 [[TMP3]], 0 -; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T]], <4 x i32> poison, <4 x i32> -; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T]] +; CHECK-NEXT: [[SHIFT:%.*]] = shufflevector <4 x i32> [[T_FR8]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw <4 x i32> [[SHIFT]], [[T_FR8]] ; CHECK-NEXT: [[ADD:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0 ; CHECK-NEXT: [[SPEC_SELECT]] = select i1 [[DOTNOT7]], i32 [[ADD]], i32 0 ; CHECK-NEXT: br label [[COMMON_RET]]