Index: include/llvm/CodeGen/MIRYamlMapping.h
===================================================================
--- include/llvm/CodeGen/MIRYamlMapping.h
+++ include/llvm/CodeGen/MIRYamlMapping.h
@@ -61,6 +61,13 @@
   unsigned Alignment = 0;
   bool ExposesReturnsTwice = false;
   bool HasInlineAsm = false;
+  // Register information
+  bool IsSSA = false;
+  bool TracksRegLiveness = false;
+  bool TracksSubRegLiveness = false;
+  // TODO: Serialize virtual register definitions.
+  // TODO: Serialize the various register masks.
+  // TODO: Serialize live in registers.
 
   std::vector<MachineBasicBlock> BasicBlocks;
 };
@@ -71,6 +78,10 @@
     YamlIO.mapOptional("alignment", MF.Alignment);
     YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
     YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
+    YamlIO.mapOptional("isSSA", MF.IsSSA);
+    YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
+    YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
+
     YamlIO.mapOptional("body", MF.BasicBlocks);
   }
 };
Index: lib/CodeGen/MIRParser/MIRParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIRParser.cpp
+++ lib/CodeGen/MIRParser/MIRParser.cpp
@@ -19,6 +19,7 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/AsmParser/Parser.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/DiagnosticInfo.h"
@@ -83,6 +84,9 @@
   bool initializeMachineBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB,
                                    const yaml::MachineBasicBlock &YamlMBB);
 
+  bool initializeRegisterInfo(MachineRegisterInfo &RegInfo,
+                              const yaml::MachineFunction &YamlMF);
+
 private:
   /// Return a MIR diagnostic converted from an LLVM assembly diagnostic.
   SMDiagnostic diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
@@ -207,6 +211,9 @@
     MF.setAlignment(YamlMF.Alignment);
   MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
   MF.setHasInlineAsm(YamlMF.HasInlineAsm);
+  if (initializeRegisterInfo(MF.getRegInfo(), YamlMF))
+    return true;
+
   const auto &F = *MF.getFunction();
   for (const auto &YamlMBB : YamlMF.BasicBlocks) {
     const BasicBlock *BB = nullptr;
@@ -245,6 +252,18 @@
   return false;
 }
 
+bool MIRParserImpl::initializeRegisterInfo(
+    MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {
+  assert(RegInfo.isSSA());
+  if (!YamlMF.IsSSA)
+    RegInfo.leaveSSA();
+  assert(RegInfo.tracksLiveness());
+  if (!YamlMF.TracksRegLiveness)
+    RegInfo.invalidateLiveness();
+  RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);
+  return false;
+}
+
 SMDiagnostic MIRParserImpl::diagFromLLVMAssemblyDiag(const SMDiagnostic &Error,
                                                      SMRange SourceRange) {
   assert(SourceRange.isValid());
Index: lib/CodeGen/MIRPrinter.cpp
===================================================================
--- lib/CodeGen/MIRPrinter.cpp
+++ lib/CodeGen/MIRPrinter.cpp
@@ -15,6 +15,7 @@
 #include "MIRPrinter.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/IR/BasicBlock.h"
 #include "llvm/IR/Module.h"
@@ -38,6 +39,8 @@
 
   void print(const MachineFunction &MF);
 
+  void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
+
   void convert(yaml::MachineBasicBlock &YamlMBB, const MachineBasicBlock &MBB);
 };
 
@@ -77,6 +80,7 @@
   YamlMF.Alignment = MF.getAlignment();
   YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
   YamlMF.HasInlineAsm = MF.hasInlineAsm();
+  convert(YamlMF, MF.getRegInfo());
   for (const auto &MBB : MF) {
     yaml::MachineBasicBlock YamlMBB;
     convert(YamlMBB, MBB);
@@ -86,6 +90,13 @@
   Out << YamlMF;
 }
 
+void MIRPrinter::convert(yaml::MachineFunction &MF,
+                         const MachineRegisterInfo &RegInfo) {
+  MF.IsSSA = RegInfo.isSSA();
+  MF.TracksRegLiveness = RegInfo.tracksLiveness();
+  MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
+}
+
 void MIRPrinter::convert(yaml::MachineBasicBlock &YamlMBB,
                          const MachineBasicBlock &MBB) {
   // TODO: Serialize unnamed BB references.
Index: test/CodeGen/MIR/machine-function.mir
===================================================================
--- test/CodeGen/MIR/machine-function.mir
+++ test/CodeGen/MIR/machine-function.mir
@@ -25,7 +25,7 @@
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
 # CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
 name:            foo
 ...
 ---
@@ -33,7 +33,7 @@
 # CHECK-NEXT: alignment:
 # CHECK-NEXT: exposesReturnsTwice: false
 # CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
 name:            bar
 ...
 ---
@@ -41,7 +41,7 @@
 # CHECK-NEXT: alignment: 8
 # CHECK-NEXT: exposesReturnsTwice: false
 # CHECK-NEXT: hasInlineAsm: false
-# CHECK-NEXT: ...
+# CHECK: ...
 name:            func
 alignment:       8
 ...
@@ -50,7 +50,7 @@
 # CHECK-NEXT: alignment: 16
 # CHECK-NEXT: exposesReturnsTwice: true
 # CHECK-NEXT: hasInlineAsm: true
-# CHECK-NEXT: ...
+# CHECK: ...
 name:            func2
 alignment:       16
 exposesReturnsTwice: true
Index: test/CodeGen/MIR/register-info.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/register-info.mir
@@ -0,0 +1,36 @@
+# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s
+# This test ensures that the MIR parser parses machine register info properties
+# correctly.
+
+--- |
+
+  define i32 @foo() {
+  entry:
+    ret i32 0
+  }
+
+  define i32 @bar() {
+  start:
+    ret i32 0
+  }
+
+...
+---
+# CHECK: name: foo
+# CHECK:      isSSA: false
+# CHECK-NEXT: tracksRegLiveness: false
+# CHECK-NEXT: tracksSubRegLiveness: false
+# CHECK: ...
+name:            foo
+...
+---
+# CHECK: name: bar
+# CHECK:      isSSA: false
+# CHECK-NEXT: tracksRegLiveness: true
+# CHECK-NEXT: tracksSubRegLiveness: true
+# CHECK: ...
+name: bar
+isSSA: false
+tracksRegLiveness: true
+tracksSubRegLiveness: true
+...